!_TAG_FILE_FORMAT	2	/extended format; --format=1 will not append ;" to lines/
!_TAG_FILE_SORTED	1	/0=unsorted, 1=sorted, 2=foldcase/
!_TAG_PROGRAM_AUTHOR	Darren Hiebert	/dhiebert@users.sourceforge.net/
!_TAG_PROGRAM_NAME	Exuberant Ctags	//
!_TAG_PROGRAM_URL	http://ctags.sourceforge.net	/official site/
!_TAG_PROGRAM_VERSION	5.9~svn20110310	//
ACCESS_CMAC	mac.h	373;"	d
ADDC_T_AVG	rtw8852a_rfk.c	384;"	d	file:
ADDR_CAM_BASE_ADDR	mac.h	235;"	d
ADDR_CAM_ENT_SIZE	mac.h	11;"	d
ARRAY_SIZE	sar.c	/^	      ARRAY_SIZE(rtw89_common_sar_freq_ranges));$/;"	v
AX_RXTIMER_UNIT_128US	pci.h	291;"	d
AX_RXTIMER_UNIT_256US	pci.h	292;"	d
AX_RXTIMER_UNIT_512US	pci.h	293;"	d
AX_RXTIMER_UNIT_64US	pci.h	290;"	d
BACKUP_BB_REGS_NR	rtw8852a_rfk.c	91;"	d	file:
BACKUP_RF_REGS_NR	rtw8852a_rfk.c	92;"	d	file:
BA_CAM_BASE_ADDR	mac.h	237;"	d
BCN_ERLY_DEF	mac.c	2743;"	d	file:
BCN_ERLY_SET_DLY	mac.c	2749;"	d	file:
BCN_HOLD_DEF	mac.c	2745;"	d	file:
BCN_IE_CAM0_BASE_ADDR	mac.h	238;"	d
BCN_IE_CAM1_BASE_ADDR	mac.h	242;"	d
BCN_INTERVAL	mac.c	2742;"	d	file:
BCN_MASK_DEF	mac.c	2746;"	d	file:
BCN_SETUP_DEF	mac.c	2744;"	d	file:
BCN_SET_UNIT	mac.c	2748;"	d	file:
BDRAM_MAX_MASK	pci.h	198;"	d
BDRAM_MIN_MASK	pci.h	199;"	d
BDRAM_SIDX_MASK	pci.h	197;"	d
BFRP_RX_STANDBY_TIMER	reg.h	1208;"	d
BSSID_CAM_BASE_ADDR	mac.h	236;"	d
BSSID_CAM_ENT_SIZE	mac.h	12;"	d
BTCRPT_VER	core.h	1274;"	d
BTC_A2DP_LEGACY	coex.c	/^	BTC_A2DP_LEGACY = 0,$/;"	e	enum:btc_bt_a2dp_type	file:
BTC_A2DP_TWS_RELAY	coex.c	/^	BTC_A2DP_TWS_RELAY = 2,$/;"	e	enum:btc_bt_a2dp_type	file:
BTC_A2DP_TWS_SNIFF	coex.c	/^	BTC_A2DP_TWS_SNIFF = 1,$/;"	e	enum:btc_bt_a2dp_type	file:
BTC_ACT_BT_A2DP	coex.c	/^	BTC_ACT_BT_A2DP,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_A2DPSINK	coex.c	/^	BTC_ACT_BT_A2DPSINK,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_A2DP_HID	coex.c	/^	BTC_ACT_BT_A2DP_HID,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_A2DP_PAN	coex.c	/^	BTC_ACT_BT_A2DP_PAN,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_A2DP_PAN_HID	coex.c	/^	BTC_ACT_BT_A2DP_PAN_HID,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_HFP	coex.c	/^	BTC_ACT_BT_HFP,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_HID	coex.c	/^	BTC_ACT_BT_HID,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_IDLE	coex.c	/^	BTC_ACT_BT_IDLE,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_OFF	coex.c	/^	BTC_ACT_BT_OFF,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_PAN	coex.c	/^	BTC_ACT_BT_PAN,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_PAN_HID	coex.c	/^	BTC_ACT_BT_PAN_HID,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_RFK	coex.c	/^	BTC_ACT_BT_RFK,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_BT_WHQL	coex.c	/^	BTC_ACT_BT_WHQL,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_EXT_BIT	coex.c	/^	BTC_ACT_EXT_BIT = BIT(14),$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_FREERUN	coex.c	/^	BTC_ACT_FREERUN,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_LAST	coex.c	/^	BTC_ACT_LAST,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_NONE	coex.c	/^	BTC_ACT_NONE = 100,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_NUM	coex.c	/^	BTC_ACT_NUM = BTC_ACT_LAST - BTC_ACT_NONE,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_25G_MCC	coex.c	/^	BTC_ACT_WL_25G_MCC,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_AP	coex.c	/^	BTC_ACT_WL_2G_AP,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_GC	coex.c	/^	BTC_ACT_WL_2G_GC,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_GO	coex.c	/^	BTC_ACT_WL_2G_GO,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_MCC	coex.c	/^	BTC_ACT_WL_2G_MCC,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_NAN	coex.c	/^	BTC_ACT_WL_2G_NAN,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_2G_SCC	coex.c	/^	BTC_ACT_WL_2G_SCC,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_5G	coex.c	/^	BTC_ACT_WL_5G,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_IDLE	coex.c	/^	BTC_ACT_WL_IDLE,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_INIT	coex.c	/^	BTC_ACT_WL_INIT,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_NC	coex.c	/^	BTC_ACT_WL_NC,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_OFF	coex.c	/^	BTC_ACT_WL_OFF,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_ONLY	coex.c	/^	BTC_ACT_WL_ONLY,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_OTHER	coex.c	/^	BTC_ACT_WL_OTHER,$/;"	e	enum:btc_reason_and_action	file:
BTC_ACT_WL_RFK	coex.c	/^	BTC_ACT_WL_RFK,$/;"	e	enum:btc_reason_and_action	file:
BTC_ANTTYPE_MAX	coex.h	/^	BTC_ANTTYPE_MAX$/;"	e	enum:btc_ant
BTC_ANT_BRFK	coex.c	/^	BTC_ANT_BRFK,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_DEDICATED	coex.h	/^	BTC_ANT_DEDICATED,$/;"	e	enum:btc_ant
BTC_ANT_FREERUN	coex.c	/^	BTC_ANT_FREERUN,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_MAX	coex.c	/^	BTC_ANT_MAX$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_SHARED	coex.h	/^	BTC_ANT_SHARED = 0,$/;"	e	enum:btc_ant
BTC_ANT_W25G	coex.c	/^	BTC_ANT_W25G,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_W2G	coex.c	/^	BTC_ANT_W2G,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_W5G	coex.c	/^	BTC_ANT_W5G,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_WINIT	coex.c	/^	BTC_ANT_WINIT,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_WOFF	coex.c	/^	BTC_ANT_WOFF,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_WONLY	coex.c	/^	BTC_ANT_WONLY,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_WPOWERON	coex.c	/^	BTC_ANT_WPOWERON = 0,$/;"	e	enum:btc_ant_phase	file:
BTC_ANT_WRFK	coex.c	/^	BTC_ANT_WRFK,$/;"	e	enum:btc_ant_phase	file:
BTC_BCNT_AFH	core.h	/^	BTC_BCNT_AFH,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_HIPRI_RX	core.h	/^	BTC_BCNT_HIPRI_RX,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_HIPRI_TX	core.h	/^	BTC_BCNT_HIPRI_TX,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_IGNOWL	core.h	/^	BTC_BCNT_IGNOWL,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_INFOSAME	core.h	/^	BTC_BCNT_INFOSAME,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_INFOUPDATE	core.h	/^	BTC_BCNT_INFOUPDATE,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_INQ	core.h	/^	BTC_BCNT_INQ,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_INQPAG	core.h	/^	BTC_BCNT_INQPAG,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_LOPRI_RX	core.h	/^	BTC_BCNT_LOPRI_RX,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_LOPRI_TX	core.h	/^	BTC_BCNT_LOPRI_TX,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_NUM	core.h	/^	BTC_BCNT_NUM$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_PAGE	core.h	/^	BTC_BCNT_PAGE,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_RATECHG	core.h	/^	BTC_BCNT_RATECHG,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_REENABLE	core.h	/^	BTC_BCNT_REENABLE,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_REINIT	core.h	/^	BTC_BCNT_REINIT,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_RELINK	core.h	/^	BTC_BCNT_RELINK,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_RETRY	core.h	/^	BTC_BCNT_RETRY = 0x0,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_RFK_FAIL	core.h	/^	BTC_BCNT_RFK_FAIL = 3,$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_RFK_GO	core.h	/^	BTC_BCNT_RFK_GO = 1,$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_RFK_MAX	core.h	/^	BTC_BCNT_RFK_MAX$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_RFK_REJECT	core.h	/^	BTC_BCNT_RFK_REJECT = 2,$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_RFK_REQ	core.h	/^	BTC_BCNT_RFK_REQ = 0,$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_RFK_TIMEOUT	core.h	/^	BTC_BCNT_RFK_TIMEOUT = 4,$/;"	e	enum:rtw89_btc_bt_rfk_counter
BTC_BCNT_ROLESW	core.h	/^	BTC_BCNT_ROLESW,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_SCBDREAD	core.h	/^	BTC_BCNT_SCBDREAD,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BCNT_SCBDUPDATE	core.h	/^	BTC_BCNT_SCBDUPDATE,$/;"	e	enum:rtw89_btc_bt_state_cnt
BTC_BLINK_NOCONNECT	coex.c	533;"	d	file:
BTC_BREAK_PARAM	reg.h	1428;"	d
BTC_BSCB_A2DP_ACT	coex.c	/^	BTC_BSCB_A2DP_ACT = BIT(4),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_ACT	coex.c	/^	BTC_BSCB_ACT = BIT(0),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_ALL	coex.c	/^	BTC_BSCB_ALL = GENMASK(30, 0),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_BT_CONNECT	coex.c	/^	BTC_BSCB_BT_CONNECT = BIT(16),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_BT_HILNA	coex.c	/^	BTC_BSCB_BT_HILNA = BIT(13),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_BT_S1	coex.c	/^	BTC_BSCB_BT_S1 = BIT(3),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_LPS	coex.c	/^	BTC_BSCB_LPS = BIT(7),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_ON	coex.c	/^	BTC_BSCB_ON = BIT(1),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_PATCH_CODE	coex.c	/^	BTC_BSCB_PATCH_CODE = BIT(30),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_RFK_REQ	coex.c	/^	BTC_BSCB_RFK_REQ = BIT(6),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_RFK_RUN	coex.c	/^	BTC_BSCB_RFK_RUN = BIT(5),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_WHQL	coex.c	/^	BTC_BSCB_WHQL = BIT(2),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BSCB_WLRFK	coex.c	/^	BTC_BSCB_WLRFK = BIT(11),$/;"	e	enum:btc_b2w_scoreboard	file:
BTC_BTINFO_AUTO	coex.h	/^	BTC_BTINFO_AUTO = 0x27$/;"	e	enum:btc_bt_mailbox_id
BTC_BTINFO_H0	core.h	/^	BTC_BTINFO_H0,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_H1	core.h	/^	BTC_BTINFO_H1,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_H2	core.h	/^	BTC_BTINFO_H2,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_H3	core.h	/^	BTC_BTINFO_H3,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_L0	core.h	/^	BTC_BTINFO_L0 = 0,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_L1	core.h	/^	BTC_BTINFO_L1,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_L2	core.h	/^	BTC_BTINFO_L2,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_L3	core.h	/^	BTC_BTINFO_L3,$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_MAX	core.h	/^	BTC_BTINFO_MAX$/;"	e	enum:rtw89_btc_btinfo
BTC_BTINFO_REPLY	coex.h	/^	BTC_BTINFO_REPLY = 0x23,$/;"	e	enum:btc_bt_mailbox_id
BTC_BT_A2DP	core.h	/^	BTC_BT_A2DP = BIT(2),$/;"	e	enum:rtw89_btc_bt_profile
BTC_BT_AFH_GROUP	core.h	1090;"	d
BTC_BT_ALONE	coex.h	/^	BTC_BT_ALONE = 0,$/;"	e	enum:btc_bt_btg
BTC_BT_BTG	coex.h	/^	BTC_BT_BTG$/;"	e	enum:btc_bt_btg
BTC_BT_HFP	core.h	/^	BTC_BT_HFP = BIT(0),$/;"	e	enum:rtw89_btc_bt_profile
BTC_BT_HID	core.h	/^	BTC_BT_HID = BIT(1),$/;"	e	enum:rtw89_btc_bt_profile
BTC_BT_MAX_GROUP	coex.h	/^	BTC_BT_MAX_GROUP,$/;"	e	enum:btc_bt_trs
BTC_BT_NOPROFILE	core.h	/^	BTC_BT_NOPROFILE = 0,$/;"	e	enum:rtw89_btc_bt_profile
BTC_BT_PAN	core.h	/^	BTC_BT_PAN = BIT(3),$/;"	e	enum:rtw89_btc_bt_profile
BTC_BT_RSSI_THMAX	core.h	1089;"	d
BTC_BT_RX_GROUP	coex.h	/^	BTC_BT_RX_GROUP = 0x3,$/;"	e	enum:btc_bt_trs
BTC_BT_RX_NORMAL_LVL	coex.c	1532;"	d	file:
BTC_BT_SS_GROUP	coex.h	/^	BTC_BT_SS_GROUP = 0x0,$/;"	e	enum:btc_bt_trs
BTC_BT_TX_GROUP	coex.h	/^	BTC_BT_TX_GROUP = 0x2,$/;"	e	enum:btc_bt_trs
BTC_CHK_HANG_MAX	coex.c	3388;"	d	file:
BTC_CHK_HANG_MAX	coex.c	600;"	d	file:
BTC_CHK_WLSLOT_DRIFT_MAX	coex.c	599;"	d	file:
BTC_COEX_INFO_ALL	coex.c	/^	BTC_COEX_INFO_ALL = GENMASK(7, 0),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_BT	coex.c	/^	BTC_COEX_INFO_BT = BIT(2),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_CX	coex.c	/^	BTC_COEX_INFO_CX = BIT(0),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_DM	coex.c	/^	BTC_COEX_INFO_DM = BIT(3),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_MREG	coex.c	/^	BTC_COEX_INFO_MREG = BIT(4),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_SUMMARY	coex.c	/^	BTC_COEX_INFO_SUMMARY = BIT(5),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_COEX_INFO_WL	coex.c	/^	BTC_COEX_INFO_WL = BIT(1),$/;"	e	enum:btc_coex_info_map_en	file:
BTC_CXP_AUTO	coex.c	/^	BTC_CXP_AUTO,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_AUTO2	coex.c	/^	BTC_CXP_AUTO2,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_AUTO2_TD2080	coex.c	/^	BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO2_TD3050	coex.c	/^	BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO2_TD3070	coex.c	/^	BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO2_TD5050	coex.c	/^	BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO2_TD6060	coex.c	/^	BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO2_TDW1B4	coex.c	/^	BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO_TD20200	coex.c	/^	BTC_CXP_AUTO_TD20200 = (BTC_CXP_AUTO << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO_TD50200	coex.c	/^	BTC_CXP_AUTO_TD50200 = (BTC_CXP_AUTO << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO_TD60200	coex.c	/^	BTC_CXP_AUTO_TD60200 = (BTC_CXP_AUTO << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_AUTO_TDW1B1	coex.c	/^	BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX	coex.c	/^	BTC_CXP_FIX,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_FIX_TD2030	coex.c	/^	BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD2060	coex.c	/^	BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD2080	coex.c	/^	BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD3030	coex.c	/^	BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD3060	coex.c	/^	BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD4010	coex.c	/^	BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD4020	coex.c	/^	BTC_CXP_FIX_TD4020 = (BTC_CXP_FIX << 8) | 9,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD5050	coex.c	/^	BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TD7010	coex.c	/^	BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_FIX_TDW1B1	coex.c	/^	BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_MAIN_MAX	coex.c	/^	BTC_CXP_MAIN_MAX$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_MANUAL	coex.c	/^	BTC_CXP_MANUAL,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_MASK	coex.c	402;"	d	file:
BTC_CXP_MAX	coex.c	/^	BTC_CXP_MAX = 0xffff$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF	coex.c	/^	BTC_CXP_OFF = 0,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_OFFB	coex.c	/^	BTC_CXP_OFFB,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_OFFB_BWB0	coex.c	/^	BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFFE	coex.c	/^	BTC_CXP_OFFE,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_OFFE_DEF	coex.c	/^	BTC_CXP_OFFE_DEF = (BTC_CXP_OFFE << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFFE_DEF2	coex.c	/^	BTC_CXP_OFFE_DEF2 = (BTC_CXP_OFFE << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_BT	coex.c	/^	BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_BWB0	coex.c	/^	BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 6,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_BWB1	coex.c	/^	BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 7,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_EQ0	coex.c	/^	BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_EQ1	coex.c	/^	BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_EQ2	coex.c	/^	BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_EQ3	coex.c	/^	BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_OFF_WL	coex.c	/^	BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO	coex.c	/^	BTC_CXP_PAUTO,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_PAUTO2	coex.c	/^	BTC_CXP_PAUTO2,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_PAUTO2_TD2080	coex.c	/^	BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO2_TD3050	coex.c	/^	BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO2_TD3070	coex.c	/^	BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO2_TD5050	coex.c	/^	BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO2_TD6060	coex.c	/^	BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO2_TDW1B4	coex.c	/^	BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO_TD20200	coex.c	/^	BTC_CXP_PAUTO_TD20200 = (BTC_CXP_PAUTO << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO_TD50200	coex.c	/^	BTC_CXP_PAUTO_TD50200 = (BTC_CXP_PAUTO << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO_TD60200	coex.c	/^	BTC_CXP_PAUTO_TD60200 = (BTC_CXP_PAUTO << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PAUTO_TDW1B1	coex.c	/^	BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX	coex.c	/^	BTC_CXP_PFIX,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CXP_PFIX_TD2030	coex.c	/^	BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TD2060	coex.c	/^	BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TD2080	coex.c	/^	BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TD3030	coex.c	/^	BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TD3070	coex.c	/^	BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TD5050	coex.c	/^	BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_PFIX_TDW1B1	coex.c	/^	BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6,$/;"	e	enum:btc_cx_poicy_type	file:
BTC_CXP_USERDEF0	coex.c	/^	BTC_CXP_USERDEF0,$/;"	e	enum:btc_cx_poicy_main_type	file:
BTC_CX_FW_OFFLOAD	coex.c	4542;"	d	file:
BTC_CYCLE_SLOT_MAX	core.h	1275;"	d
BTC_CYSTA_CHK_PERIOD	coex.c	837;"	d	file:
BTC_DBG_MAX1	core.h	1374;"	d
BTC_DCNT_B1	core.h	/^	BTC_DCNT_B1,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_B1_FREEZE	core.h	/^	BTC_DCNT_B1_FREEZE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_BTCNT_FREEZE	core.h	/^	BTC_DCNT_BTCNT_FREEZE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_CX_RUNINFO	core.h	/^	BTC_DCNT_CX_RUNINFO,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_CYCLE	core.h	/^	BTC_DCNT_CYCLE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_CYCLE_FREEZE	core.h	/^	BTC_DCNT_CYCLE_FREEZE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_NUM	core.h	/^	BTC_DCNT_NUM,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_RPT	core.h	/^	BTC_DCNT_RPT,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_RPT_FREEZE	core.h	/^	BTC_DCNT_RPT_FREEZE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_RUN	core.h	/^	BTC_DCNT_RUN = 0x0,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_SLOT_NONSYNC	core.h	/^	BTC_DCNT_SLOT_NONSYNC,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_TDMA_NONSYNC	core.h	/^	BTC_DCNT_TDMA_NONSYNC,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_W1	core.h	/^	BTC_DCNT_W1,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_W1_FREEZE	core.h	/^	BTC_DCNT_W1_FREEZE,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_WL_SLOT_DRIFT	core.h	/^	BTC_DCNT_WL_SLOT_DRIFT,$/;"	e	enum:rtw89_btc_dcnt
BTC_DCNT_WL_STA_LAST	core.h	/^	BTC_DCNT_WL_STA_LAST,$/;"	e	enum:rtw89_btc_dcnt
BTC_FREERUN_ANTISO_MIN	coex.c	531;"	d	file:
BTC_FWINFO_BUF	coex.c	596;"	d	file:
BTC_GNT_HW	coex.c	/^	BTC_GNT_HW	= 0,$/;"	e	enum:btc_gnt_state	file:
BTC_GNT_MAX	coex.c	/^	BTC_GNT_MAX$/;"	e	enum:btc_gnt_state	file:
BTC_GNT_SW_HI	coex.c	/^	BTC_GNT_SW_HI,$/;"	e	enum:btc_gnt_state	file:
BTC_GNT_SW_LO	coex.c	/^	BTC_GNT_SW_LO,$/;"	e	enum:btc_gnt_state	file:
BTC_HID_218	coex.c	/^	BTC_HID_218 = BIT(0),$/;"	e	enum:btc_bt_hid_type	file:
BTC_HID_418	coex.c	/^	BTC_HID_418 = BIT(1),$/;"	e	enum:btc_bt_hid_type	file:
BTC_HID_BLE	coex.c	/^	BTC_HID_BLE = BIT(2),$/;"	e	enum:btc_bt_hid_type	file:
BTC_HID_OTHER_LEGACY	coex.c	/^	BTC_HID_OTHER_LEGACY = BIT(5)$/;"	e	enum:btc_bt_hid_type	file:
BTC_HID_RCU	coex.c	/^	BTC_HID_RCU = BIT(3),$/;"	e	enum:btc_bt_hid_type	file:
BTC_HID_RCU_VOICE	coex.c	/^	BTC_HID_RCU_VOICE = BIT(4),$/;"	e	enum:btc_bt_hid_type	file:
BTC_LEAK_AP_TH	coex.c	836;"	d	file:
BTC_MAX_TX_RETRY_DEF	coex.c	/^	BTC_MAX_TX_RETRY_DEF = 31,$/;"	e	enum:btc_wl_max_tx_retry	file:
BTC_MAX_TX_RETRY_L1	coex.c	/^	BTC_MAX_TX_RETRY_L1 = 7,$/;"	e	enum:btc_wl_max_tx_retry	file:
BTC_MAX_TX_RETRY_L2	coex.c	/^	BTC_MAX_TX_RETRY_L2 = 15,$/;"	e	enum:btc_wl_max_tx_retry	file:
BTC_MAX_TX_TIME_DEF	coex.c	/^	BTC_MAX_TX_TIME_DEF = 5280$/;"	e	enum:btc_wl_max_tx_time	file:
BTC_MAX_TX_TIME_L1	coex.c	/^	BTC_MAX_TX_TIME_L1 = 500,$/;"	e	enum:btc_wl_max_tx_time	file:
BTC_MAX_TX_TIME_L2	coex.c	/^	BTC_MAX_TX_TIME_L2 = 1000,$/;"	e	enum:btc_wl_max_tx_time	file:
BTC_MAX_TX_TIME_L3	coex.c	/^	BTC_MAX_TX_TIME_L3 = 2000,$/;"	e	enum:btc_wl_max_tx_time	file:
BTC_MODE_BT	coex.h	/^	BTC_MODE_BT,$/;"	e	enum:btc_mode
BTC_MODE_MAX	coex.h	/^	BTC_MODE_MAX$/;"	e	enum:btc_mode
BTC_MODE_NORMAL	coex.h	/^	BTC_MODE_NORMAL,$/;"	e	enum:btc_mode
BTC_MODE_WL	coex.h	/^	BTC_MODE_WL,$/;"	e	enum:btc_mode
BTC_MODE_WLOFF	coex.h	/^	BTC_MODE_WLOFF,$/;"	e	enum:btc_mode
BTC_NCNT_CONTROL	core.h	/^	BTC_NCNT_CONTROL,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_CUSTOMERIZE	core.h	/^	BTC_NCNT_CUSTOMERIZE,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_FWINFO	core.h	/^	BTC_NCNT_FWINFO,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_INIT_COEX	core.h	/^	BTC_NCNT_INIT_COEX,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_NUM	core.h	/^	BTC_NCNT_NUM$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_POWER_OFF	core.h	/^	BTC_NCNT_POWER_OFF,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_POWER_ON	core.h	/^	BTC_NCNT_POWER_ON = 0x0,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_RADIO_STATE	core.h	/^	BTC_NCNT_RADIO_STATE,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_RFK_TIMEOUT	core.h	/^	BTC_NCNT_RFK_TIMEOUT,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_ROLE_INFO	core.h	/^	BTC_NCNT_ROLE_INFO,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_SCAN_FINISH	core.h	/^	BTC_NCNT_SCAN_FINISH,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_SCAN_START	core.h	/^	BTC_NCNT_SCAN_START,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_SHOW_COEX_INFO	core.h	/^	BTC_NCNT_SHOW_COEX_INFO,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_SPECIAL_PACKET	core.h	/^	BTC_NCNT_SPECIAL_PACKET,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_SWITCH_BAND	core.h	/^	BTC_NCNT_SWITCH_BAND,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_TIMER	core.h	/^	BTC_NCNT_TIMER,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_WL_RFK	core.h	/^	BTC_NCNT_WL_RFK,$/;"	e	enum:rtw89_btc_ncnt
BTC_NCNT_WL_STA	core.h	/^	BTC_NCNT_WL_STA,$/;"	e	enum:rtw89_btc_ncnt
BTC_NHM_CHK_INTVL	coex.c	4445;"	d	file:
BTC_PHY_0	coex.c	/^	BTC_PHY_0 = BIT(0),$/;"	e	enum:btc_phymap	file:
BTC_PHY_1	coex.c	/^	BTC_PHY_1 = BIT(1),$/;"	e	enum:btc_phymap	file:
BTC_PHY_ALL	coex.c	/^	BTC_PHY_ALL = BIT(0) | BIT(1),$/;"	e	enum:btc_phymap	file:
BTC_PLT_ALL	coex.c	/^	BTC_PLT_ALL = 0xf$/;"	e	enum:btc_plt	file:
BTC_PLT_BT	coex.c	/^	BTC_PLT_BT = BIT(1) | BIT(2),$/;"	e	enum:btc_plt	file:
BTC_PLT_GNT_BT_RX	coex.c	/^	BTC_PLT_GNT_BT_RX = BIT(2),$/;"	e	enum:btc_plt	file:
BTC_PLT_GNT_BT_TX	coex.c	/^	BTC_PLT_GNT_BT_TX = BIT(1),$/;"	e	enum:btc_plt	file:
BTC_PLT_GNT_WL	coex.c	/^	BTC_PLT_GNT_WL = BIT(3),$/;"	e	enum:btc_plt	file:
BTC_PLT_LTE_RX	coex.c	/^	BTC_PLT_LTE_RX = BIT(0),$/;"	e	enum:btc_plt	file:
BTC_PLT_NONE	coex.c	/^	BTC_PLT_NONE = 0,$/;"	e	enum:btc_plt	file:
BTC_POLICY_EXT_BIT	coex.c	/^	BTC_POLICY_EXT_BIT = BIT(15),$/;"	e	enum:btc_reason_and_action	file:
BTC_PRI_MASK_BEACON	coex.h	/^	BTC_PRI_MASK_BEACON,$/;"	e	enum:btc_pri
BTC_PRI_MASK_MAX	coex.h	/^	BTC_PRI_MASK_MAX,$/;"	e	enum:btc_pri
BTC_PRI_MASK_RX_CCK	coex.h	/^	BTC_PRI_MASK_RX_CCK,$/;"	e	enum:btc_pri
BTC_PRI_MASK_RX_RESP	coex.h	/^	BTC_PRI_MASK_RX_RESP = 0,$/;"	e	enum:btc_pri
BTC_PRI_MASK_TX_MNGQ	coex.h	/^	BTC_PRI_MASK_TX_MNGQ,$/;"	e	enum:btc_pri
BTC_PRI_MASK_TX_RESP	coex.h	/^	BTC_PRI_MASK_TX_RESP,$/;"	e	enum:btc_pri
BTC_PROFILE_MAX	core.h	/^	BTC_PROFILE_MAX = 4,$/;"	e	enum:rtw89_btc_bt_profile
BTC_RESET_ALL	coex.c	/^	BTC_RESET_ALL =  GENMASK(7, 0),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_BTINFO	coex.c	/^	BTC_RESET_BTINFO = BIT(3),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_CTRL	coex.c	/^	BTC_RESET_CTRL = BIT(2),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_CX	coex.c	/^	BTC_RESET_CX = BIT(0),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_CXDM	coex.c	/^	BTC_RESET_CXDM = BIT(0) | BIT(1),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_DM	coex.c	/^	BTC_RESET_DM = BIT(1),$/;"	e	enum:btc_reset_module	file:
BTC_RESET_MDINFO	coex.c	/^	BTC_RESET_MDINFO = BIT(4),$/;"	e	enum:btc_reset_module	file:
BTC_RFCTRL_FW_CTRL	coex.h	/^	BTC_RFCTRL_FW_CTRL,$/;"	e	enum:btc_rfctrl
BTC_RFCTRL_MAX	coex.h	/^	BTC_RFCTRL_MAX$/;"	e	enum:btc_rfctrl
BTC_RFCTRL_WL_OFF	coex.h	/^	BTC_RFCTRL_WL_OFF,$/;"	e	enum:btc_rfctrl
BTC_RFCTRL_WL_ON	coex.h	/^	BTC_RFCTRL_WL_ON,$/;"	e	enum:btc_rfctrl
BTC_RFK_BAND_MAP	coex.h	36;"	d
BTC_RFK_PATH_MAP	coex.h	34;"	d
BTC_RFK_PHY_MAP	coex.h	35;"	d
BTC_ROLE_CHG_TYPE	coex.h	/^	BTC_ROLE_CHG_TYPE,$/;"	e	enum:btc_role_state
BTC_ROLE_MSTS_AP_START	coex.h	/^	BTC_ROLE_MSTS_AP_START,$/;"	e	enum:btc_role_state
BTC_ROLE_MSTS_AP_STOP	coex.h	/^	BTC_ROLE_MSTS_AP_STOP,$/;"	e	enum:btc_role_state
BTC_ROLE_MSTS_STA_CONN_END	coex.h	/^	BTC_ROLE_MSTS_STA_CONN_END,$/;"	e	enum:btc_role_state
BTC_ROLE_MSTS_STA_CONN_START	coex.h	/^	BTC_ROLE_MSTS_STA_CONN_START,$/;"	e	enum:btc_role_state
BTC_ROLE_MSTS_STA_DIS_CONN	coex.h	/^	BTC_ROLE_MSTS_STA_DIS_CONN,$/;"	e	enum:btc_role_state
BTC_ROLE_START	coex.h	/^	BTC_ROLE_START,$/;"	e	enum:btc_role_state
BTC_ROLE_STATE_UNKNOWN	coex.h	/^	BTC_ROLE_STATE_UNKNOWN$/;"	e	enum:btc_role_state
BTC_ROLE_STOP	coex.h	/^	BTC_ROLE_STOP,$/;"	e	enum:btc_role_state
BTC_RPT_HDR_SIZE	coex.c	598;"	d	file:
BTC_RPT_TYPE_BT_AFH	core.h	/^	BTC_RPT_TYPE_BT_AFH,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_BT_DEVICE	core.h	/^	BTC_RPT_TYPE_BT_DEVICE,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_BT_SCAN	core.h	/^	BTC_RPT_TYPE_BT_SCAN,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_BT_VER	core.h	/^	BTC_RPT_TYPE_BT_VER,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_CTRL	core.h	/^	BTC_RPT_TYPE_CTRL = 0x0,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_CYSTA	core.h	/^	BTC_RPT_TYPE_CYSTA,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_GPIO_DBG	core.h	/^	BTC_RPT_TYPE_GPIO_DBG,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_MAX	core.h	/^	BTC_RPT_TYPE_MAX = 31$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_MREG	core.h	/^	BTC_RPT_TYPE_MREG,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_NULLSTA	core.h	/^	BTC_RPT_TYPE_NULLSTA,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_SLOT	core.h	/^	BTC_RPT_TYPE_SLOT,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_STEP	core.h	/^	BTC_RPT_TYPE_STEP,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_TDMA	core.h	/^	BTC_RPT_TYPE_TDMA,$/;"	e	enum:btf_fw_event_report
BTC_RPT_TYPE_TEST	core.h	/^	BTC_RPT_TYPE_TEST,$/;"	e	enum:btf_fw_event_report
BTC_RSN_ACT1_WORK	coex.c	/^	BTC_RSN_ACT1_WORK,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_BT_DEVINFO_WORK	coex.c	/^	BTC_RSN_BT_DEVINFO_WORK,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_CMD_SET_COEX	coex.c	/^	BTC_RSN_CMD_SET_COEX,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NONE	coex.c	/^	BTC_RSN_NONE,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_INIT	coex.c	/^	BTC_RSN_NTFY_INIT,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_POWEROFF	coex.c	/^	BTC_RSN_NTFY_POWEROFF,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_RADIO_STATE	coex.c	/^	BTC_RSN_NTFY_RADIO_STATE,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_ROLE_INFO	coex.c	/^	BTC_RSN_NTFY_ROLE_INFO,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_SCAN_FINISH	coex.c	/^	BTC_RSN_NTFY_SCAN_FINISH,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_SCAN_START	coex.c	/^	BTC_RSN_NTFY_SCAN_START,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_SPECIFIC_PACKET	coex.c	/^	BTC_RSN_NTFY_SPECIFIC_PACKET,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_SWBAND	coex.c	/^	BTC_RSN_NTFY_SWBAND,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_WL_RFK	coex.c	/^	BTC_RSN_NTFY_WL_RFK,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NTFY_WL_STA	coex.c	/^	BTC_RSN_NTFY_WL_STA,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_NUM	coex.c	/^	BTC_RSN_NUM,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_RFK_CHK_WORK	coex.c	/^	BTC_RSN_RFK_CHK_WORK,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_UPDATE_BT_INFO	coex.c	/^	BTC_RSN_UPDATE_BT_INFO,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSN_UPDATE_BT_SCBD	coex.c	/^	BTC_RSN_UPDATE_BT_SCBD,$/;"	e	enum:btc_reason_and_action	file:
BTC_RSSI_CHANGE	coex.h	79;"	d
BTC_RSSI_HIGH	coex.h	69;"	d
BTC_RSSI_LOW	coex.h	74;"	d
BTC_RSSI_ST_HIGH	coex.h	/^	BTC_RSSI_ST_HIGH,$/;"	e	enum:btc_rssi_st
BTC_RSSI_ST_LOW	coex.h	/^	BTC_RSSI_ST_LOW = 0x0,$/;"	e	enum:btc_rssi_st
BTC_RSSI_ST_MAX	coex.h	/^	BTC_RSSI_ST_MAX$/;"	e	enum:btc_rssi_st
BTC_RSSI_ST_STAY_HIGH	coex.h	/^	BTC_RSSI_ST_STAY_HIGH,$/;"	e	enum:btc_rssi_st
BTC_RSSI_ST_STAY_LOW	coex.h	/^	BTC_RSSI_ST_STAY_LOW,$/;"	e	enum:btc_rssi_st
BTC_SCAN_ADV	core.h	/^	BTC_SCAN_ADV,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_BLE	core.h	/^	BTC_SCAN_BLE,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_INIT	core.h	/^	BTC_SCAN_INIT,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_INQ	core.h	/^	BTC_SCAN_INQ	= 0,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_MAX1	core.h	/^	BTC_SCAN_MAX1,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_PAGE	core.h	/^	BTC_SCAN_PAGE,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCAN_TV	core.h	/^	BTC_SCAN_TV,$/;"	e	enum:rtw89_btc_bt_scan_type
BTC_SCB_INV_VALUE	coex.c	3389;"	d	file:
BTC_SWITCH_EXTERNAL	coex.h	/^	BTC_SWITCH_EXTERNAL$/;"	e	enum:btc_switch
BTC_SWITCH_INTERNAL	coex.h	/^	BTC_SWITCH_INTERNAL = 0,$/;"	e	enum:btc_switch
BTC_TDMA_BTHID_MAX	coex.c	532;"	d	file:
BTC_TDMA_WLROLE_MAX	coex.c	1445;"	d	file:
BTC_TLV_HDR_LEN	coex.c	1142;"	d	file:
BTC_WBUSY_BNOSCAN	coex.c	/^	BTC_WBUSY_BNOSCAN,$/;"	e	enum:btc_cx_state_map	file:
BTC_WBUSY_BSCAN	coex.c	/^	BTC_WBUSY_BSCAN,$/;"	e	enum:btc_cx_state_map	file:
BTC_WCNT_ARP	core.h	/^	BTC_WCNT_ARP,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_CH_UPDATE	core.h	/^	BTC_WCNT_CH_UPDATE,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_DHCP	core.h	/^	BTC_WCNT_DHCP,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_EAPOL	core.h	/^	BTC_WCNT_EAPOL,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_NUM	core.h	/^	BTC_WCNT_NUM$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_RFK_GO	core.h	/^	BTC_WCNT_RFK_GO,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_RFK_REJECT	core.h	/^	BTC_WCNT_RFK_REJECT,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_RFK_REQ	core.h	/^	BTC_WCNT_RFK_REQ,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_RFK_TIMEOUT	core.h	/^	BTC_WCNT_RFK_TIMEOUT,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_SCANAP	core.h	/^	BTC_WCNT_SCANAP = 0x0,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WCNT_SCBDUPDATE	core.h	/^	BTC_WCNT_SCBDUPDATE,$/;"	e	enum:rtw89_btc_wl_state_cnt
BTC_WIDLE	coex.c	/^	BTC_WIDLE = 0,$/;"	e	enum:btc_cx_state_map	file:
BTC_WLINKING	coex.c	/^	BTC_WLINKING$/;"	e	enum:btc_cx_state_map	file:
BTC_WLINK_25G_DBCC	coex.c	/^	BTC_WLINK_25G_DBCC,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_25G_MCC	coex.c	/^	BTC_WLINK_25G_MCC,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_AP	coex.c	/^	BTC_WLINK_2G_AP,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_GC	coex.c	/^	BTC_WLINK_2G_GC,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_GO	coex.c	/^	BTC_WLINK_2G_GO,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_MCC	coex.c	/^	BTC_WLINK_2G_MCC,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_NAN	coex.c	/^	BTC_WLINK_2G_NAN,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_SCC	coex.c	/^	BTC_WLINK_2G_SCC,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_2G_STA	coex.c	/^	BTC_WLINK_2G_STA,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_5G	coex.c	/^	BTC_WLINK_5G,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_MAX	coex.c	/^	BTC_WLINK_MAX$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_NOLINK	coex.c	/^	BTC_WLINK_NOLINK = 0x0,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WLINK_OTHER	coex.c	/^	BTC_WLINK_OTHER,$/;"	e	enum:btc_wl_link_mode	file:
BTC_WL_MODE_HE	coex.c	/^	BTC_WL_MODE_HE = 2,$/;"	e	enum:btc_wl_mode	file:
BTC_WL_MODE_HT	coex.c	/^	BTC_WL_MODE_HT = 0,$/;"	e	enum:btc_wl_mode	file:
BTC_WL_MODE_NUM	coex.c	/^	BTC_WL_MODE_NUM,$/;"	e	enum:btc_wl_mode	file:
BTC_WL_MODE_VHT	coex.c	/^	BTC_WL_MODE_VHT = 1,$/;"	e	enum:btc_wl_mode	file:
BTC_WL_RSSI_THMAX	core.h	889;"	d
BTC_WRFKT_DACK	coex.h	/^	BTC_WRFKT_DACK = 4,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_DPK	coex.h	/^	BTC_WRFKT_DPK = 2,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_IQK	coex.h	/^	BTC_WRFKT_IQK = 0,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_LCK	coex.h	/^	BTC_WRFKT_LCK = 1,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_RXDCK	coex.h	/^	BTC_WRFKT_RXDCK = 5,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_TSSI	coex.h	/^	BTC_WRFKT_TSSI = 6,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFKT_TXGAPK	coex.h	/^	BTC_WRFKT_TXGAPK = 3,$/;"	e	enum:btc_wl_rfk_type
BTC_WRFK_ALLOW	coex.c	/^	BTC_WRFK_ALLOW = 1,$/;"	e	enum:btc_wl_rfk_result	file:
BTC_WRFK_ONESHOT_START	coex.h	/^	BTC_WRFK_ONESHOT_START = 2,$/;"	e	enum:btc_wl_rfk_state
BTC_WRFK_ONESHOT_STOP	coex.h	/^	BTC_WRFK_ONESHOT_STOP = 3,$/;"	e	enum:btc_wl_rfk_state
BTC_WRFK_REJECT	coex.c	/^	BTC_WRFK_REJECT = 0,$/;"	e	enum:btc_wl_rfk_result	file:
BTC_WRFK_START	coex.h	/^	BTC_WRFK_START = 1,$/;"	e	enum:btc_wl_rfk_state
BTC_WRFK_STOP	coex.h	/^	BTC_WRFK_STOP = 0,$/;"	e	enum:btc_wl_rfk_state
BTC_WSCAN_BNOSCAN	coex.c	/^	BTC_WSCAN_BNOSCAN,$/;"	e	enum:btc_cx_state_map	file:
BTC_WSCAN_BSCAN	coex.c	/^	BTC_WSCAN_BSCAN,$/;"	e	enum:btc_cx_state_map	file:
BTC_WSCB_ACTIVE	coex.c	/^	BTC_WSCB_ACTIVE = BIT(0),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_ALL	coex.c	/^	BTC_WSCB_ALL = GENMASK(23, 0),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_BTLOG	coex.c	/^	BTC_WSCB_BTLOG = BIT(14),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_BTRFK_GNT	coex.c	/^	BTC_WSCB_BTRFK_GNT = BIT(12), \/* not used, use mailbox to inform BT *\/$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_BT_HILNA	coex.c	/^	BTC_WSCB_BT_HILNA = BIT(13),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_EXTFEM	coex.c	/^	BTC_WSCB_EXTFEM = BIT(8),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_FIX2M	coex.c	/^	BTC_WSCB_FIX2M = BIT(10),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_ON	coex.c	/^	BTC_WSCB_ON = BIT(1),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_RXGAIN	coex.c	/^	BTC_WSCB_RXGAIN = BIT(4),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_SCAN	coex.c	/^	BTC_WSCB_SCAN = BIT(2),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_TDMA	coex.c	/^	BTC_WSCB_TDMA = BIT(9),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_UNDERTEST	coex.c	/^	BTC_WSCB_UNDERTEST = BIT(3),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_WLBUSY	coex.c	/^	BTC_WSCB_WLBUSY = BIT(7),$/;"	e	enum:btc_w2b_scoreboard	file:
BTC_WSCB_WLRFK	coex.c	/^	BTC_WSCB_WLRFK = BIT(11),$/;"	e	enum:btc_w2b_scoreboard	file:
BTFC_FW_EVENT	fw.h	/^	BTFC_FW_EVENT = 0x12,$/;"	e	enum:rtw89_btc_btf_h2c_class
BTFC_GET	fw.h	/^	BTFC_GET = 0x11,$/;"	e	enum:rtw89_btc_btf_h2c_class
BTFC_SET	fw.h	/^	BTFC_SET = 0x10,$/;"	e	enum:rtw89_btc_btf_h2c_class
BTFRE_EXCEPTION	core.h	/^	BTFRE_EXCEPTION,$/;"	e	enum:rtw89_btc_btfre_type
BTFRE_INVALID_INPUT	core.h	/^	BTFRE_INVALID_INPUT = 0x0, \/* invalid input parameters *\/$/;"	e	enum:rtw89_btc_btfre_type
BTFRE_MAX	core.h	/^	BTFRE_MAX,$/;"	e	enum:rtw89_btc_btfre_type
BTFRE_UNDEF_TYPE	core.h	/^	BTFRE_UNDEF_TYPE,$/;"	e	enum:rtw89_btc_btfre_type
BTF_EVNT_BT_INFO	core.h	/^	BTF_EVNT_BT_INFO = 1,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_BT_PSD	core.h	/^	BTF_EVNT_BT_PSD = 5,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_BT_REG	core.h	/^	BTF_EVNT_BT_REG = 3,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_BT_SCBD	core.h	/^	BTF_EVNT_BT_SCBD = 2,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_BUF_OVERFLOW	core.h	/^	BTF_EVNT_BUF_OVERFLOW,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_C2H_LOOPBACK	core.h	/^	BTF_EVNT_C2H_LOOPBACK,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_CX_RUNINFO	core.h	/^	BTF_EVNT_CX_RUNINFO = 4,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_MAX	core.h	/^	BTF_EVNT_MAX,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_EVNT_RPT	core.h	/^	BTF_EVNT_RPT = 0,$/;"	e	enum:rtw89_btc_btf_fw_event
BTF_SET_MON_REG_VER	coex.c	155;"	d	file:
BTF_SET_REPORT_VER	coex.c	141;"	d	file:
BTF_SET_SLOT_TABLE_VER	coex.c	148;"	d	file:
B_2P4G_BAND_SEL	reg.h	1932;"	d
B_ADC_FIFO_RST	reg.h	1797;"	d
B_ANAPAR_14	reg.h	1671;"	d
B_ANAPAR_15	reg.h	1667;"	d
B_ANAPAR_ADCCLK	reg.h	1668;"	d
B_ANAPAR_CRXBB	reg.h	1670;"	d
B_ANAPAR_FLTRST	reg.h	1669;"	d
B_ANAPAR_PW15	reg.h	1663;"	d
B_ANAPAR_PW15_H	reg.h	1664;"	d
B_ANAPAR_PW15_H2	reg.h	1665;"	d
B_AXC_PHY_TXON_TIMEOUT	reg.h	1182;"	d
B_AX_ACKTO_CCK_MASK	reg.h	1118;"	d
B_AX_ACKTO_MASK	reg.h	1119;"	d
B_AX_ADDR_CAM_A2_B0_CHK	reg.h	1316;"	d
B_AX_ADDR_CAM_CLR	reg.h	1315;"	d
B_AX_ADDR_CAM_CMPLIMT_MASK	reg.h	1314;"	d
B_AX_ADDR_CAM_EN	reg.h	1318;"	d
B_AX_ADDR_CAM_RANGE_MASK	reg.h	1313;"	d
B_AX_ADDR_CAM_SRCH_PERPKT	reg.h	1317;"	d
B_AX_ADD_TXCNT_BY	reg.h	1000;"	d
B_AX_AMPDU_MAX_LEN_HT_MASK	reg.h	975;"	d
B_AX_AMPDU_MAX_TIME_MASK	reg.h	968;"	d
B_AX_APB_BRIDGE_ERR_FLAG	reg.h	286;"	d
B_AX_APPEND_FCS	reg.h	539;"	d
B_AX_APPEND_ICV	reg.h	571;"	d
B_AX_APPEND_MIC	reg.h	572;"	d
B_AX_APP_LTR_ACT	reg.h	246;"	d
B_AX_APP_LTR_IDLE	reg.h	247;"	d
B_AX_APP_MAC_INFO_RPT	reg.h	1331;"	d
B_AX_APP_PLCP_HDR_RPT	reg.h	1329;"	d
B_AX_APP_RX_CNT_RPT	reg.h	1330;"	d
B_AX_ASFF_FULL_NO_STK	reg.h	162;"	d
B_AX_AUTOLOAD_SUS	reg.h	9;"	d
B_AX_AVAL_PG_MASK	reg.h	344;"	d
B_AX_A_A1_MATCH	reg.h	1292;"	d
B_AX_A_BC	reg.h	1291;"	d
B_AX_A_BCN_CHK_EN	reg.h	1286;"	d
B_AX_A_BCN_CHK_RULE_MASK	reg.h	1285;"	d
B_AX_A_BC_CAM_MATCH	reg.h	1288;"	d
B_AX_A_CRC32_ERR	reg.h	1283;"	d
B_AX_A_ERR_PKT	reg.h	1281;"	d
B_AX_A_FTM_REQ	reg.h	1280;"	d
B_AX_A_ICV_ERR	reg.h	538;"	d
B_AX_A_MC	reg.h	1290;"	d
B_AX_A_MC_LIST_CAM_MATCH	reg.h	1287;"	d
B_AX_A_PWR_MGNT	reg.h	1284;"	d
B_AX_A_UC_CAM_MATCH	reg.h	1289;"	d
B_AX_A_UNSUP_PKT	reg.h	1282;"	d
B_AX_BAND_MODE	reg.h	993;"	d
B_AX_BCNERLY_MASK	reg.h	855;"	d
B_AX_BCNERR_CNT_EN	reg.h	825;"	d
B_AX_BCNTX_EN	reg.h	821;"	d
B_AX_BCN_AGRES	reg.h	826;"	d
B_AX_BCN_CNT_TMR_MASK	reg.h	931;"	d
B_AX_BCN_CTN_AREA_MASK	reg.h	848;"	d
B_AX_BCN_DROP_ALLOW	reg.h	819;"	d
B_AX_BCN_ERR_CNT_CCA_MASK	reg.h	896;"	d
B_AX_BCN_ERR_CNT_EDCCA_MASK	reg.h	895;"	d
B_AX_BCN_ERR_CNT_NAV_MASK	reg.h	894;"	d
B_AX_BCN_ERR_CNT_SUM_MASK	reg.h	893;"	d
B_AX_BCN_ERR_FLAG_CMP	reg.h	908;"	d
B_AX_BCN_ERR_FLAG_INVALID	reg.h	907;"	d
B_AX_BCN_ERR_FLAG_LOCK	reg.h	909;"	d
B_AX_BCN_ERR_FLAG_MAC	reg.h	904;"	d
B_AX_BCN_ERR_FLAG_OTHERS	reg.h	903;"	d
B_AX_BCN_ERR_FLAG_SRCHEND	reg.h	906;"	d
B_AX_BCN_ERR_FLAG_TXON	reg.h	905;"	d
B_AX_BCN_FORCETX_EN	reg.h	823;"	d
B_AX_BCN_MAX_ERR_MASK	reg.h	886;"	d
B_AX_BCN_MSK_AREA_MASK	reg.h	847;"	d
B_AX_BCN_SPACE_MASK	reg.h	877;"	d
B_AX_BC_DEC	reg.h	566;"	d
B_AX_BFMEE_BFPARAM_SEL	reg.h	1219;"	d
B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK	reg.h	1205;"	d
B_AX_BFMEE_BF_PORT_SEL	reg.h	1221;"	d
B_AX_BFMEE_CSIINFO0_BF_EN	reg.h	1229;"	d
B_AX_BFMEE_CSIINFO0_CB_MASK	reg.h	1233;"	d
B_AX_BFMEE_CSIINFO0_CS_MASK	reg.h	1232;"	d
B_AX_BFMEE_CSIINFO0_LDPC_EN	reg.h	1231;"	d
B_AX_BFMEE_CSIINFO0_NC_MASK	reg.h	1236;"	d
B_AX_BFMEE_CSIINFO0_NG_MASK	reg.h	1234;"	d
B_AX_BFMEE_CSIINFO0_NR_MASK	reg.h	1235;"	d
B_AX_BFMEE_CSIINFO0_STBC_EN	reg.h	1230;"	d
B_AX_BFMEE_CSISEQ_SEL	reg.h	1218;"	d
B_AX_BFMEE_CSI_FORCE_RETE_EN	reg.h	1226;"	d
B_AX_BFMEE_CSI_GID_SEL	reg.h	1224;"	d
B_AX_BFMEE_CSI_RATE_FB_EN	reg.h	1223;"	d
B_AX_BFMEE_CSI_RSC_MASK	reg.h	1225;"	d
B_AX_BFMEE_CSI_USE_NDPARATE	reg.h	1227;"	d
B_AX_BFMEE_CSI_WITHHTC_EN	reg.h	1228;"	d
B_AX_BFMEE_HE_CSI_RATE_MASK	reg.h	1244;"	d
B_AX_BFMEE_HE_NDPA_EN	reg.h	1210;"	d
B_AX_BFMEE_HT_CSI_RATE_MASK	reg.h	1246;"	d
B_AX_BFMEE_HT_NDPA_EN	reg.h	1212;"	d
B_AX_BFMEE_NDP_RXSTDBY_SEL	reg.h	1207;"	d
B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK	reg.h	1204;"	d
B_AX_BFMEE_OFDM_LEN_TH_MASK	reg.h	1220;"	d
B_AX_BFMEE_USE_NSTS	reg.h	1222;"	d
B_AX_BFMEE_VHT_CSI_RATE_MASK	reg.h	1245;"	d
B_AX_BFMEE_VHT_NDPA_EN	reg.h	1211;"	d
B_AX_BFMER_HE_CSI_OFFSET_MASK	reg.h	1196;"	d
B_AX_BFMER_HT_CSI_OFFSET_MASK	reg.h	1198;"	d
B_AX_BFMER_NDP_BFEN	reg.h	1199;"	d
B_AX_BFMER_VHT_BFPRT_CHK	reg.h	1200;"	d
B_AX_BFMER_VHT_CSI_OFFSET_MASK	reg.h	1197;"	d
B_AX_BMAC_CCA_TIMEOUT_FLAG	reg.h	1361;"	d
B_AX_BMAC_CCA_TO_IDLE_TIMEOUT_FLAG	reg.h	1364;"	d
B_AX_BMAC_CSI_TIMEOUT_FLAG	reg.h	1359;"	d
B_AX_BMAC_DATA_ON_TIMEOUT_FLAG	reg.h	1360;"	d
B_AX_BMAC_DATA_ON_TO_IDLE_TIMEOUT_FLAG	reg.h	1363;"	d
B_AX_BMAC_DMA_TIMEOUT_FLAG	reg.h	1362;"	d
B_AX_BMC_MGNT_DEC	reg.h	563;"	d
B_AX_BOOT_MODE	reg.h	45;"	d
B_AX_BOOT_REASON_MASK	reg.h	123;"	d
B_AX_BRK_SETUP	reg.h	817;"	d
B_AX_BSS_COLOB_AX_PORT_0_MASK	reg.h	1030;"	d
B_AX_BSS_COLOB_AX_PORT_1_MASK	reg.h	1029;"	d
B_AX_BSS_COLOB_AX_PORT_2_MASK	reg.h	1028;"	d
B_AX_BSS_COLOB_AX_PORT_3_MASK	reg.h	1027;"	d
B_AX_BSS_COLOB_AX_PORT_4_MASK	reg.h	1034;"	d
B_AX_BTCCA_BRK_TXOP_EN	reg.h	722;"	d
B_AX_BTCCA_EN	reg.h	723;"	d
B_AX_BTMODE_MASK	reg.h	56;"	d
B_AX_BT_AOD_GPIO3	reg.h	50;"	d
B_AX_BT_CNT_RST	reg.h	1442;"	d
B_AX_BT_HID_ISR_SET_MASK	reg.h	1465;"	d
B_AX_BT_PLT_PKT_CNT_MASK	reg.h	1013;"	d
B_AX_BT_PLT_RST	reg.h	1014;"	d
B_AX_BT_PRI_DETECT_TO_MASK	reg.h	1447;"	d
B_AX_BT_RPT_SAMPLE_RATE_MASK	reg.h	1476;"	d
B_AX_BT_STAT_DELAY_MASK	reg.h	1443;"	d
B_AX_BT_SW_CTRL_WL_PRIORITY	reg.h	1497;"	d
B_AX_BT_TIME_MASK	reg.h	1475;"	d
B_AX_BT_TRX_INIT_DETECT_MASK	reg.h	1445;"	d
B_AX_C2HREG_TRIGGER	reg.h	187;"	d
B_AX_C2H_INT	reg.h	174;"	d
B_AX_C2H_INT_EN	reg.h	172;"	d
B_AX_CALIB_EN	pci.h	23;"	d
B_AX_CCA_EN	reg.h	728;"	d
B_AX_CCK_CCA_TIMEOUT	reg.h	1181;"	d
B_AX_CCK_CCA_TIMEOUT_INT_EN	reg.h	1187;"	d
B_AX_CCK_CRC_CHK	reg.h	1271;"	d
B_AX_CCK_SIG_CHK	reg.h	1270;"	d
B_AX_CH10_BUSY	pci.h	276;"	d
B_AX_CH11_BUSY	pci.h	275;"	d
B_AX_CHECK_CCK_EN	reg.h	996;"	d
B_AX_CHECK_SOUNDING_SEQ	reg.h	1116;"	d
B_AX_CHIP_VER_MASK	reg.h	93;"	d
B_AX_CH_EN_MASK	reg.h	1255;"	d
B_AX_CLK_CALIB_EN	pci.h	22;"	d
B_AX_CLK_EN_CGCMP	reg.h	560;"	d
B_AX_CLK_EN_WAPI	reg.h	561;"	d
B_AX_CLK_EN_WEP_TKIP	reg.h	562;"	d
B_AX_CLR_ACH0_IDX	pci.h	255;"	d
B_AX_CLR_ACH1_IDX	pci.h	254;"	d
B_AX_CLR_ACH2_IDX	pci.h	253;"	d
B_AX_CLR_ACH3_IDX	pci.h	252;"	d
B_AX_CLR_ACH4_IDX	pci.h	251;"	d
B_AX_CLR_ACH5_IDX	pci.h	250;"	d
B_AX_CLR_ACH6_IDX	pci.h	249;"	d
B_AX_CLR_ACH7_IDX	pci.h	248;"	d
B_AX_CLR_CH10_IDX	pci.h	265;"	d
B_AX_CLR_CH11_IDX	pci.h	264;"	d
B_AX_CLR_CH12_IDX	pci.h	245;"	d
B_AX_CLR_CH8_IDX	pci.h	247;"	d
B_AX_CLR_CH9_IDX	pci.h	246;"	d
B_AX_CLR_RPQ_IDX	pci.h	259;"	d
B_AX_CLR_RXQ_IDX	pci.h	260;"	d
B_AX_CMAC1_FEN	reg.h	630;"	d
B_AX_CMAC_ALLCKEN	reg.h	653;"	d
B_AX_CMAC_CKEN	reg.h	654;"	d
B_AX_CMAC_CRPRT	reg.h	639;"	d
B_AX_CMAC_DMA_CKEN	reg.h	656;"	d
B_AX_CMAC_DMA_EN	reg.h	645;"	d
B_AX_CMAC_EN	reg.h	640;"	d
B_AX_CMAC_RXEN	reg.h	642;"	d
B_AX_CMAC_TXEN	reg.h	641;"	d
B_AX_CPL_STATUS_MASK	pci.h	300;"	d
B_AX_CPUQ_OP_CMD_TYPE_MASK	reg.h	504;"	d
B_AX_CPUQ_OP_DST_PID_MASK	reg.h	512;"	d
B_AX_CPUQ_OP_DST_QID_MASK	reg.h	513;"	d
B_AX_CPUQ_OP_MACID_MASK	reg.h	505;"	d
B_AX_CPUQ_OP_PKTNUM_MASK	reg.h	506;"	d
B_AX_CPUQ_OP_SRC_PID_MASK	reg.h	510;"	d
B_AX_CPUQ_OP_SRC_QID_MASK	reg.h	511;"	d
B_AX_CPU_CLK_EN	reg.h	19;"	d
B_AX_CPU_SHIFT_EN_ERR_INT_EN	reg.h	311;"	d
B_AX_CPWM_INT_EN	reg.h	170;"	d
B_AX_CSI_ON_TIMEOUT	reg.h	1177;"	d
B_AX_CSI_ON_TIMEOUT_INT_EN	reg.h	1183;"	d
B_AX_CS_REQ_SEL	reg.h	1079;"	d
B_AX_CS_REQ_VAL	reg.h	1078;"	d
B_AX_CTN_CHK_BASIC_NAV	reg.h	786;"	d
B_AX_CTN_CHK_BTCCA	reg.h	787;"	d
B_AX_CTN_CHK_CCA_P20	reg.h	792;"	d
B_AX_CTN_CHK_CCA_S20	reg.h	791;"	d
B_AX_CTN_CHK_CCA_S40	reg.h	790;"	d
B_AX_CTN_CHK_CCA_S80	reg.h	789;"	d
B_AX_CTN_CHK_EDCCA	reg.h	788;"	d
B_AX_CTN_CHK_INTRA_NAV	reg.h	785;"	d
B_AX_CTN_CHK_TXNAV	reg.h	784;"	d
B_AX_CTN_TXEN_BCNQ	reg.h	735;"	d
B_AX_CTN_TXEN_BE_0	reg.h	747;"	d
B_AX_CTN_TXEN_BE_1	reg.h	743;"	d
B_AX_CTN_TXEN_BK_0	reg.h	746;"	d
B_AX_CTN_TXEN_BK_1	reg.h	742;"	d
B_AX_CTN_TXEN_CPUMGQ	reg.h	737;"	d
B_AX_CTN_TXEN_HGQ	reg.h	736;"	d
B_AX_CTN_TXEN_MGQ	reg.h	739;"	d
B_AX_CTN_TXEN_MGQ1	reg.h	738;"	d
B_AX_CTN_TXEN_TWT_0	reg.h	733;"	d
B_AX_CTN_TXEN_TWT_1	reg.h	732;"	d
B_AX_CTN_TXEN_ULQ	reg.h	734;"	d
B_AX_CTN_TXEN_VI_0	reg.h	745;"	d
B_AX_CTN_TXEN_VI_1	reg.h	741;"	d
B_AX_CTN_TXEN_VO_0	reg.h	744;"	d
B_AX_CTN_TXEN_VO_1	reg.h	740;"	d
B_AX_DATA_ON_TIMEOUT	reg.h	1179;"	d
B_AX_DATA_ON_TIMEOUT_INT_EN	reg.h	1185;"	d
B_AX_DBGSEL_MACTX_MASK	reg.h	1094;"	d
B_AX_DBGSEL_TRXPTCL_MASK	reg.h	1173;"	d
B_AX_DBG_DUMMY_MASK	reg.h	158;"	d
B_AX_DBG_SEL0	reg.h	70;"	d
B_AX_DBG_SEL0_16BIT	reg.h	69;"	d
B_AX_DBG_SEL0_4BIT	reg.h	68;"	d
B_AX_DBG_SEL1	reg.h	67;"	d
B_AX_DBG_SEL1_16BIT	reg.h	66;"	d
B_AX_DBG_SEL1_4BIT	reg.h	65;"	d
B_AX_DBG_SEL_MASK	reg.h	159;"	d
B_AX_DBI_ADDR_MSK	pci.h	31;"	d
B_AX_DBI_RFLAG	pci.h	28;"	d
B_AX_DBI_WFLAG	pci.h	29;"	d
B_AX_DBI_WREN_MSK	pci.h	30;"	d
B_AX_DEBUG_SEL_MASK	reg.h	1374;"	d
B_AX_DEBUG_ST_MASK	reg.h	90;"	d
B_AX_DEFT_RATE_MASK	reg.h	992;"	d
B_AX_DEGLITCH	pci.h	18;"	d
B_AX_DESC_NUM_MSK	pci.h	166;"	d
B_AX_DFI_ACTIVE	reg.h	615;"	d
B_AX_DFI_ADDR_MASK	reg.h	617;"	d
B_AX_DFI_DATA_MASK	reg.h	619;"	d
B_AX_DFI_TRGSEL_MASK	reg.h	616;"	d
B_AX_DISPATCHER_CLK_EN	reg.h	220;"	d
B_AX_DISPATCHER_EN	reg.h	209;"	d
B_AX_DISPATCH_ERR_FLAG	reg.h	287;"	d
B_AX_DIS_BTC_CLK_G	reg.h	1417;"	d
B_AX_DIS_CHK_MIN_LEN	reg.h	1264;"	d
B_AX_DIS_RXDMA_PRE	pci.h	216;"	d
B_AX_DIV	pci.h	24;"	d
B_AX_DLE_CPUIO_CLK_EN	reg.h	219;"	d
B_AX_DLE_CPUIO_EN	reg.h	208;"	d
B_AX_DLE_CPUIO_ERR_FLAG	reg.h	285;"	d
B_AX_DLE_FREE_HEADPG	reg.h	405;"	d
B_AX_DLE_FREE_TAILPG	reg.h	406;"	d
B_AX_DLE_PLE_CLK_EN	reg.h	217;"	d
B_AX_DLE_PLE_EN	reg.h	204;"	d
B_AX_DLE_PUB_PGNUM	reg.h	404;"	d
B_AX_DLE_QEMPTY_GRP	reg.h	409;"	d
B_AX_DLE_RSV_PGNUM	reg.h	408;"	d
B_AX_DLE_USE_PGNUM	reg.h	407;"	d
B_AX_DLE_WDE_CLK_EN	reg.h	214;"	d
B_AX_DLE_WDE_EN	reg.h	201;"	d
B_AX_DMAC_FUNC_EN	reg.h	198;"	d
B_AX_DMAC_TBL_EN	reg.h	206;"	d
B_AX_DMA_TOP_ERR_IND	reg.h	691;"	d
B_AX_DRV_INFO_SIZE_MASK	reg.h	1254;"	d
B_AX_DTIM_CURRCNT_MASK	reg.h	917;"	d
B_AX_DTIM_NUM_MASK	reg.h	916;"	d
B_AX_EDCCA_EN	reg.h	724;"	d
B_AX_EF_ADDR_MASK	reg.h	41;"	d
B_AX_EF_CELL_SEL_MASK	reg.h	32;"	d
B_AX_EF_COMP_RESULT	reg.h	40;"	d
B_AX_EF_DATA_MASK	reg.h	42;"	d
B_AX_EF_MODE_SEL_MASK	reg.h	38;"	d
B_AX_EF_PD_DIS	reg.h	30;"	d
B_AX_EF_PGPD_MASK	reg.h	26;"	d
B_AX_EF_PGTS_MASK	reg.h	29;"	d
B_AX_EF_POR	reg.h	31;"	d
B_AX_EF_RDT	reg.h	27;"	d
B_AX_EF_RDY	reg.h	39;"	d
B_AX_EF_VDDQST_MASK	reg.h	28;"	d
B_AX_ENABLE_COEXIST_TAB_IN_TDMA	reg.h	1469;"	d
B_AX_ENABLE_PTA_TDMA_MODE	reg.h	1468;"	d
B_AX_ENABLE_TDMA_FW_MODE	reg.h	1467;"	d
B_AX_ENBT	reg.h	59;"	d
B_AX_ENHANCED_BT	reg.h	1452;"	d
B_AX_ENHTP	reg.h	49;"	d
B_AX_ENSIC	reg.h	51;"	d
B_AX_ENUARTRX	reg.h	61;"	d
B_AX_ENUARTTX	reg.h	55;"	d
B_AX_EN_32K	reg.h	126;"	d
B_AX_EN_CHKDSC_NO_RX_STUCK	pci.h	314;"	d
B_AX_EN_STUCK_DBG	reg.h	163;"	d
B_AX_EROM_EN	reg.h	60;"	d
B_AX_F2PCMD_USER_ALLC_ERR_INT_EN	reg.h	1038;"	d
B_AX_FEN_BBRSTB	reg.h	13;"	d
B_AX_FEN_BB_GLB_RSTN	reg.h	12;"	d
B_AX_FORCE_BCN_CURRCNT_MASK	reg.h	884;"	d
B_AX_FORCE_BCN_NUM_MASK	reg.h	885;"	d
B_AX_FORCE_CMACREG_GCKEN	reg.h	643;"	d
B_AX_FORCE_PWR_BY_RATE_EN	reg.h	1378;"	d
B_AX_FORCE_PWR_BY_RATE_VALUE_MASK	reg.h	1379;"	d
B_AX_FSM_TIMEOUT_ERR_INT_EN	reg.h	797;"	d
B_AX_FWDL_PATH_RDY	reg.h	106;"	d
B_AX_FWD_PPDU_STAT_MASK	reg.h	548;"	d
B_AX_G0_AVAL_PG_MASK	reg.h	362;"	d
B_AX_G0_USE_PG_MASK	reg.h	373;"	d
B_AX_G1_AVAL_PG_MASK	reg.h	361;"	d
B_AX_G1_USE_PG_MASK	reg.h	372;"	d
B_AX_GI_LTF_FB_SEL	reg.h	1006;"	d
B_AX_GNT_BT_BB_S0_SW_CTRL	reg.h	1506;"	d
B_AX_GNT_BT_BB_S0_SW_VAL	reg.h	1505;"	d
B_AX_GNT_BT_BB_S1_SW_CTRL	reg.h	1494;"	d
B_AX_GNT_BT_BB_S1_SW_VAL	reg.h	1493;"	d
B_AX_GNT_BT_BYPASS_PRIORITY	reg.h	1435;"	d
B_AX_GNT_BT_POLARITY	reg.h	1436;"	d
B_AX_GNT_BT_RFC_S0_SW_CTRL	reg.h	1502;"	d
B_AX_GNT_BT_RFC_S0_SW_VAL	reg.h	1501;"	d
B_AX_GNT_BT_RFC_S1_SW_CTRL	reg.h	1490;"	d
B_AX_GNT_BT_RFC_S1_SW_VAL	reg.h	1489;"	d
B_AX_GNT_BT_RX_SW_CTRL	reg.h	1523;"	d
B_AX_GNT_BT_RX_SW_VAL	reg.h	1522;"	d
B_AX_GNT_BT_TX_SW_CTRL	reg.h	1525;"	d
B_AX_GNT_BT_TX_SW_VAL	reg.h	1524;"	d
B_AX_GNT_WL_BB_S0_SW_CTRL	reg.h	1508;"	d
B_AX_GNT_WL_BB_S0_SW_VAL	reg.h	1507;"	d
B_AX_GNT_WL_BB_S1_SW_CTRL	reg.h	1496;"	d
B_AX_GNT_WL_BB_S1_SW_VAL	reg.h	1495;"	d
B_AX_GNT_WL_RFC_S0_SW_CTRL	reg.h	1504;"	d
B_AX_GNT_WL_RFC_S0_SW_VAL	reg.h	1503;"	d
B_AX_GNT_WL_RFC_S1_SW_CTRL	reg.h	1492;"	d
B_AX_GNT_WL_RFC_S1_SW_VAL	reg.h	1491;"	d
B_AX_GNT_WL_RX_SW_CTRL	reg.h	1519;"	d
B_AX_GNT_WL_RX_SW_VAL	reg.h	1518;"	d
B_AX_GNT_WL_TX_SW_CTRL	reg.h	1521;"	d
B_AX_GNT_WL_TX_SW_VAL	reg.h	1520;"	d
B_AX_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA	reg.h	1470;"	d
B_AX_GPIOSEL_MASK	reg.h	62;"	d
B_AX_GRP	reg.h	330;"	d
B_AX_GT3_INT_EN	reg.h	171;"	d
B_AX_H2CREG_TRIGGER	reg.h	185;"	d
B_AX_H2C_PATH_RDY	reg.h	107;"	d
B_AX_HALT_C2H_INT_EN	pci.h	42;"	d
B_AX_HALT_H2C_TRIGGER	reg.h	100;"	d
B_AX_HC00ISR_IND_INT	pci.h	80;"	d
B_AX_HC00ISR_IND_INT_EN	pci.h	52;"	d
B_AX_HC10ISR_IND_INT	pci.h	113;"	d
B_AX_HC10ISR_IND_INT_EN	pci.h	108;"	d
B_AX_HCI_FC_CH12_EN	reg.h	320;"	d
B_AX_HCI_FC_CH12_FULL_COND_MASK	reg.h	316;"	d
B_AX_HCI_FC_EN	reg.h	322;"	d
B_AX_HCI_FC_MODE_MASK	reg.h	321;"	d
B_AX_HCI_FC_WD_FULL_COND_MASK	reg.h	319;"	d
B_AX_HCI_FC_WP_CH07_FULL_COND_MASK	reg.h	318;"	d
B_AX_HCI_FC_WP_CH811_FULL_COND_MASK	reg.h	317;"	d
B_AX_HCI_RXDMA_EN	reg.h	191;"	d
B_AX_HCI_TXDMA_EN	reg.h	192;"	d
B_AX_HD0ISR_IND_INT	pci.h	82;"	d
B_AX_HD0ISR_IND_INT_EN	pci.h	54;"	d
B_AX_HD1ISR_IND_INT	pci.h	81;"	d
B_AX_HD1ISR_IND_INT_EN	pci.h	53;"	d
B_AX_HDT_OFFSET_UNMATCH_INT_EN	reg.h	307;"	d
B_AX_HDT_PKT_FAIL_DBG_INT_EN	reg.h	308;"	d
B_AX_HE_SIGB_CRC_CHK	reg.h	1265;"	d
B_AX_HOST_ADDR_INFO_8B_SEL	reg.h	304;"	d
B_AX_HS0ISR_IND_INT	pci.h	83;"	d
B_AX_HS0ISR_IND_INT_EN	pci.h	55;"	d
B_AX_HW_CTS2SELF_EN	reg.h	984;"	d
B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK	reg.h	982;"	d
B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK	reg.h	983;"	d
B_AX_L0_TO_L1_EVENT_MASK	reg.h	260;"	d
B_AX_L1OFF_PWR_OFF_EN	pci.h	284;"	d
B_AX_LATENCY_CONTROL	pci.h	210;"	d
B_AX_LBC_EN	pci.h	311;"	d
B_AX_LBC_FLAG	pci.h	310;"	d
B_AX_LBC_TIMER	pci.h	309;"	d
B_AX_LENGTH_ERR_FLAG_U0	reg.h	1093;"	d
B_AX_LENGTH_ERR_FLAG_U1	reg.h	1092;"	d
B_AX_LENGTH_ERR_FLAG_U2	reg.h	1091;"	d
B_AX_LENGTH_ERR_FLAG_U3	reg.h	1090;"	d
B_AX_LSIG_PARITY_CHK_EN	reg.h	1269;"	d
B_AX_LTECOEX_3WIRE_CTRL_MUX	reg.h	1510;"	d
B_AX_LTECOEX_FUN_EN	reg.h	1509;"	d
B_AX_LTECOEX_OP_MODE_SEL_MASK	reg.h	1511;"	d
B_AX_LTECOEX_UART_MODE_SEL_MASK	reg.h	1513;"	d
B_AX_LTECOEX_UART_MUX	reg.h	1512;"	d
B_AX_LTE_MUX_CTRL_PATH	reg.h	76;"	d
B_AX_LTE_PATTERN_1_EN	reg.h	1500;"	d
B_AX_LTE_PATTERN_2_EN	reg.h	1499;"	d
B_AX_LTR_EN	reg.h	248;"	d
B_AX_LTR_HW_EN	reg.h	249;"	d
B_AX_LTR_IDLE_TIMER_IDX_MASK	reg.h	245;"	d
B_AX_LTR_RX0_TH_MASK	reg.h	253;"	d
B_AX_LTR_RX1_TH_MASK	reg.h	252;"	d
B_AX_LTR_SPACE_IDX_MASK	reg.h	244;"	d
B_AX_L_TXCNT_LMT_MASK	reg.h	1002;"	d
B_AX_MACID127_96_SLEEP_MASK	reg.h	713;"	d
B_AX_MACID127_96_SLEEP_SH	reg.h	712;"	d
B_AX_MACID31_0_SLEEP_MASK	reg.h	698;"	d
B_AX_MACID31_0_SLEEP_SH	reg.h	697;"	d
B_AX_MACID63_32_SLEEP_MASK	reg.h	703;"	d
B_AX_MACID63_32_SLEEP_SH	reg.h	702;"	d
B_AX_MACID95_64_SLEEP_MASK	reg.h	708;"	d
B_AX_MACID95_64_SLEEP_SH	reg.h	707;"	d
B_AX_MACLBK_EN	reg.h	1145;"	d
B_AX_MACTX_DMA_CNT	reg.h	1089;"	d
B_AX_MACTX_MPDU_CNT	reg.h	1088;"	d
B_AX_MAC_FUNC_EN	reg.h	197;"	d
B_AX_MAC_SEC_CLK_EN	reg.h	221;"	d
B_AX_MAC_SEC_EN	reg.h	210;"	d
B_AX_MAX_AGG_NUM_MASK	reg.h	971;"	d
B_AX_MAX_PG_MASK	reg.h	328;"	d
B_AX_MAX_TAG_NUM	pci.h	315;"	d
B_AX_MAX_TXNSS_MASK	reg.h	994;"	d
B_AX_MBSSID_DROP_15_0_MASK	reg.h	1009;"	d
B_AX_MC_DEC	reg.h	565;"	d
B_AX_MDIO_ADDR_MASK	pci.h	49;"	d
B_AX_MDIO_PHY_ADDR_MASK	pci.h	46;"	d
B_AX_MDIO_RFLAG	pci.h	47;"	d
B_AX_MDIO_WFLAG	pci.h	48;"	d
B_AX_MIN_PG_MASK	reg.h	329;"	d
B_AX_MPDU_ERR_FLAG	reg.h	293;"	d
B_AX_MPDU_PROC_EN	reg.h	199;"	d
B_AX_MRD_TIMEOUT_EN	reg.h	161;"	d
B_AX_MUEDCA_BE_PARAM_0_AIFS_MASK	reg.h	753;"	d
B_AX_MUEDCA_BE_PARAM_0_CW_MASK	reg.h	752;"	d
B_AX_MUEDCA_BE_PARAM_0_TIMER_MASK	reg.h	751;"	d
B_AX_MUEDCA_EN_0	reg.h	766;"	d
B_AX_MUEDCA_WMM_SEL	reg.h	764;"	d
B_AX_MU_BFRPTSEG_SEL_MASK	reg.h	1206;"	d
B_AX_NET_TYPE_MASK	reg.h	822;"	d
B_AX_NO_RESERVE_PAGE_ERR_IMR	reg.h	1064;"	d
B_AX_OCP_L1_MASK	reg.h	35;"	d
B_AX_OFDM_CCA_TIMEOUT	reg.h	1180;"	d
B_AX_OFDM_CCA_TIMEOUT_INT_EN	reg.h	1186;"	d
B_AX_P0MB10_EN	reg.h	956;"	d
B_AX_P0MB11_EN	reg.h	955;"	d
B_AX_P0MB12_EN	reg.h	954;"	d
B_AX_P0MB13_EN	reg.h	953;"	d
B_AX_P0MB14_EN	reg.h	952;"	d
B_AX_P0MB15_EN	reg.h	951;"	d
B_AX_P0MB1_EN	reg.h	965;"	d
B_AX_P0MB2_EN	reg.h	964;"	d
B_AX_P0MB3_EN	reg.h	963;"	d
B_AX_P0MB4_EN	reg.h	962;"	d
B_AX_P0MB5_EN	reg.h	961;"	d
B_AX_P0MB6_EN	reg.h	960;"	d
B_AX_P0MB7_EN	reg.h	959;"	d
B_AX_P0MB8_EN	reg.h	958;"	d
B_AX_P0MB9_EN	reg.h	957;"	d
B_AX_P0MB_ALL_MASK	reg.h	949;"	d
B_AX_P0MB_NUM_MASK	reg.h	950;"	d
B_AX_PCIEDBG_TXERR0	pci.h	303;"	d
B_AX_PCIEIO_BUSY	pci.h	271;"	d
B_AX_PCIEIO_RX_BUSY	pci.h	269;"	d
B_AX_PCIEIO_TX_BUSY	pci.h	270;"	d
B_AX_PCIE_AUXCLK_GATE	reg.h	75;"	d
B_AX_PCIE_DBG_SEL	reg.h	160;"	d
B_AX_PCIE_DIS_L2_CTRL_LDO_HCI	reg.h	73;"	d
B_AX_PCIE_DIS_WLSUS_AFT_PDN	reg.h	74;"	d
B_AX_PCIE_FLR_INT	pci.h	90;"	d
B_AX_PCIE_FLR_INT_EN	pci.h	62;"	d
B_AX_PCIE_FLR_KEEP_REG	pci.h	205;"	d
B_AX_PCIE_HCISYS_PWR_STE_MASK	reg.h	153;"	d
B_AX_PCIE_HOTRST_INT	pci.h	89;"	d
B_AX_PCIE_HOTRST_INT_EN	pci.h	61;"	d
B_AX_PCIE_MAX_RXDMA_MASK	pci.h	208;"	d
B_AX_PCIE_MAX_TXDMA_MASK	pci.h	212;"	d
B_AX_PCIE_PERST_INT	pci.h	91;"	d
B_AX_PCIE_PERST_INT_EN	pci.h	63;"	d
B_AX_PCIE_PERST_KEEP_REG	pci.h	204;"	d
B_AX_PCIE_RPQ_FULL	pci.h	298;"	d
B_AX_PCIE_RXP1_ERR0	pci.h	304;"	d
B_AX_PCIE_RXQ_FULL	pci.h	299;"	d
B_AX_PCIE_RXRST_KEEP_REG	pci.h	202;"	d
B_AX_PCIE_TRAIN_KEEP_REG	pci.h	206;"	d
B_AX_PCIE_TXBD_4KBOUD_LENERR	pci.h	306;"	d
B_AX_PCIE_TXBD_LEN0	pci.h	305;"	d
B_AX_PCIE_TXRST_KEEP_REG	pci.h	203;"	d
B_AX_PCLP_MON_CONT_MASK	reg.h	1370;"	d
B_AX_PCLP_MON_SEL_MASK	reg.h	1369;"	d
B_AX_PHYINTF_CKEN	reg.h	655;"	d
B_AX_PHYINTF_EN	reg.h	644;"	d
B_AX_PHYINTF_ERR_IND	reg.h	690;"	d
B_AX_PHYINTF_TIMEOUT_THR_MSAK	reg.h	1189;"	d
B_AX_PHY_TXON_TIMEOUT_INT_EN	reg.h	1188;"	d
B_AX_PKTIN_ERR_FLAG	reg.h	288;"	d
B_AX_PKT_BUF_EN	reg.h	205;"	d
B_AX_PKT_IN_CLK_EN	reg.h	218;"	d
B_AX_PKT_IN_EN	reg.h	207;"	d
B_AX_PLE_BUF_MGN_INI_RDY	reg.h	450;"	d
B_AX_PLE_DFI_ACTIVE	reg.h	453;"	d
B_AX_PLE_DFI_ADDR_MASK	reg.h	455;"	d
B_AX_PLE_DFI_DATA_MASK	reg.h	457;"	d
B_AX_PLE_DFI_TRGSEL_MASK	reg.h	454;"	d
B_AX_PLE_DLE_ERR_FLAG	reg.h	289;"	d
B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL	reg.h	268;"	d
B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL	reg.h	267;"	d
B_AX_PLE_EMPTY_QTA_DMAC_CPUIO	reg.h	263;"	d
B_AX_PLE_EMPTY_QTA_DMAC_H2C	reg.h	266;"	d
B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX	reg.h	264;"	d
B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU	reg.h	265;"	d
B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX	reg.h	276;"	d
B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX	reg.h	275;"	d
B_AX_PLE_FREE_PAGE_NUM_MASK	reg.h	425;"	d
B_AX_PLE_GETNPG_STRPG_ERR_INT_EN	reg.h	429;"	d
B_AX_PLE_MAX_SIZE_MASK	reg.h	432;"	d
B_AX_PLE_MIN_SIZE_MASK	reg.h	433;"	d
B_AX_PLE_PAGE_SEL_MASK	reg.h	424;"	d
B_AX_PLE_Q6_MAX_SIZE_MASK	reg.h	441;"	d
B_AX_PLE_Q6_MIN_SIZE_MASK	reg.h	442;"	d
B_AX_PLE_Q_MGN_INI_RDY	reg.h	449;"	d
B_AX_PLE_START_BOUND_MASK	reg.h	423;"	d
B_AX_PLT_EN	reg.h	1015;"	d
B_AX_PL_PAGE_128B_SEL	reg.h	298;"	d
B_AX_PORT_DROP_4_0_MASK	reg.h	1008;"	d
B_AX_PORT_FUNC_EN	reg.h	830;"	d
B_AX_PO_BT_PTA_PINS	reg.h	54;"	d
B_AX_PO_WIFI_PTA_PINS	reg.h	53;"	d
B_AX_PPDU_STAT_RPT_A1M	reg.h	1328;"	d
B_AX_PPDU_STAT_RPT_CRC32	reg.h	1327;"	d
B_AX_PPDU_STAT_RPT_EN	reg.h	1332;"	d
B_AX_PPDU_STAT_RPT_TRIG	reg.h	1326;"	d
B_AX_PREBKF_TIME_MASK	reg.h	718;"	d
B_AX_PREC_PAGE_CH011_MASK	reg.h	326;"	d
B_AX_PREC_PAGE_CH12_MASK	reg.h	325;"	d
B_AX_PREC_PAGE_WP_CH07_MASK	reg.h	380;"	d
B_AX_PREC_PAGE_WP_CH811_MASK	reg.h	379;"	d
B_AX_PSUS_OFF_CAPC_EN	reg.h	16;"	d
B_AX_PTA_EDCCA_EN	reg.h	1425;"	d
B_AX_PTA_WL_PRI_MASK_BCNQ	reg.h	1420;"	d
B_AX_PTA_WL_TX_EN	reg.h	1424;"	d
B_AX_PTCLTOP_CKEN	reg.h	657;"	d
B_AX_PTCLTOP_EN	reg.h	646;"	d
B_AX_PTCL_DBG_EN	reg.h	1059;"	d
B_AX_PTCL_DBG_INFO_MASK	reg.h	1056;"	d
B_AX_PTCL_DBG_SEL_MASK	reg.h	1060;"	d
B_AX_PTCL_TOP_ERR_IND	reg.h	692;"	d
B_AX_PTCL_TX_ARB_TO_MODE	reg.h	1047;"	d
B_AX_PTCL_TX_ARB_TO_THR_MASK	reg.h	1048;"	d
B_AX_PTCL_TX_ON_STAT	reg.h	1052;"	d
B_AX_PUBPG_ALL_MASK	reg.h	369;"	d
B_AX_PUBPG_G0_MASK	reg.h	366;"	d
B_AX_PUBPG_G1_MASK	reg.h	365;"	d
B_AX_PUB_AVAL_PG_MASK	reg.h	376;"	d
B_AX_PWR_UL_CFO_MASK	reg.h	1388;"	d
B_AX_PWR_UL_CTRL2_MASK	reg.h	1389;"	d
B_AX_PWR_UL_TB_1T_MASK	reg.h	1393;"	d
B_AX_PWR_UL_TB_2T_MASK	reg.h	1395;"	d
B_AX_PWR_UL_TB_CTRL_EN	reg.h	1391;"	d
B_AX_RATE_SEL_MASK	reg.h	1007;"	d
B_AX_RA_TRY_RATE_AGG_LMT_MASK	reg.h	969;"	d
B_AX_RDU_INT	pci.h	86;"	d
B_AX_RDU_INT_EN	pci.h	58;"	d
B_AX_RETRAIN_INT	pci.h	84;"	d
B_AX_RETRAIN_INT_EN	pci.h	56;"	d
B_AX_RLSRPT0_AGGNUM_MASK	reg.h	471;"	d
B_AX_RLSRPT0_FLTR_MAP_MASK	reg.h	464;"	d
B_AX_RLSRPT0_PID_MASK	reg.h	466;"	d
B_AX_RLSRPT0_PKTTYPE_MASK	reg.h	465;"	d
B_AX_RLSRPT0_QID_MASK	reg.h	467;"	d
B_AX_RLSRPT0_TO_MASK	reg.h	470;"	d
B_AX_RLSRPT_BUFREQ_TO_MASK	reg.h	460;"	d
B_AX_RMAC_CCA_TIMEOUT_INT_EN	reg.h	1353;"	d
B_AX_RMAC_CCA_TO_IDLE_TIMEOUT_INT_EN	reg.h	1356;"	d
B_AX_RMAC_CKEN	reg.h	660;"	d
B_AX_RMAC_CSI_TIMEOUT_INT_EN	reg.h	1351;"	d
B_AX_RMAC_DATA_ON_TIMEOUT_INT_EN	reg.h	1352;"	d
B_AX_RMAC_DATA_ON_TO_IDLE_TIMEOUT_INT_EN	reg.h	1355;"	d
B_AX_RMAC_DMA_TIMEOUT_INT_EN	reg.h	1354;"	d
B_AX_RMAC_EN	reg.h	649;"	d
B_AX_RMAC_PLCP_MON_MASK	reg.h	1368;"	d
B_AX_RMAC_RX_CSI_TIMEOUT_FLAG	reg.h	1357;"	d
B_AX_RMAC_RX_CSI_TIMEOUT_INT_EN	reg.h	1349;"	d
B_AX_RMAC_RX_TIMEOUT_FLAG	reg.h	1358;"	d
B_AX_RMAC_RX_TIMEOUT_INT_EN	reg.h	1350;"	d
B_AX_RPQBD_FULL_INT	pci.h	85;"	d
B_AX_RPQBD_FULL_INT_EN	pci.h	57;"	d
B_AX_RPQDMA_INT	pci.h	103;"	d
B_AX_RPQDMA_INT_EN	pci.h	75;"	d
B_AX_RSP_CHK_BASIC_NAV	reg.h	1112;"	d
B_AX_RSP_CHK_BTCCA	reg.h	1129;"	d
B_AX_RSP_CHK_CCA	reg.h	1131;"	d
B_AX_RSP_CHK_EDCCA	reg.h	1130;"	d
B_AX_RSP_CHK_INTRA_NAV	reg.h	1113;"	d
B_AX_RSP_CHK_SEC_CCA_20	reg.h	1128;"	d
B_AX_RSP_CHK_SEC_CCA_40	reg.h	1127;"	d
B_AX_RSP_CHK_SEC_CCA_80	reg.h	1126;"	d
B_AX_RSP_CHK_TXNAV	reg.h	1114;"	d
B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN	reg.h	1110;"	d
B_AX_RSP_TBPPDU_CHK_PWR	reg.h	1111;"	d
B_AX_RST_BDRAM	pci.h	215;"	d
B_AX_RTK_BT_ENABLE	reg.h	1471;"	d
B_AX_RTS_LEN_TH_MASK	reg.h	977;"	d
B_AX_RTS_LIMIT_IN_OFDM6	reg.h	995;"	d
B_AX_RTS_MAX_AGG_NUM_MASK	reg.h	970;"	d
B_AX_RTS_TXTIME_TH_MASK	reg.h	976;"	d
B_AX_RXBA_IGNOREA2	reg.h	1117;"	d
B_AX_RXBCN_RPT_EN	reg.h	832;"	d
B_AX_RXBD_CLR_ALL	pci.h	261;"	d
B_AX_RXBD_MODE	pci.h	207;"	d
B_AX_RXCOUNTER_MATCH_MASK	pci.h	294;"	d
B_AX_RXDATA_FSM_HANG_ERROR_IMR	reg.h	1065;"	d
B_AX_RXDMA_INT	pci.h	105;"	d
B_AX_RXDMA_INT_EN	pci.h	77;"	d
B_AX_RXDMA_PREF_ADV_EN	pci.h	319;"	d
B_AX_RXDMA_STUCK_INT	pci.h	87;"	d
B_AX_RXDMA_STUCK_INT_EN	pci.h	59;"	d
B_AX_RXEN	pci.h	20;"	d
B_AX_RXERR_INTPS_EN	reg.h	1348;"	d
B_AX_RXHCI_EN	pci.h	209;"	d
B_AX_RXMIT_RXP1_SEL	pci.h	288;"	d
B_AX_RXMIT_RXP2_SEL	pci.h	287;"	d
B_AX_RXP1DMA_INT	pci.h	104;"	d
B_AX_RXP1DMA_INT_EN	pci.h	76;"	d
B_AX_RXTIMER_MATCH_MASK	pci.h	295;"	d
B_AX_RXTIMER_UNIT_MASK	pci.h	289;"	d
B_AX_RXTRIG_EN	reg.h	1153;"	d
B_AX_RXTRIG_FCSCHK_EN	reg.h	1151;"	d
B_AX_RXTRIG_MACID_MASK	reg.h	1149;"	d
B_AX_RXTRIG_PORT_SEL_MASK	reg.h	1152;"	d
B_AX_RXTRIG_RU26_DIS	reg.h	1150;"	d
B_AX_RXTRIG_USERINFO_2_MASK	reg.h	1154;"	d
B_AX_RX_BSSID_FIT_EN	reg.h	828;"	d
B_AX_RX_DLK_CCA_TIME_MASK	reg.h	1259;"	d
B_AX_RX_DLK_DATA_TIME_MASK	reg.h	1260;"	d
B_AX_RX_FLTR_CFG_MASK	reg.h	1299;"	d
B_AX_RX_MPDU_MAX_LEN_MASK	reg.h	1278;"	d
B_AX_RX_MPDU_MAX_LEN_SIZE	reg.h	1279;"	d
B_AX_RX_PLT_GNT_BT_RX	reg.h	1017;"	d
B_AX_RX_PLT_GNT_BT_TX	reg.h	1018;"	d
B_AX_RX_PLT_GNT_LTE_RX	reg.h	1016;"	d
B_AX_RX_PLT_GNT_WL	reg.h	1019;"	d
B_AX_RX_STATE_MONITOR_MASK	reg.h	1340;"	d
B_AX_RX_STUCK	pci.h	301;"	d
B_AX_RX_TRUNC_MODE	pci.h	214;"	d
B_AX_R_BT_CMD_RPT_MASK	reg.h	1463;"	d
B_AX_R_DIS_PRST	reg.h	22;"	d
B_AX_R_RPT_FROM_BT_MASK	reg.h	1464;"	d
B_AX_R_SYM_FEN_WLBBFUN_1	reg.h	632;"	d
B_AX_R_SYM_FEN_WLBBGLB_1	reg.h	631;"	d
B_AX_R_SYM_ISO_CMAC12PP	reg.h	633;"	d
B_AX_R_SYM_WLCMAC1_P1_PC_EN	reg.h	626;"	d
B_AX_R_SYM_WLCMAC1_P2_PC_EN	reg.h	625;"	d
B_AX_R_SYM_WLCMAC1_P3_PC_EN	reg.h	624;"	d
B_AX_R_SYM_WLCMAC1_P4_PC_EN	reg.h	623;"	d
B_AX_R_SYM_WLCMAC1_PC_EN	reg.h	627;"	d
B_AX_SCHEDULER_CKEN	reg.h	658;"	d
B_AX_SCHEDULER_DBG_MASK	reg.h	810;"	d
B_AX_SCHEDULER_EN	reg.h	647;"	d
B_AX_SCHEDULE_TOP_ERR_IND	reg.h	693;"	d
B_AX_SCH_CFG_CMD_SEL	reg.h	805;"	d
B_AX_SCH_DBG_EN	reg.h	804;"	d
B_AX_SCH_DBG_SEL_MASK	reg.h	806;"	d
B_AX_SDIO_HCISYS_PWR_STE_MASK	reg.h	151;"	d
B_AX_SEC20_EN	reg.h	727;"	d
B_AX_SEC40_EN	reg.h	726;"	d
B_AX_SEC80_EN	reg.h	725;"	d
B_AX_SECSIC_SEL	reg.h	48;"	d
B_AX_SEC_RX_DEC	reg.h	567;"	d
B_AX_SEC_TX_ENC	reg.h	568;"	d
B_AX_SEL_0XC0_MASK	reg.h	96;"	d
B_AX_SET_MUEDCATIMER_TF_0	reg.h	765;"	d
B_AX_SIC_EN_FORCE_CLKREQ	pci.h	316;"	d
B_AX_SIC_SWRST	reg.h	52;"	d
B_AX_SIFS_CHK_BTCCA	reg.h	778;"	d
B_AX_SIFS_CHK_CCA_P20	reg.h	783;"	d
B_AX_SIFS_CHK_CCA_S20	reg.h	782;"	d
B_AX_SIFS_CHK_CCA_S40	reg.h	781;"	d
B_AX_SIFS_CHK_CCA_S80	reg.h	780;"	d
B_AX_SIFS_CHK_EDCCA	reg.h	779;"	d
B_AX_SIGA_CRC_CHK	reg.h	1268;"	d
B_AX_SNIFFER_MODE	reg.h	1293;"	d
B_AX_SORT_NON_IDLE_ERR_INT_EN	reg.h	796;"	d
B_AX_SPEC_SIFS_CCK_PTCL_MASK	reg.h	987;"	d
B_AX_SPEC_SIFS_OFDM_PTCL_MASK	reg.h	986;"	d
B_AX_SPEC_SIFS_OFDM_PTCL_SH	reg.h	985;"	d
B_AX_SR_EN	reg.h	1336;"	d
B_AX_SSN_SEL	reg.h	1322;"	d
B_AX_SS_EN	reg.h	586;"	d
B_AX_SS_INIT_DONE_1	reg.h	584;"	d
B_AX_SS_MACID127_96_PAUSE_MASK	reg.h	602;"	d
B_AX_SS_MACID127_96_PAUSE_SH	reg.h	601;"	d
B_AX_SS_MACID31_0_PAUSE_MASK	reg.h	590;"	d
B_AX_SS_MACID31_0_PAUSE_SH	reg.h	589;"	d
B_AX_SS_MACID63_32_PAUSE_MASK	reg.h	594;"	d
B_AX_SS_MACID63_32_PAUSE_SH	reg.h	593;"	d
B_AX_SS_MACID95_64_PAUSE_MASK	reg.h	598;"	d
B_AX_SS_MACID95_64_PAUSE_SH	reg.h	597;"	d
B_AX_SS_WARM_INIT_FLG	reg.h	585;"	d
B_AX_STATE_CUR_MASK	reg.h	1341;"	d
B_AX_STATE_NXT_MASK	reg.h	1342;"	d
B_AX_STATE_SEL_MASK	reg.h	1344;"	d
B_AX_STATE_UPD	reg.h	1343;"	d
B_AX_STATIS_BT_EN	reg.h	1450;"	d
B_AX_STATIS_BT_HI_RX_MASK	reg.h	1455;"	d
B_AX_STATIS_BT_HI_TX_MASK	reg.h	1456;"	d
B_AX_STATIS_BT_LO_RX_1_MASK	reg.h	1459;"	d
B_AX_STATIS_BT_LO_TX_1_MASK	reg.h	1458;"	d
B_AX_STA_SCHEDULER_ERR_FLAG	reg.h	292;"	d
B_AX_STA_SCH_CLK_EN	reg.h	216;"	d
B_AX_STA_SCH_EN	reg.h	203;"	d
B_AX_STOP_ACH0	pci.h	234;"	d
B_AX_STOP_ACH1	pci.h	233;"	d
B_AX_STOP_ACH2	pci.h	232;"	d
B_AX_STOP_ACH3	pci.h	231;"	d
B_AX_STOP_ACH4	pci.h	230;"	d
B_AX_STOP_ACH5	pci.h	229;"	d
B_AX_STOP_ACH6	pci.h	228;"	d
B_AX_STOP_ACH7	pci.h	227;"	d
B_AX_STOP_CH10	pci.h	241;"	d
B_AX_STOP_CH11	pci.h	240;"	d
B_AX_STOP_CH12	pci.h	224;"	d
B_AX_STOP_CH8	pci.h	226;"	d
B_AX_STOP_CH9	pci.h	225;"	d
B_AX_STOP_PCIEIO	pci.h	222;"	d
B_AX_STOP_RPQ	pci.h	235;"	d
B_AX_STOP_RXQ	pci.h	236;"	d
B_AX_STOP_RX_IN	reg.h	1253;"	d
B_AX_STOP_WPDMA	pci.h	223;"	d
B_AX_STS_ON_TIMEOUT	reg.h	1178;"	d
B_AX_STS_ON_TIMEOUT_INT_EN	reg.h	1184;"	d
B_AX_SUB_BCN_SPACE_MASK	reg.h	876;"	d
B_AX_S_TXCNT_LMT_MASK	reg.h	1001;"	d
B_AX_TBTTERLY_MASK	reg.h	862;"	d
B_AX_TBTT_AGG_NUM_MASK	reg.h	869;"	d
B_AX_TBTT_HOLD_MASK	reg.h	839;"	d
B_AX_TBTT_PROHIB_EN	reg.h	820;"	d
B_AX_TBTT_SETUP_MASK	reg.h	840;"	d
B_AX_TBTT_SHIFT_OFST_MASK	reg.h	924;"	d
B_AX_TBTT_UPD_SHIFT_SEL	reg.h	818;"	d
B_AX_TB_CHK_BASIC_NAV	reg.h	771;"	d
B_AX_TB_CHK_BTCCA	reg.h	772;"	d
B_AX_TB_CHK_CCA_P20	reg.h	777;"	d
B_AX_TB_CHK_CCA_S20	reg.h	776;"	d
B_AX_TB_CHK_CCA_S40	reg.h	775;"	d
B_AX_TB_CHK_CCA_S80	reg.h	774;"	d
B_AX_TB_CHK_EDCCA	reg.h	773;"	d
B_AX_TB_CHK_TX_NAV	reg.h	770;"	d
B_AX_TCR_CCK_LOCK_CLK	reg.h	1073;"	d
B_AX_TCR_FORCE_READ_TXDFIFO	reg.h	1074;"	d
B_AX_TCR_SMOOTH_CTRL	reg.h	1077;"	d
B_AX_TCR_SMOOTH_VAL	reg.h	1076;"	d
B_AX_TCR_TXTIMEOUT	reg.h	1081;"	d
B_AX_TCR_USTIME	reg.h	1075;"	d
B_AX_TCR_ZLD_USTIME_AFTERPHYTXON	reg.h	1080;"	d
B_AX_TDMA_BT_START_NOTIFY	reg.h	1466;"	d
B_AX_TIMER_MASK	reg.h	1437;"	d
B_AX_TMAC_CKEN	reg.h	659;"	d
B_AX_TMAC_EN	reg.h	648;"	d
B_AX_TOGGLE	reg.h	82;"	d
B_AX_TSFTR_HIGH_MASK	reg.h	945;"	d
B_AX_TSFTR_LOW_MASK	reg.h	938;"	d
B_AX_TSFTR_RST	reg.h	827;"	d
B_AX_TSF_UDT_EN	reg.h	829;"	d
B_AX_TXAGC_BT_EN	reg.h	1383;"	d
B_AX_TXAGC_BT_MASK	reg.h	1384;"	d
B_AX_TXBCN_BTCCA_EN	reg.h	824;"	d
B_AX_TXBCN_RPT_EN	reg.h	831;"	d
B_AX_TXBD_CLR1_ALL	pci.h	256;"	d
B_AX_TXBD_CLR2_ALL	pci.h	266;"	d
B_AX_TXDATA_END_PS_OPT	reg.h	1115;"	d
B_AX_TXDFIFO_THRESHOLD	reg.h	1072;"	d
B_AX_TXDMA_ACH0_INT	pci.h	102;"	d
B_AX_TXDMA_ACH0_INT_EN	pci.h	74;"	d
B_AX_TXDMA_ACH1_INT	pci.h	101;"	d
B_AX_TXDMA_ACH1_INT_EN	pci.h	73;"	d
B_AX_TXDMA_ACH2_INT	pci.h	100;"	d
B_AX_TXDMA_ACH2_INT_EN	pci.h	72;"	d
B_AX_TXDMA_ACH3_INT	pci.h	99;"	d
B_AX_TXDMA_ACH3_INT_EN	pci.h	71;"	d
B_AX_TXDMA_ACH4_INT	pci.h	98;"	d
B_AX_TXDMA_ACH4_INT_EN	pci.h	70;"	d
B_AX_TXDMA_ACH5_INT	pci.h	97;"	d
B_AX_TXDMA_ACH5_INT_EN	pci.h	69;"	d
B_AX_TXDMA_ACH6_INT	pci.h	96;"	d
B_AX_TXDMA_ACH6_INT_EN	pci.h	68;"	d
B_AX_TXDMA_ACH7_INT	pci.h	95;"	d
B_AX_TXDMA_ACH7_INT_EN	pci.h	67;"	d
B_AX_TXDMA_CH10_INT	pci.h	115;"	d
B_AX_TXDMA_CH10_INT_EN	pci.h	110;"	d
B_AX_TXDMA_CH11_INT	pci.h	114;"	d
B_AX_TXDMA_CH11_INT_EN	pci.h	109;"	d
B_AX_TXDMA_CH12_INT	pci.h	92;"	d
B_AX_TXDMA_CH12_INT_EN	pci.h	64;"	d
B_AX_TXDMA_CH8_INT	pci.h	94;"	d
B_AX_TXDMA_CH8_INT_EN	pci.h	66;"	d
B_AX_TXDMA_CH9_INT	pci.h	93;"	d
B_AX_TXDMA_CH9_INT_EN	pci.h	65;"	d
B_AX_TXDMA_STUCK_INT	pci.h	88;"	d
B_AX_TXDMA_STUCK_INT_EN	pci.h	60;"	d
B_AX_TXHCI_EN	pci.h	211;"	d
B_AX_TXPKTCTL_CMDPSR_FRZTO_ERR_INT_EN	reg.h	609;"	d
B_AX_TXPKTCTL_USRCTL_NOINIT_ERR_INT_EN	reg.h	612;"	d
B_AX_TXPKTCTL_USRCTL_RDNRLSCMD_ERR_INT_EN	reg.h	611;"	d
B_AX_TXPKTCTL_USRCTL_RLSBMPLEN_ERR_INT_EN	reg.h	610;"	d
B_AX_TXPKTCTRL_ERR_FLAG	reg.h	290;"	d
B_AX_TXPKT_CTRL_CLK_EN	reg.h	215;"	d
B_AX_TXPKT_CTRL_EN	reg.h	202;"	d
B_AX_TXPWR_CTRL_ERR_IND	reg.h	689;"	d
B_AX_TXSC_20M_MASK	reg.h	683;"	d
B_AX_TXSC_40M_MASK	reg.h	682;"	d
B_AX_TXSC_80M_MASK	reg.h	681;"	d
B_AX_TX_CTRL_DEBUG_SEL_MASK	reg.h	1098;"	d
B_AX_TX_CTRL_INFO_P0_MASK	reg.h	1102;"	d
B_AX_TX_CTRL_INFO_P1_MASK	reg.h	1106;"	d
B_AX_TX_PARTIAL_MODE	reg.h	559;"	d
B_AX_TX_PLT_GNT_BT_RX	reg.h	1021;"	d
B_AX_TX_PLT_GNT_BT_TX	reg.h	1022;"	d
B_AX_TX_PLT_GNT_LTE_RX	reg.h	1020;"	d
B_AX_TX_PLT_GNT_WL	reg.h	1023;"	d
B_AX_TX_RECORD_PKTID_ERR_INT_EN	reg.h	1039;"	d
B_AX_TX_STOP1_ALL	pci.h	237;"	d
B_AX_TX_STOP2_ALL	pci.h	242;"	d
B_AX_TX_STUCK	pci.h	302;"	d
B_AX_TX_TRUNC_MODE	pci.h	213;"	d
B_AX_UART_HCISYS_PWR_STE_MASK	reg.h	150;"	d
B_AX_UC_MGNT_DEC	reg.h	564;"	d
B_AX_UID_FILTER_MASK	reg.h	1275;"	d
B_AX_UNSPT_FILTER_MASK	reg.h	1277;"	d
B_AX_UNSPT_FILTER_SH	reg.h	1276;"	d
B_AX_USB_HCISYS_PWR_STE_MASK	reg.h	152;"	d
B_AX_USE_PG_MASK	reg.h	345;"	d
B_AX_VHT_MU_SIGB_CRC_CHK	reg.h	1266;"	d
B_AX_VHT_SU_SIGB_CRC_CHK	reg.h	1267;"	d
B_AX_WCPU_EN	reg.h	79;"	d
B_AX_WCPU_FWDL_EN	reg.h	108;"	d
B_AX_WCPU_FWDL_STS_MASK	reg.h	105;"	d
B_AX_WDE_BUF_MGN_INI_RDY	reg.h	413;"	d
B_AX_WDE_DFI_ACTIVE	reg.h	416;"	d
B_AX_WDE_DFI_ADDR_MASK	reg.h	418;"	d
B_AX_WDE_DFI_DATA_MASK	reg.h	420;"	d
B_AX_WDE_DFI_TRGSEL_MASK	reg.h	417;"	d
B_AX_WDE_DLE_ERR_FLAG	reg.h	291;"	d
B_AX_WDE_EMPTY_QTA_DMAC_CPUIO	reg.h	269;"	d
B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU	reg.h	271;"	d
B_AX_WDE_EMPTY_QTA_DMAC_HIF	reg.h	273;"	d
B_AX_WDE_EMPTY_QTA_DMAC_PKTIN	reg.h	270;"	d
B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU	reg.h	272;"	d
B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC	reg.h	282;"	d
B_AX_WDE_EMPTY_QUE_CMAC0_MBH	reg.h	281;"	d
B_AX_WDE_EMPTY_QUE_CMAC0_WMM0	reg.h	279;"	d
B_AX_WDE_EMPTY_QUE_CMAC0_WMM1	reg.h	278;"	d
B_AX_WDE_EMPTY_QUE_CMAC1_MBH	reg.h	280;"	d
B_AX_WDE_EMPTY_QUE_DMAC_PKTIN	reg.h	274;"	d
B_AX_WDE_EMPTY_QUE_OTHERS	reg.h	277;"	d
B_AX_WDE_FREE_PAGE_NUM_MASK	reg.h	391;"	d
B_AX_WDE_MAX_SIZE_MASK	reg.h	396;"	d
B_AX_WDE_MIN_SIZE_MASK	reg.h	397;"	d
B_AX_WDE_PAGE_SEL_MASK	reg.h	390;"	d
B_AX_WDE_Q_MGN_INI_RDY	reg.h	412;"	d
B_AX_WDE_START_BOUND_MASK	reg.h	389;"	d
B_AX_WDRLS_CTL_FRZTO_ERR_INT_EN	reg.h	480;"	d
B_AX_WDRLS_CTL_PLPKTID_ISNULL_ERR_INT_EN	reg.h	481;"	d
B_AX_WDRLS_CTL_WDPKTID_ISNULL_ERR_INT_EN	reg.h	482;"	d
B_AX_WDRLS_ERR_FLAG	reg.h	295;"	d
B_AX_WDRLS_MODE_MASK	reg.h	461;"	d
B_AX_WDRLS_PLEBREQ_PKTID_ISNULL_ERR_INT_EN	reg.h	478;"	d
B_AX_WDRLS_PLEBREQ_TO_ERR_INT_EN	reg.h	479;"	d
B_AX_WDRLS_RPT0_AGGNUM0_ERR_INT_EN	reg.h	477;"	d
B_AX_WDRLS_RPT0_FRZTO_ERR_INT_EN	reg.h	476;"	d
B_AX_WDRLS_RPT1_AGGNUM0_ERR_INT_EN	reg.h	475;"	d
B_AX_WDRLS_RPT1_FRZTO_ERR_INT_EN	reg.h	474;"	d
B_AX_WDT_PTFM_INT_EN	reg.h	169;"	d
B_AX_WD_ADDR_INFO_LENGTH	reg.h	530;"	d
B_AX_WD_BUF_REQ_EXEC	reg.h	492;"	d
B_AX_WD_BUF_REQ_LEN_MASK	reg.h	494;"	d
B_AX_WD_BUF_REQ_QUOTA_ID_MASK	reg.h	493;"	d
B_AX_WD_BUF_STAT_DONE	reg.h	498;"	d
B_AX_WD_BUF_STAT_PKTID_MASK	reg.h	499;"	d
B_AX_WD_CPUQ_OP_END_PKTID_MASK	reg.h	518;"	d
B_AX_WD_CPUQ_OP_EXEC	reg.h	503;"	d
B_AX_WD_CPUQ_OP_PKTID_MASK	reg.h	523;"	d
B_AX_WD_CPUQ_OP_STAT_DONE	reg.h	522;"	d
B_AX_WD_CPUQ_OP_STRT_PKTID_MASK	reg.h	517;"	d
B_AX_WD_ITVL_ACT	pci.h	281;"	d
B_AX_WD_ITVL_IDLE	pci.h	280;"	d
B_AX_WD_PAGE_64B_SEL	reg.h	299;"	d
B_AX_WD_RLS_CLK_EN	reg.h	213;"	d
B_AX_WD_RLS_EN	reg.h	200;"	d
B_AX_WHOLE_SYS_PWR_STE_MASK	reg.h	148;"	d
B_AX_WLMAC_PWR_STE_MASK	reg.h	149;"	d
B_AX_WLOCK_1C_BIT6	reg.h	23;"	d
B_AX_WLRF1_CTRL_1	reg.h	143;"	d
B_AX_WLRF1_CTRL_7	reg.h	142;"	d
B_AX_WLRF_CTRL_1	reg.h	145;"	d
B_AX_WLRF_CTRL_7	reg.h	144;"	d
B_AX_WL_ACT_MASK_ENABLE	reg.h	1451;"	d
B_AX_WL_ACT_MSK	reg.h	1449;"	d
B_AX_WL_EECS_EXT_32K_SEL	reg.h	46;"	d
B_AX_WL_RX_CTRL	reg.h	1517;"	d
B_AX_WL_SEC_BONDING_OPT_STS	reg.h	47;"	d
B_AX_WL_SW_CTRL_WL_PRIORITY	reg.h	1498;"	d
B_AX_WMAC_BESP_EARLY_TXBA	reg.h	1135;"	d
B_AX_WMAC_LDPC_EN	reg.h	1132;"	d
B_AX_WMAC_RESP_STBC_EN	reg.h	1123;"	d
B_AX_WMAC_RFMOD_MASK	reg.h	664;"	d
B_AX_WMAC_RXFTM_TXACKBWEQ	reg.h	1125;"	d
B_AX_WMAC_RXFTM_TXACK_SC	reg.h	1124;"	d
B_AX_WMAC_RX_ERR_IND	reg.h	688;"	d
B_AX_WMAC_SGIEN	reg.h	1133;"	d
B_AX_WMAC_SPEC_SIFS_CCK_MASK	reg.h	1137;"	d
B_AX_WMAC_SPEC_SIFS_OFDM_MASK	reg.h	1136;"	d
B_AX_WMAC_SPLCPEN	reg.h	1134;"	d
B_AX_WMAC_TX_ERR_IND	reg.h	687;"	d
B_AX_WMAC_TX_TF_INFO_P0_MASK	reg.h	1162;"	d
B_AX_WMAC_TX_TF_INFO_P1_MASK	reg.h	1166;"	d
B_AX_WMAC_TX_TF_INFO_SEL_MASK	reg.h	1158;"	d
B_AX_WPDMA_BUSY	pci.h	272;"	d
B_AX_WP_AVAL_PG_MASK	reg.h	386;"	d
B_AX_WP_THRD_MASK	reg.h	383;"	d
B_AX_WSEC_ERR_FLAG	reg.h	294;"	d
B_AX_XTAL_SC_LPS	reg.h	134;"	d
B_AX_XTAL_SC_MASK	reg.h	137;"	d
B_AX_XTAL_SC_XI_MASK	reg.h	136;"	d
B_AX_XTAL_SC_XO_MASK	reg.h	135;"	d
B_BANDEDGE_EN	reg.h	1859;"	d
B_BSS_CLR_MAP_STAID	reg.h	1848;"	d
B_BSS_CLR_MAP_TGT	reg.h	1847;"	d
B_BSS_CLR_MAP_VLD0	reg.h	1846;"	d
B_BTC_PRI_MASK_TX_RESP_V1	reg.h	1431;"	d
B_BTC_WL_TX_POWER_SIGN	coex.c	1461;"	d	file:
B_CCX_EDCCA_OPT_MSK	reg.h	1699;"	d
B_CCX_EN_MSK	reg.h	1702;"	d
B_CCX_TRIG_OPT_MSK	reg.h	1701;"	d
B_CFIR_LUT_G2	reg.h	2107;"	d
B_CFIR_LUT_G3	reg.h	2106;"	d
B_CFIR_LUT_GP	reg.h	2108;"	d
B_CFIR_LUT_SEL	reg.h	2105;"	d
B_CFO_COMP_VALID_BIT	reg.h	1942;"	d
B_CFO_COMP_VAL_MSK	reg.h	1944;"	d
B_CFO_COMP_WEIGHT_MSK	reg.h	1943;"	d
B_CFO_TRK_MSK	reg.h	1851;"	d
B_CHBW_MOD_PRICH	reg.h	1937;"	d
B_CHBW_MOD_SBW	reg.h	1938;"	d
B_COEF_SEL_IQC	reg.h	2083;"	d
B_COEF_SEL_MDPD	reg.h	2084;"	d
B_DCFO	reg.h	1840;"	d
B_DCFO_COMP_S0_MSK	reg.h	1853;"	d
B_DCFO_OPT_EN	reg.h	1857;"	d
B_DCFO_WEIGHT_MSK	reg.h	1855;"	d
B_DPD_OFT_ADDR	reg.h	1948;"	d
B_DPD_OFT_EN	reg.h	1946;"	d
B_DPK_CFG2_ST	reg.h	2064;"	d
B_DPK_CFG_IDX	reg.h	2062;"	d
B_DPK_CTL_EN	reg.h	2060;"	d
B_DPK_TRK_DIS	reg.h	2074;"	d
B_FC0_BW_INV	reg.h	1934;"	d
B_FC0_BW_SET	reg.h	1935;"	d
B_GAPK_ADR	reg.h	2071;"	d
B_IFSCNT_DONE_MSK	reg.h	1784;"	d
B_IFSCNT_TOTAL_CNT_MSK	reg.h	1785;"	d
B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK	reg.h	1762;"	d
B_IFS_CLM_CCK_FA_MSK	reg.h	1765;"	d
B_IFS_CLM_COUNTER_UNIT_MSK	reg.h	1705;"	d
B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK	reg.h	1758;"	d
B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK	reg.h	1761;"	d
B_IFS_CLM_OFDM_FA_MSK	reg.h	1764;"	d
B_IFS_CLM_PERIOD_MSK	reg.h	1704;"	d
B_IFS_CLM_TX_CNT_MSK	reg.h	1759;"	d
B_IFS_COLLECT_EN	reg.h	1707;"	d
B_IFS_COUNTER_CLR_MSK	reg.h	1706;"	d
B_IFS_T1_AVG_MSK	reg.h	1773;"	d
B_IFS_T1_CCA_MSK	reg.h	1779;"	d
B_IFS_T1_EN_MSK	reg.h	1710;"	d
B_IFS_T1_HIS_MSK	reg.h	1770;"	d
B_IFS_T1_TH_HIGH_MSK	reg.h	1709;"	d
B_IFS_T1_TH_LOW_MSK	reg.h	1711;"	d
B_IFS_T2_AVG_MSK	reg.h	1772;"	d
B_IFS_T2_CCA_MSK	reg.h	1778;"	d
B_IFS_T2_EN_MSK	reg.h	1714;"	d
B_IFS_T2_HIS_MSK	reg.h	1769;"	d
B_IFS_T2_TH_HIGH_MSK	reg.h	1713;"	d
B_IFS_T2_TH_LOW_MSK	reg.h	1715;"	d
B_IFS_T3_AVG_MSK	reg.h	1776;"	d
B_IFS_T3_CCA_MSK	reg.h	1782;"	d
B_IFS_T3_EN_MSK	reg.h	1718;"	d
B_IFS_T3_HIS_MSK	reg.h	1768;"	d
B_IFS_T3_TH_HIGH_MSK	reg.h	1717;"	d
B_IFS_T3_TH_LOW_MSK	reg.h	1719;"	d
B_IFS_T4_AVG_MSK	reg.h	1775;"	d
B_IFS_T4_CCA_MSK	reg.h	1781;"	d
B_IFS_T4_EN_MSK	reg.h	1722;"	d
B_IFS_T4_HIS_MSK	reg.h	1767;"	d
B_IFS_T4_TH_HIGH_MSK	reg.h	1721;"	d
B_IFS_T4_TH_LOW_MSK	reg.h	1723;"	d
B_IOQ_IQK_DPK_EN	reg.h	1727;"	d
B_IQKCH_BAND	reg.h	2154;"	d
B_IQKCH_BW	reg.h	2153;"	d
B_IQKCH_CH	reg.h	2152;"	d
B_IQKINF2_FCNT	reg.h	2156;"	d
B_IQKINF2_KCNT	reg.h	2157;"	d
B_IQKINF2_NCTLV	reg.h	2158;"	d
B_IQKINF_FAIL	reg.h	2146;"	d
B_IQKINF_FAIL_RXGRP	reg.h	2144;"	d
B_IQKINF_FAIL_TXGRP	reg.h	2145;"	d
B_IQKINF_FCOR	reg.h	2150;"	d
B_IQKINF_FFIN	reg.h	2149;"	d
B_IQKINF_FTX	reg.h	2148;"	d
B_IQKINF_F_RX	reg.h	2147;"	d
B_IQKINF_VER	reg.h	2143;"	d
B_IQK_CFG_SET	reg.h	2046;"	d
B_IQK_DIF1_TXPI	reg.h	2039;"	d
B_IQK_DIF2_RXPI	reg.h	2041;"	d
B_IQK_DIF4_RXT	reg.h	2044;"	d
B_IQK_DIF4_TXT	reg.h	2043;"	d
B_IQK_DIF_TRX	reg.h	2037;"	d
B_IQK_RES_RXCFIR	reg.h	2088;"	d
B_IQK_RES_TXCFIR	reg.h	2087;"	d
B_KIP_DBCC	reg.h	2096;"	d
B_KIP_IQP_IQSW	reg.h	2117;"	d
B_KIP_RFGAIN	reg.h	2097;"	d
B_KIP_RPT1_SEL	reg.h	2068;"	d
B_KIP_RPT_SEL	reg.h	2119;"	d
B_LDL_NORM_OP	reg.h	2058;"	d
B_LDL_NORM_PN	reg.h	2057;"	d
B_LOAD_COEF_AUTO	reg.h	2124;"	d
B_LOAD_COEF_CFIR	reg.h	2123;"	d
B_LOAD_COEF_MDPD	reg.h	2122;"	d
B_MAC_AX_BTGS1_NOTIFY	reg.h	85;"	d
B_MAC_AX_SB_DRV_MASK	reg.h	84;"	d
B_MAC_AX_SB_FW_MASK	reg.h	83;"	d
B_MAC_SEL_DPD_EN	reg.h	1688;"	d
B_MAC_SEL_MOD	reg.h	1687;"	d
B_MAC_SEL_PWR_EN	reg.h	1689;"	d
B_MDPK_SYNC_MAN	reg.h	2051;"	d
B_MDPK_SYNC_SEL	reg.h	2050;"	d
B_MEASUREMENT_TRIG_MSK	reg.h	1700;"	d
B_NCTL_CFG_SPAGE	reg.h	2029;"	d
B_NCTL_N1_CIP	reg.h	2033;"	d
B_NCTL_RPT_FLG	reg.h	2031;"	d
B_NDP_RU_BRK	reg.h	1734;"	d
B_P0_EN_SOUND_WO_NDP	reg.h	1729;"	d
B_P0_NBIIDX_NOTCH_EN	reg.h	1910;"	d
B_P0_NBIIDX_VAL	reg.h	1909;"	d
B_P0_NRBW_DBG	reg.h	1743;"	d
B_P0_RFCTM_VAL	reg.h	1960;"	d
B_P0_RSTB_WATCH_DOG	reg.h	1659;"	d
B_P0_RXCK_BW3	reg.h	1741;"	d
B_P0_RXCK_ON	reg.h	1740;"	d
B_P0_RXCK_VAL	reg.h	1739;"	d
B_P0_TMETER	reg.h	1950;"	d
B_P0_TMETER_DIS	reg.h	1951;"	d
B_P0_TMETER_TRK	reg.h	1952;"	d
B_P0_TSSI_AVG	reg.h	1958;"	d
B_P0_TSSI_MV_AVG	reg.h	1968;"	d
B_P0_TSSI_OFT	reg.h	1956;"	d
B_P0_TSSI_OFT_EN	reg.h	1955;"	d
B_P0_TSSI_TRK_EN	reg.h	1954;"	d
B_P0_TXDPD	reg.h	1963;"	d
B_P0_TXPW_RSTB_MANON	reg.h	1965;"	d
B_P0_TXPW_RSTB_TSSI	reg.h	1966;"	d
B_P1_DBGMOD_ON	reg.h	1825;"	d
B_P1_EN_SOUND_WO_NDP	reg.h	1823;"	d
B_P1_MODE_SEL	reg.h	1912;"	d
B_P1_NBIIDX_NOTCH_EN	reg.h	1927;"	d
B_P1_NBIIDX_VAL	reg.h	1926;"	d
B_P1_RFCTM_VAL	reg.h	2003;"	d
B_P1_RSTB_WATCH_DOG	reg.h	1660;"	d
B_P1_TMETER	reg.h	1992;"	d
B_P1_TMETER_DIS	reg.h	1993;"	d
B_P1_TMETER_TRK	reg.h	1994;"	d
B_P1_TSSI_AVG	reg.h	2000;"	d
B_P1_TSSI_MV_AVG	reg.h	2008;"	d
B_P1_TSSI_OFT	reg.h	1998;"	d
B_P1_TSSI_OFT_EN	reg.h	1997;"	d
B_P1_TSSI_TRK_EN	reg.h	1996;"	d
B_P1_TXPW_RSTB_MANON	reg.h	2005;"	d
B_P1_TXPW_RSTB_TSSI	reg.h	2006;"	d
B_PATH0_BTG_SHEN	reg.h	1901;"	d
B_PATH0_IB_PBK_MSK	reg.h	1895;"	d
B_PATH0_IB_PKPW_MSK	reg.h	1867;"	d
B_PATH0_LNA_ERR_G0_A_MSK	reg.h	1871;"	d
B_PATH0_LNA_ERR_G0_G_MSK	reg.h	1870;"	d
B_PATH0_LNA_ERR_G1_A_MSK	reg.h	1869;"	d
B_PATH0_LNA_ERR_G1_G_MSK	reg.h	1875;"	d
B_PATH0_LNA_ERR_G2_A_MSK	reg.h	1874;"	d
B_PATH0_LNA_ERR_G2_G_MSK	reg.h	1873;"	d
B_PATH0_LNA_ERR_G3_A_MSK	reg.h	1880;"	d
B_PATH0_LNA_ERR_G3_G_MSK	reg.h	1879;"	d
B_PATH0_LNA_ERR_G4_A_MSK	reg.h	1878;"	d
B_PATH0_LNA_ERR_G4_G_MSK	reg.h	1877;"	d
B_PATH0_LNA_ERR_G5_A_MSK	reg.h	1884;"	d
B_PATH0_LNA_ERR_G5_G_MSK	reg.h	1883;"	d
B_PATH0_LNA_ERR_G6_A_MSK	reg.h	1882;"	d
B_PATH0_LNA_ERR_G6_G_MSK	reg.h	1886;"	d
B_PATH0_LNA_INIT_IDX_MSK	reg.h	1899;"	d
B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK	reg.h	1905;"	d
B_PATH0_RXB_INIT_IDX_MSK	reg.h	1897;"	d
B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK	reg.h	1907;"	d
B_PATH0_TIA_ERR_G0_A_MSK	reg.h	1889;"	d
B_PATH0_TIA_ERR_G0_G_MSK	reg.h	1888;"	d
B_PATH0_TIA_ERR_G1_A_MSK	reg.h	1893;"	d
B_PATH0_TIA_ERR_G1_G_MSK	reg.h	1892;"	d
B_PATH0_TIA_ERR_G1_SEL	reg.h	1891;"	d
B_PATH0_TIA_INIT_IDX_MSK	reg.h	1903;"	d
B_PATH1_BTG_SHEN	reg.h	1918;"	d
B_PATH1_LNA_INIT_IDX_MSK	reg.h	1914;"	d
B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK	reg.h	1922;"	d
B_PATH1_RXB_INIT_IDX_MSK	reg.h	1920;"	d
B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK	reg.h	1924;"	d
B_PATH1_TIA_INIT_IDX_MSK	reg.h	1916;"	d
B_PD_HIT_DIS	reg.h	1725;"	d
B_PMAC_CTX_EN	reg.h	1694;"	d
B_PMAC_GNT_P1	reg.h	1680;"	d
B_PMAC_GNT_P2	reg.h	1681;"	d
B_PMAC_GNT_RXEN	reg.h	1679;"	d
B_PMAC_GNT_TXEN	reg.h	1678;"	d
B_PMAC_OPT1_MSK	reg.h	1683;"	d
B_PMAC_PTX_EN	reg.h	1695;"	d
B_PMAC_RXMOD_MSK	reg.h	1685;"	d
B_PMAC_TXEN_DIS	reg.h	1691;"	d
B_PMAC_TX_CNT_MSK	reg.h	1697;"	d
B_PMAC_TX_PRD_MSK	reg.h	1693;"	d
B_PRT_COM_CORI	reg.h	2081;"	d
B_PRT_COM_CORV	reg.h	2078;"	d
B_PRT_COM_DCI	reg.h	2077;"	d
B_PRT_COM_DCQ	reg.h	2079;"	d
B_PRT_COM_GL	reg.h	2080;"	d
B_PRT_COM_SYNERR	reg.h	2076;"	d
B_RFGAIN_BND	reg.h	2102;"	d
B_RFGAIN_PAD	reg.h	2099;"	d
B_RFGAIN_TXBB	reg.h	2100;"	d
B_RSTB_ASYNC_ALL	reg.h	1676;"	d
B_RXCCA_DIS	reg.h	1815;"	d
B_RXIQC_BYPASS	reg.h	2091;"	d
B_RXIQC_BYPASS2	reg.h	2092;"	d
B_RXIQC_NEWP	reg.h	2093;"	d
B_RXIQC_NEWX	reg.h	2094;"	d
B_RXSCOBC_TH	reg.h	1819;"	d
B_RXSCOCCK_TH	reg.h	1821;"	d
B_RXSC_EN	reg.h	1817;"	d
B_S0_ADDCK_I	reg.h	1794;"	d
B_S0_ADDCK_Q	reg.h	1795;"	d
B_S0_DACKI2_K	reg.h	1977;"	d
B_S0_DACKI7_K	reg.h	1979;"	d
B_S0_DACKI8_K	reg.h	1981;"	d
B_S0_DACKI_AR	reg.h	1974;"	d
B_S0_DACKI_EN	reg.h	1975;"	d
B_S0_DACKQ2_K	reg.h	1986;"	d
B_S0_DACKQ7_K	reg.h	1988;"	d
B_S0_DACKQ8_K	reg.h	1990;"	d
B_S0_DACKQ_AR	reg.h	1983;"	d
B_S0_DACKQ_EN	reg.h	1984;"	d
B_S0_RXDC2_AVG	reg.h	1749;"	d
B_S0_RXDC2_MEN	reg.h	1750;"	d
B_S0_RXDC2_Q2	reg.h	1751;"	d
B_S0_RXDC2_SEL	reg.h	1748;"	d
B_S0_RXDC_I	reg.h	1745;"	d
B_S0_RXDC_Q	reg.h	1746;"	d
B_S1_ADDCK_I	reg.h	1837;"	d
B_S1_ADDCK_Q	reg.h	1838;"	d
B_S1_DACKI2_K	reg.h	2014;"	d
B_S1_DACKI8_K	reg.h	2018;"	d
B_S1_DACKI_AR	reg.h	2011;"	d
B_S1_DACKI_EN	reg.h	2012;"	d
B_S1_DACKI_K	reg.h	2016;"	d
B_S1_DACKQ2_K	reg.h	2023;"	d
B_S1_DACKQ7_K	reg.h	2025;"	d
B_S1_DACKQ8_K	reg.h	2027;"	d
B_S1_DACKQ_AR	reg.h	2020;"	d
B_S1_DACKQ_EN	reg.h	2021;"	d
B_S1_RXDC2_EN	reg.h	1830;"	d
B_S1_RXDC2_Q2	reg.h	1832;"	d
B_S1_RXDC2_SEL	reg.h	1831;"	d
B_S1_RXDC_I	reg.h	1827;"	d
B_S1_RXDC_Q	reg.h	1828;"	d
B_SEG0CSI_EN	reg.h	1844;"	d
B_SEG0CSI_IDX	reg.h	1842;"	d
B_SEG0R_PD_LOWER_BOUND_MSK	reg.h	1930;"	d
B_SEG0R_PD_SPATIAL_REUSE_EN_MSK	reg.h	1929;"	d
B_SPOOF_ASYNC_RST	reg.h	1731;"	d
B_TPG_MOD_F	reg.h	2048;"	d
B_TSSI_THER	reg.h	1789;"	d
B_TSSI_WL_TX_POWER_SIGN	coex.c	1462;"	d	file:
B_TXAGC_BB	reg.h	1792;"	d
B_TXAGC_BB_OFT	reg.h	1791;"	d
B_TXAGC_BB_S1	reg.h	1835;"	d
B_TXAGC_BB_S1_OFT	reg.h	1834;"	d
B_TXAGC_RFK_CH0	reg.h	2114;"	d
B_TXAGC_TP	reg.h	1787;"	d
B_TXFIR_C01	reg.h	1799;"	d
B_TXFIR_C23	reg.h	1801;"	d
B_TXFIR_C45	reg.h	1803;"	d
B_TXFIR_C67	reg.h	1805;"	d
B_TXFIR_C89	reg.h	1807;"	d
B_TXFIR_CAB	reg.h	1809;"	d
B_TXFIR_CCD	reg.h	1811;"	d
B_TXFIR_CEF	reg.h	1813;"	d
B_TXGAIN_SCALE_EN	reg.h	1970;"	d
B_TXGAIN_SCALE_OFT	reg.h	1971;"	d
B_TXNSS_MAP_MSK	reg.h	1865;"	d
B_TXPATH_SEL_MSK	reg.h	1861;"	d
B_TXPWR_MSK	reg.h	1863;"	d
B_UPD_CLK_ADC_ON	reg.h	1673;"	d
B_UPD_CLK_ADC_VAL	reg.h	1674;"	d
B_UPD_P0_EN	reg.h	1661;"	d
CASE_BTC_ACT_STR	coex.c	4866;"	d	file:
CASE_BTC_POLICY_STR	coex.c	4867;"	d	file:
CASE_BTC_RSN_STR	coex.c	4865;"	d	file:
CCTL_INFO_SIZE	mac.h	244;"	d
CCX_MAX_PERIOD	phy.h	64;"	d
CCX_MAX_PERIOD_UNIT	phy.h	65;"	d
CCX_US_BASE_RATIO	phy.h	129;"	d
CFO_COMP_PERIOD	phy.h	60;"	d
CFO_COMP_WEIGHT	phy.h	61;"	d
CFO_PERIOD_CNT	phy.h	57;"	d
CFO_SW_COMP_FINE_TUNE	phy.h	56;"	d
CFO_TP_LOWER	phy.h	59;"	d
CFO_TP_UPPER	phy.h	58;"	d
CFO_TRACK_MAX_USER	core.h	32;"	d
CFO_TRK_ENABLE_TH	phy.h	50;"	d
CFO_TRK_STOP_TH	phy.h	55;"	d
CFO_TRK_STOP_TH_1	phy.h	54;"	d
CFO_TRK_STOP_TH_2	phy.h	53;"	d
CFO_TRK_STOP_TH_3	phy.h	52;"	d
CFO_TRK_STOP_TH_4	phy.h	51;"	d
CHIP_CAV	core.h	/^	CHIP_CAV,$/;"	e	enum:rtw89_cv
CHIP_CBV	core.h	/^	CHIP_CBV,$/;"	e	enum:rtw89_cv
CHIP_CCV	core.h	/^	CHIP_CCV,$/;"	e	enum:rtw89_cv
CHIP_CDV	core.h	/^	CHIP_CDV,$/;"	e	enum:rtw89_cv
CHIP_CEV	core.h	/^	CHIP_CEV,$/;"	e	enum:rtw89_cv
CHIP_CFV	core.h	/^	CHIP_CFV,$/;"	e	enum:rtw89_cv
CHIP_CV_INVALID	core.h	/^	CHIP_CV_INVALID = CHIP_CV_MAX,$/;"	e	enum:rtw89_cv
CHIP_CV_MAX	core.h	/^	CHIP_CV_MAX,$/;"	e	enum:rtw89_cv
CMAC1_END_ADDR	reg.h	1484;"	d
CMAC1_START_ADDR	reg.h	1483;"	d
CMAC_TBL_BASE_ADDR	mac.h	234;"	d
CONT_TX	rtw8852a.h	/^	CONT_TX$/;"	e	enum:rtw8852a_pmac_mode
COUNTRY_REGD	regd.c	8;"	d	file:
CPUIO_OP_CMD_DEQ	mac.h	/^	CPUIO_OP_CMD_DEQ = 8,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_DEQ_ENQ_ALL	mac.h	/^	CPUIO_OP_CMD_DEQ_ENQ_ALL = 9,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL	mac.h	/^	CPUIO_OP_CMD_DEQ_ENQ_TO_TAIL = 12$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_ENQ_TO_HEAD	mac.h	/^	CPUIO_OP_CMD_ENQ_TO_HEAD = 5,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_ENQ_TO_TAIL	mac.h	/^	CPUIO_OP_CMD_ENQ_TO_TAIL = 4,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_GET_1ST_PID	mac.h	/^	CPUIO_OP_CMD_GET_1ST_PID = 0,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPUIO_OP_CMD_GET_NEXT_PID	mac.h	/^	CPUIO_OP_CMD_GET_NEXT_PID = 1,$/;"	e	enum:rtw89_mac_cpuio_op_cmd_type
CPWM_SEQ_NUM_MAX	reg.h	120;"	d
CSI_INIT_RATE_HE	reg.h	1247;"	d
CSI_INIT_RATE_HT	reg.h	1249;"	d
CSI_INIT_RATE_VHT	reg.h	1248;"	d
CSI_RRSC_BMAP	reg.h	1240;"	d
CXBCN_ALL	core.h	/^	CXBCN_ALL = 0x0,$/;"	e	enum:__anon7
CXBCN_ALL_OK	core.h	/^	CXBCN_ALL_OK,$/;"	e	enum:__anon7
CXBCN_BT_OK	core.h	/^	CXBCN_BT_OK,$/;"	e	enum:__anon7
CXBCN_BT_SLOT	core.h	/^	CXBCN_BT_SLOT,$/;"	e	enum:__anon7
CXBCN_MAX	core.h	/^	CXBCN_MAX$/;"	e	enum:__anon7
CXDRVINFO_CTRL	fw.h	/^	CXDRVINFO_CTRL,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_DBCC	fw.h	/^	CXDRVINFO_DBCC,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_INIT	fw.h	/^	CXDRVINFO_INIT = 0,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_MAX	fw.h	/^	CXDRVINFO_MAX,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_RFK	fw.h	/^	CXDRVINFO_RFK,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_ROLE	fw.h	/^	CXDRVINFO_ROLE,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_RUN	fw.h	/^	CXDRVINFO_RUN,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_SCAN	fw.h	/^	CXDRVINFO_SCAN,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXDRVINFO_SMAP	fw.h	/^	CXDRVINFO_SMAP,$/;"	e	enum:rtw89_btc_cxdrvinfo
CXECTL_B2	core.h	/^	CXECTL_B2 = 0x1, \/* allow B2 (beacon-early) *\/$/;"	e	enum:rtw89_fbtc_ext_ctrl_type
CXECTL_EXT	core.h	/^	CXECTL_EXT = 0x2,$/;"	e	enum:rtw89_fbtc_ext_ctrl_type
CXECTL_MAX	core.h	/^	CXECTL_MAX$/;"	e	enum:rtw89_fbtc_ext_ctrl_type
CXECTL_OFF	core.h	/^	CXECTL_OFF = 0x0, \/* tdma off *\/$/;"	e	enum:rtw89_fbtc_ext_ctrl_type
CXFLC_CTS	coex.c	/^	CXFLC_CTS = 0x3,$/;"	e	enum:btc_fbtc_tdma_rx_flow_ctrl	file:
CXFLC_MAX	coex.c	/^	CXFLC_MAX$/;"	e	enum:btc_fbtc_tdma_rx_flow_ctrl	file:
CXFLC_NULLP	coex.c	/^	CXFLC_NULLP = 0x1,$/;"	e	enum:btc_fbtc_tdma_rx_flow_ctrl	file:
CXFLC_OFF	coex.c	/^	CXFLC_OFF = 0x0,$/;"	e	enum:btc_fbtc_tdma_rx_flow_ctrl	file:
CXFLC_QOSNULL	coex.c	/^	CXFLC_QOSNULL = 0x2,$/;"	e	enum:btc_fbtc_tdma_rx_flow_ctrl	file:
CXMREG_MAX	core.h	1272;"	d
CXPOLICY_MAX	coex.c	/^	CXPOLICY_MAX,$/;"	e	enum:btc_btf_set_cx_policy	file:
CXPOLICY_SLOT	coex.c	/^	CXPOLICY_SLOT = 0x1,$/;"	e	enum:btc_btf_set_cx_policy	file:
CXPOLICY_TDMA	coex.c	/^	CXPOLICY_TDMA = 0x0,$/;"	e	enum:btc_btf_set_cx_policy	file:
CXPOLICY_TYPE	coex.c	/^	CXPOLICY_TYPE = 0x2,$/;"	e	enum:btc_btf_set_cx_policy	file:
CXSTEP_EVNT	core.h	/^	CXSTEP_EVNT = 0x1,$/;"	e	enum:__anon10
CXSTEP_MAX	core.h	/^	CXSTEP_MAX,$/;"	e	enum:__anon10
CXSTEP_NONE	core.h	/^	CXSTEP_NONE = 0x0,$/;"	e	enum:__anon10
CXSTEP_SLOT	core.h	/^	CXSTEP_SLOT = 0x2,$/;"	e	enum:__anon10
CXSTYPE_NUM	core.h	/^	CXSTYPE_NUM,$/;"	e	enum:btc_slot_type
CXST_B1	core.h	/^	CXST_B1 = 0x5,$/;"	e	enum:rtw89_btc_cxst_state
CXST_B1FDD	core.h	/^	CXST_B1FDD = 0x11,$/;"	e	enum:rtw89_btc_cxst_state
CXST_B2	core.h	/^	CXST_B2 = 0x6,$/;"	e	enum:rtw89_btc_cxst_state
CXST_B2W	core.h	/^	CXST_B2W = 0x1,$/;"	e	enum:rtw89_btc_cxst_state
CXST_B3	core.h	/^	CXST_B3 = 0x7,$/;"	e	enum:rtw89_btc_cxst_state
CXST_B4	core.h	/^	CXST_B4 = 0x8,$/;"	e	enum:rtw89_btc_cxst_state
CXST_BLK	core.h	/^	CXST_BLK = 0xa,$/;"	e	enum:rtw89_btc_cxst_state
CXST_E2G	core.h	/^	CXST_E2G = 0xb,$/;"	e	enum:rtw89_btc_cxst_state
CXST_E5G	core.h	/^	CXST_E5G = 0xc,$/;"	e	enum:rtw89_btc_cxst_state
CXST_EBT	core.h	/^	CXST_EBT = 0xd,$/;"	e	enum:rtw89_btc_cxst_state
CXST_ENULL	core.h	/^	CXST_ENULL = 0xe,$/;"	e	enum:rtw89_btc_cxst_state
CXST_LK	core.h	/^	CXST_LK = 0x9,$/;"	e	enum:rtw89_btc_cxst_state
CXST_MAX	core.h	/^	CXST_MAX = 0x12,$/;"	e	enum:rtw89_btc_cxst_state
CXST_OFF	core.h	/^	CXST_OFF = 0x0,$/;"	e	enum:rtw89_btc_cxst_state
CXST_W1	core.h	/^	CXST_W1 = 0x2,$/;"	e	enum:rtw89_btc_cxst_state
CXST_W1FDD	core.h	/^	CXST_W1FDD = 0x10,$/;"	e	enum:rtw89_btc_cxst_state
CXST_W2	core.h	/^	CXST_W2 = 0x3,$/;"	e	enum:rtw89_btc_cxst_state
CXST_W2B	core.h	/^	CXST_W2B = 0x4,$/;"	e	enum:rtw89_btc_cxst_state
CXST_WLK	core.h	/^	CXST_WLK = 0xf,$/;"	e	enum:rtw89_btc_cxst_state
CXTDMA_AUTO	coex.c	/^	CXTDMA_AUTO = 0x2,$/;"	e	enum:btc_fbtc_tdma_type	file:
CXTDMA_AUTO2	coex.c	/^	CXTDMA_AUTO2 = 0x3,$/;"	e	enum:btc_fbtc_tdma_type	file:
CXTDMA_FIX	coex.c	/^	CXTDMA_FIX = 0x1,$/;"	e	enum:btc_fbtc_tdma_type	file:
CXTDMA_MAX	coex.c	/^	CXTDMA_MAX$/;"	e	enum:btc_fbtc_tdma_type	file:
CXTDMA_OFF	coex.c	/^	CXTDMA_OFF = 0x0,$/;"	e	enum:btc_fbtc_tdma_type	file:
CXTD_AUTO	coex.c	/^	CXTD_AUTO,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_AUTO2	coex.c	/^	CXTD_AUTO2,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_FIX	coex.c	/^	CXTD_FIX,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_MAX	coex.c	/^	CXTD_MAX,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_OFF	coex.c	/^	CXTD_OFF = 0x0,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_OFF_B2	coex.c	/^	CXTD_OFF_B2,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_OFF_EXT	coex.c	/^	CXTD_OFF_EXT,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_PAUTO	coex.c	/^	CXTD_PAUTO,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_PAUTO2	coex.c	/^	CXTD_PAUTO2,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTD_PFIX	coex.c	/^	CXTD_PFIX,$/;"	e	enum:btc_fbtc_tdma_template	file:
CXTPS_MAX	coex.c	/^	CXTPS_MAX$/;"	e	enum:btc_fbtc_tdma_wlan_tx_pause	file:
CXTPS_OFF	coex.c	/^	CXTPS_OFF = 0x0,  \/* no wl tx pause*\/$/;"	e	enum:btc_fbtc_tdma_wlan_tx_pause	file:
CXTPS_ON	coex.c	/^	CXTPS_ON = 0x1,$/;"	e	enum:btc_fbtc_tdma_wlan_tx_pause	file:
CXT_BT	core.h	/^	CXT_BT = 0x0,$/;"	e	enum:__anon8
CXT_FLCTRL_MAX	core.h	/^	CXT_FLCTRL_MAX$/;"	e	enum:__anon9
CXT_FLCTRL_OFF	core.h	/^	CXT_FLCTRL_OFF = 0x0,$/;"	e	enum:__anon9
CXT_FLCTRL_ON	core.h	/^	CXT_FLCTRL_ON = 0x1,$/;"	e	enum:__anon9
CXT_MAX	core.h	/^	CXT_MAX$/;"	e	enum:__anon8
CXT_WL	core.h	/^	CXT_WL = 0x1,$/;"	e	enum:__anon8
DATA_RATE_HT_IDX_MASK	txrx.h	13;"	d
DATA_RATE_MODE_CTRL_MASK	txrx.h	10;"	d
DATA_RATE_MODE_HE	txrx.h	18;"	d
DATA_RATE_MODE_HT	txrx.h	14;"	d
DATA_RATE_MODE_NON_HT	txrx.h	12;"	d
DATA_RATE_MODE_VHT	txrx.h	17;"	d
DATA_RATE_NOT_HT_IDX_MASK	txrx.h	11;"	d
DATA_RATE_VHT_HE_IDX_MASK	txrx.h	16;"	d
DATA_RATE_VHT_HE_NSS_MASK	txrx.h	15;"	d
DECLARE_DIG_TABLE	rtw8852a_table.c	48631;"	d	file:
DECLARE_PHY_REG3_TBL	phy.h	202;"	d
DECLARE_RFK_TBL	rtw8852a_rfk_table.h	24;"	d
DECL_RFK_DELAY	rtw8852a_rfk_table.h	53;"	d
DECL_RFK_WC	rtw8852a_rfk_table.h	48;"	d
DECL_RFK_WM	rtw8852a_rfk_table.h	37;"	d
DECL_RFK_WRF	rtw8852a_rfk_table.h	30;"	d
DECL_RFK_WS	rtw8852a_rfk_table.h	43;"	d
DEFAULT_AX_RX_FLTR	reg.h	1294;"	d
DELTA_SWINGIDX_SIZE	phy.h	168;"	d
DIG_GAIN	phy.h	81;"	d
DIG_GAIN_SHIFT	phy.h	80;"	d
DLE_BOUND_UNIT	mac.h	381;"	d
DLE_CTRL_TYPE_NUM	mac.h	/^	DLE_CTRL_TYPE_NUM = 2,$/;"	e	enum:rtw89_mac_dle_ctrl_type
DLE_CTRL_TYPE_PLE	mac.h	/^	DLE_CTRL_TYPE_PLE = 1,$/;"	e	enum:rtw89_mac_dle_ctrl_type
DLE_CTRL_TYPE_WDE	mac.h	/^	DLE_CTRL_TYPE_WDE = 0,$/;"	e	enum:rtw89_mac_dle_ctrl_type
DLE_DFI_DUMP	debug.c	854;"	d	file:
DLE_DFI_DUMP	debug.c	950;"	d	file:
DLE_DFI_FREE_PAGE_DUMP	debug.c	881;"	d	file:
DLE_DFI_FREE_PAGE_DUMP	debug.c	951;"	d	file:
DLE_DFI_TYPE_FREEPG	mac.h	/^	DLE_DFI_TYPE_FREEPG	= 0,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_NXTPKTLLT	mac.h	/^	DLE_DFI_TYPE_NXTPKTLLT	= 5,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_PAGELLT	mac.h	/^	DLE_DFI_TYPE_PAGELLT	= 2,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_PKTINFO	mac.h	/^	DLE_DFI_TYPE_PKTINFO	= 3,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_PREPKTLLT	mac.h	/^	DLE_DFI_TYPE_PREPKTLLT	= 4,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_QEMPTY	mac.h	/^	DLE_DFI_TYPE_QEMPTY	= 7,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_QLNKTBL	mac.h	/^	DLE_DFI_TYPE_QLNKTBL	= 6,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_DFI_TYPE_QUOTA	mac.h	/^	DLE_DFI_TYPE_QUOTA	= 1,$/;"	e	enum:rtw89_mac_dle_dfi_type
DLE_WAIT_CNT	mac.h	382;"	d
DMAC_TBL_BASE_ADDR	mac.h	240;"	d
DPK_AGC_ADJ_LMT	rtw8852a_rfk.c	2415;"	d	file:
DPK_AGC_STEP_GAIN_ADJ	rtw8852a_rfk.c	/^	DPK_AGC_STEP_GAIN_ADJ,$/;"	e	enum:dpk_agc_step	file:
DPK_AGC_STEP_GAIN_LOSS_IDX	rtw8852a_rfk.c	/^	DPK_AGC_STEP_GAIN_LOSS_IDX,$/;"	e	enum:dpk_agc_step	file:
DPK_AGC_STEP_GL_GT_CRITERION	rtw8852a_rfk.c	/^	DPK_AGC_STEP_GL_GT_CRITERION,$/;"	e	enum:dpk_agc_step	file:
DPK_AGC_STEP_GL_LT_CRITERION	rtw8852a_rfk.c	/^	DPK_AGC_STEP_GL_LT_CRITERION,$/;"	e	enum:dpk_agc_step	file:
DPK_AGC_STEP_SET_TX_GAIN	rtw8852a_rfk.c	/^	DPK_AGC_STEP_SET_TX_GAIN,$/;"	e	enum:dpk_agc_step	file:
DPK_AGC_STEP_SYNC_DGAIN	rtw8852a_rfk.c	/^	DPK_AGC_STEP_SYNC_DGAIN,$/;"	e	enum:dpk_agc_step	file:
DPK_DGAIN_LOWER	rtw8852a_rfk.c	2417;"	d	file:
DPK_DGAIN_UPPER	rtw8852a_rfk.c	2416;"	d	file:
DPK_GL_CRIT	rtw8852a_rfk.c	2420;"	d	file:
DPK_RXBB_LOWER	rtw8852a_rfk.c	2419;"	d	file:
DPK_RXBB_UPPER	rtw8852a_rfk.c	2418;"	d	file:
DPK_SYNC_TH_CORR	rtw8852a_rfk.c	2238;"	d	file:
DPK_SYNC_TH_DC_I	rtw8852a_rfk.c	2236;"	d	file:
DPK_SYNC_TH_DC_Q	rtw8852a_rfk.c	2237;"	d	file:
DPK_TXAGC_INVAL	rtw8852a_rfk.c	2341;"	d	file:
DPK_TXAGC_LOWER	rtw8852a_rfk.c	2339;"	d	file:
DPK_TXAGC_UPPER	rtw8852a_rfk.c	2340;"	d	file:
ENV_MNTR_FAIL_DWORD	phy.h	67;"	d
ENV_MNTR_IFSCLM_HIS_MAX	phy.h	68;"	d
FA_TH_NUM	core.h	2504;"	d
FCXCYSTA_VER	core.h	1433;"	d
FCXDEF_STEP	coex.c	12;"	d	file:
FCXGPIODBG_VER	core.h	1373;"	d
FCXMAX_STEP	core.h	1273;"	d
FCXMREG_VER	core.h	1384;"	d
FCXNULLSTA_VER	core.h	1460;"	d
FCXONESLOT_VER	coex.c	55;"	d	file:
FCXSLOTS_VER	core.h	1408;"	d
FCXSTEP_VER	core.h	1417;"	d
FCXTDMA_VER	core.h	1566;"	d
FCX_BTAFH_VER	core.h	1488;"	d
FCX_BTDEVINFO_VER	core.h	1498;"	d
FCX_BTSCAN_VER	core.h	1480;"	d
FCX_BTVER_VER	core.h	1470;"	d
FC_EXEC	coex.h	29;"	d
FWCMD_SET_ADDR_ADDR_MASK	cam.h	28;"	d
FWCMD_SET_ADDR_AID12	cam.h	76;"	d
FWCMD_SET_ADDR_AID12_0	cam.h	78;"	d
FWCMD_SET_ADDR_AID12_1	cam.h	80;"	d
FWCMD_SET_ADDR_BB_SEL	cam.h	26;"	d
FWCMD_SET_ADDR_BCN_HIT_COND	cam.h	22;"	d
FWCMD_SET_ADDR_BSSID_BB_SEL	cam.h	130;"	d
FWCMD_SET_ADDR_BSSID_BSSID0	cam.h	134;"	d
FWCMD_SET_ADDR_BSSID_BSSID1	cam.h	136;"	d
FWCMD_SET_ADDR_BSSID_BSSID2	cam.h	138;"	d
FWCMD_SET_ADDR_BSSID_BSSID3	cam.h	140;"	d
FWCMD_SET_ADDR_BSSID_BSSID4	cam.h	142;"	d
FWCMD_SET_ADDR_BSSID_BSSID5	cam.h	144;"	d
FWCMD_SET_ADDR_BSSID_BSS_COLOR	cam.h	132;"	d
FWCMD_SET_ADDR_BSSID_CAM_IDX	cam.h	36;"	d
FWCMD_SET_ADDR_BSSID_IDX	cam.h	122;"	d
FWCMD_SET_ADDR_BSSID_LEN	cam.h	126;"	d
FWCMD_SET_ADDR_BSSID_OFFSET	cam.h	124;"	d
FWCMD_SET_ADDR_BSSID_VALID	cam.h	128;"	d
FWCMD_SET_ADDR_FRM_TGT_IND	cam.h	74;"	d
FWCMD_SET_ADDR_HIT_RULE	cam.h	24;"	d
FWCMD_SET_ADDR_IDX	cam.h	12;"	d
FWCMD_SET_ADDR_LEN	cam.h	16;"	d
FWCMD_SET_ADDR_LSIG_TXOP	cam.h	70;"	d
FWCMD_SET_ADDR_MACID	cam.h	62;"	d
FWCMD_SET_ADDR_MASK_SEL	cam.h	30;"	d
FWCMD_SET_ADDR_NET_TYPE	cam.h	20;"	d
FWCMD_SET_ADDR_OFFSET	cam.h	14;"	d
FWCMD_SET_ADDR_PORT_INT	cam.h	64;"	d
FWCMD_SET_ADDR_SEC_ENT0	cam.h	108;"	d
FWCMD_SET_ADDR_SEC_ENT0_KEYID	cam.h	92;"	d
FWCMD_SET_ADDR_SEC_ENT1	cam.h	110;"	d
FWCMD_SET_ADDR_SEC_ENT1_KEYID	cam.h	94;"	d
FWCMD_SET_ADDR_SEC_ENT2	cam.h	112;"	d
FWCMD_SET_ADDR_SEC_ENT2_KEYID	cam.h	96;"	d
FWCMD_SET_ADDR_SEC_ENT3	cam.h	114;"	d
FWCMD_SET_ADDR_SEC_ENT3_KEYID	cam.h	98;"	d
FWCMD_SET_ADDR_SEC_ENT4	cam.h	116;"	d
FWCMD_SET_ADDR_SEC_ENT4_KEYID	cam.h	100;"	d
FWCMD_SET_ADDR_SEC_ENT5	cam.h	118;"	d
FWCMD_SET_ADDR_SEC_ENT5_KEYID	cam.h	102;"	d
FWCMD_SET_ADDR_SEC_ENT6	cam.h	120;"	d
FWCMD_SET_ADDR_SEC_ENT6_KEYID	cam.h	104;"	d
FWCMD_SET_ADDR_SEC_ENT_MODE	cam.h	90;"	d
FWCMD_SET_ADDR_SEC_ENT_VALID	cam.h	106;"	d
FWCMD_SET_ADDR_SMA0	cam.h	38;"	d
FWCMD_SET_ADDR_SMA1	cam.h	40;"	d
FWCMD_SET_ADDR_SMA2	cam.h	42;"	d
FWCMD_SET_ADDR_SMA3	cam.h	44;"	d
FWCMD_SET_ADDR_SMA4	cam.h	46;"	d
FWCMD_SET_ADDR_SMA5	cam.h	48;"	d
FWCMD_SET_ADDR_SMA_HASH	cam.h	32;"	d
FWCMD_SET_ADDR_TF_TRS	cam.h	68;"	d
FWCMD_SET_ADDR_TGT_IND	cam.h	72;"	d
FWCMD_SET_ADDR_TMA0	cam.h	50;"	d
FWCMD_SET_ADDR_TMA1	cam.h	52;"	d
FWCMD_SET_ADDR_TMA2	cam.h	54;"	d
FWCMD_SET_ADDR_TMA3	cam.h	56;"	d
FWCMD_SET_ADDR_TMA4	cam.h	58;"	d
FWCMD_SET_ADDR_TMA5	cam.h	60;"	d
FWCMD_SET_ADDR_TMA_HASH	cam.h	34;"	d
FWCMD_SET_ADDR_TSF_SYNC	cam.h	66;"	d
FWCMD_SET_ADDR_VALID	cam.h	18;"	d
FWCMD_SET_ADDR_WAPI	cam.h	88;"	d
FWCMD_SET_ADDR_WOL_MAGIC	cam.h	86;"	d
FWCMD_SET_ADDR_WOL_PATTERN	cam.h	82;"	d
FWCMD_SET_ADDR_WOL_UC	cam.h	84;"	d
FWCMD_TYPE_H2C	fw.h	1271;"	d
FWDL_SECTION_CHKSUM_LEN	fw.h	127;"	d
FWDL_SECTION_MAX_NUM	fw.h	126;"	d
FWDL_SECTION_PER_PKT_LEN	fw.h	128;"	d
FWDL_WAIT_CNT	fw.c	47;"	d	file:
FW_EDCA_PARAM_AIFS_MSK	fw.h	252;"	d
FW_EDCA_PARAM_CWMAX_MSK	fw.h	250;"	d
FW_EDCA_PARAM_CWMIN_MSK	fw.h	251;"	d
FW_EDCA_PARAM_TXOPLMT_MSK	fw.h	249;"	d
FW_PROG_CNTR_DBG_SEL	mac.h	445;"	d
GAIN_CAL	rtw8852a_rfk.c	/^	GAIN_CAL	= 0x14,$/;"	e	enum:rtw8852a_dpk_id	file:
GAIN_LOSS	rtw8852a_rfk.c	/^	GAIN_LOSS	= 0x13,$/;"	e	enum:rtw8852a_dpk_id	file:
GET_DATA_RATE_HT_IDX	txrx.h	21;"	d
GET_DATA_RATE_MODE	txrx.h	19;"	d
GET_DATA_RATE_NOT_HT_IDX	txrx.h	20;"	d
GET_DATA_RATE_NSS	txrx.h	23;"	d
GET_DATA_RATE_VHT_HE_IDX	txrx.h	22;"	d
GET_FWSECTION_HDR_CHECKSUM	fw.h	256;"	d
GET_FWSECTION_HDR_DL_ADDR	fw.h	260;"	d
GET_FWSECTION_HDR_REDL	fw.h	258;"	d
GET_FWSECTION_HDR_SEC_SIZE	fw.h	254;"	d
GET_FW_HDR_CMD_VERSERION	fw.h	283;"	d
GET_FW_HDR_DATE	fw.h	273;"	d
GET_FW_HDR_HOUR	fw.h	275;"	d
GET_FW_HDR_MAJOR_VERSION	fw.h	263;"	d
GET_FW_HDR_MIN	fw.h	277;"	d
GET_FW_HDR_MINOR_VERSION	fw.h	265;"	d
GET_FW_HDR_MONTH	fw.h	271;"	d
GET_FW_HDR_SEC_NUM	fw.h	281;"	d
GET_FW_HDR_SUBINDEX	fw.h	269;"	d
GET_FW_HDR_SUBVERSION	fw.h	267;"	d
GET_FW_HDR_YEAR	fw.h	279;"	d
H2C_BA_CAM_LEN	fw.c	557;"	d	file:
H2C_CAM_LEN	fw.c	525;"	d	file:
H2C_CAT_MAC	fw.h	1273;"	d
H2C_CAT_OUTSRC	fw.h	1315;"	d
H2C_CL_BA_CAM	fw.h	1312;"	d
H2C_CL_FW_INFO	fw.h	1276;"	d
H2C_CL_MAC_ADDR_CAM_UPDATE	fw.h	1293;"	d
H2C_CL_MAC_FR_EXCHG	fw.h	1289;"	d
H2C_CL_MAC_FWDL	fw.h	1285;"	d
H2C_CL_MAC_FW_OFLD	fw.h	1302;"	d
H2C_CL_MAC_MEDIA_RPT	fw.h	1297;"	d
H2C_CL_MAC_PS	fw.h	1281;"	d
H2C_CL_MAC_SEC_CAM	fw.h	1308;"	d
H2C_CL_OUTSRC_RA	fw.h	1317;"	d
H2C_CL_OUTSRC_RF_REG_A	fw.h	1320;"	d
H2C_CL_OUTSRC_RF_REG_B	fw.h	1321;"	d
H2C_CMC_TBL_LEN	fw.c	717;"	d	file:
H2C_EDCA_LEN	fw.c	1025;"	d	file:
H2C_FUNC_LOG_CFG	fw.h	1277;"	d
H2C_FUNC_MAC_ADDR_CAM_UPD	fw.h	1294;"	d
H2C_FUNC_MAC_BA_CAM	fw.h	1313;"	d
H2C_FUNC_MAC_CCTLINFO_UD	fw.h	1290;"	d
H2C_FUNC_MAC_FWHDR_DL	fw.h	1286;"	d
H2C_FUNC_MAC_FWROLE_MAINTAIN	fw.h	1299;"	d
H2C_FUNC_MAC_GENERAL_PKT	fw.h	1278;"	d
H2C_FUNC_MAC_JOININFO	fw.h	1298;"	d
H2C_FUNC_MAC_LPS_PARM	fw.h	1282;"	d
H2C_FUNC_MAC_MACID_PAUSE	fw.h	1303;"	d
H2C_FUNC_MAC_SEC_UPD	fw.h	1309;"	d
H2C_FUNC_OFLD_CFG	fw.h	1305;"	d
H2C_FUNC_OUTSRC_RA_MACIDCFG	fw.h	1318;"	d
H2C_FUNC_USR_EDCA	fw.h	1304;"	d
H2C_GENERAL_PKT_ID_UND	fw.c	639;"	d	file:
H2C_GENERAL_PKT_LEN	fw.c	638;"	d	file:
H2C_HDR_CAT	fw.h	1262;"	d
H2C_HDR_CLASS	fw.h	1263;"	d
H2C_HDR_DEL_TYPE	fw.h	1265;"	d
H2C_HDR_DONE_ACK	fw.h	1269;"	d
H2C_HDR_FUNC	fw.h	1264;"	d
H2C_HDR_H2C_SEQ	fw.h	1266;"	d
H2C_HDR_REC_ACK	fw.h	1268;"	d
H2C_HDR_TOTAL_LEN	fw.h	1267;"	d
H2C_HEADER_LEN	fw.h	1261;"	d
H2C_JOIN_INFO_LEN	fw.c	948;"	d	file:
H2C_LEN_CXDRVHDR	fw.c	1155;"	d	file:
H2C_LEN_CXDRVINFO_CTRL	fw.c	1286;"	d	file:
H2C_LEN_CXDRVINFO_INIT	fw.c	1156;"	d	file:
H2C_LEN_CXDRVINFO_RFK	fw.c	1327;"	d	file:
H2C_LEN_CXDRVINFO_ROLE	fw.c	1214;"	d	file:
H2C_LOG_CFG_LEN	fw.c	601;"	d	file:
H2C_LPS_PARM_LEN	fw.c	675;"	d	file:
H2C_OFLD_CFG_LEN	fw.c	1060;"	d	file:
H2C_RA_LEN	fw.c	1090;"	d	file:
H2C_SEC_CAM_LEN	fw.h	1259;"	d
H2C_VIF_MAINTAIN_LEN	fw.c	913;"	d	file:
HFC_PAGE_UNIT	mac.h	13;"	d
HTC_OM_CHANNEL_WIDTH_160_OR_80_80	core.h	/^	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,$/;"	e	enum:htc_om_channel_width
HTC_OM_CHANNEL_WIDTH_20	core.h	/^	HTC_OM_CHANNEL_WIDTH_20 = 0,$/;"	e	enum:htc_om_channel_width
HTC_OM_CHANNEL_WIDTH_40	core.h	/^	HTC_OM_CHANNEL_WIDTH_40 = 1,$/;"	e	enum:htc_om_channel_width
HTC_OM_CHANNEL_WIDTH_80	core.h	/^	HTC_OM_CHANNEL_WIDTH_80 = 2,$/;"	e	enum:htc_om_channel_width
IB_PBK_BASE	phy.c	2586;"	d	file:
ID_FLOK_COARSE	rtw8852a_rfk.c	/^	ID_FLOK_COARSE,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_FLOK_FINE	rtw8852a_rfk.c	/^	ID_FLOK_FINE,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_NBRXK	rtw8852a_rfk.c	/^	ID_NBRXK,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_NBTXK	rtw8852a_rfk.c	/^	ID_NBTXK,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_RXAGC	rtw8852a_rfk.c	/^	ID_RXAGC,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_RXK	rtw8852a_rfk.c	/^	ID_RXK,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_TXAGC	rtw8852a_rfk.c	/^	ID_TXAGC,$/;"	e	enum:rtw8852a_iqk_type	file:
ID_TXK	rtw8852a_rfk.c	/^	ID_TXK,$/;"	e	enum:rtw8852a_iqk_type	file:
IFS_CLM_TH0_UPPER	phy.h	71;"	d
IFS_CLM_TH_MUL	phy.h	72;"	d
IFS_CLM_TH_START_IDX	phy.h	73;"	d
IGI_OFFSET_MAX	phy.c	2619;"	d	file:
IGI_OFFSET_MUL	phy.c	2620;"	d	file:
IGI_RSSI_MIN	phy.c	2773;"	d	file:
IGI_RSSI_TH_NUM	core.h	2503;"	d
INTF_INTGRA_HOSTREF_V1	pci.h	346;"	d
INTF_INTGRA_MINREF_V1	pci.h	345;"	d
INVALID_QT_WCPU	mac.c	1292;"	d	file:
INV_RF_DATA	core.h	29;"	d
IS_TSSI_EXTRA_GROUP	rtw8852a_rfk.c	3236;"	d	file:
LBK_RXIQK	rtw8852a_rfk.c	/^	LBK_RXIQK	= 0x06,$/;"	e	enum:rtw8852a_dpk_id	file:
LNA0_GAIN	phy.h	77;"	d
LNA_GAIN_NUM	core.h	2505;"	d
LNA_IDX_MAX	phy.h	83;"	d
LNA_IDX_MIN	phy.h	84;"	d
MAC_AX_BT_MODE_0_3	reg.h	57;"	d
MAC_AX_BT_MODE_2	reg.h	58;"	d
MAC_AX_CSR_DELAY	reg.h	1444;"	d
MAC_AX_CSR_PRI_TO	reg.h	1448;"	d
MAC_AX_CSR_RATE	reg.h	1438;"	d
MAC_AX_CSR_TRX_TO	reg.h	1446;"	d
MAC_AX_DFLT_TX_TIME	mac.c	3712;"	d	file:
MAC_AX_DUMP_SHAREBUFF_INDICATOR	mac.h	/^	MAC_AX_DUMP_SHAREBUFF_INDICATOR = 0x80000000,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_CPU_EXCEPTION	mac.h	/^	MAC_AX_ERR_CPU_EXCEPTION = 0x3000,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_CFG_DIS_NOTIFY	mac.h	/^	MAC_AX_ERR_L0_CFG_DIS_NOTIFY = 0x0011,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_CFG_HANDSHAKE	mac.h	/^	MAC_AX_ERR_L0_CFG_HANDSHAKE = 0x0012,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_CFG_NOTIFY	mac.h	/^	MAC_AX_ERR_L0_CFG_NOTIFY = 0x0010,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_ERR_CMAC0	mac.h	/^	MAC_AX_ERR_L0_ERR_CMAC0 = 0x0001,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_ERR_CMAC1	mac.h	/^	MAC_AX_ERR_L0_ERR_CMAC1 = 0x0002,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_PROMOTE_TO_L1	mac.h	/^	MAC_AX_ERR_L0_PROMOTE_TO_L1 = 0x0010,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_RCVY_EN	mac.h	/^	MAC_AX_ERR_L0_RCVY_EN = 0x0013,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L0_RESET_DONE	mac.h	/^	MAC_AX_ERR_L0_RESET_DONE = 0x0003,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_DISABLE_EN	mac.h	/^	MAC_AX_ERR_L1_DISABLE_EN = 0x0001,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_ERR_DMAC	mac.h	/^	MAC_AX_ERR_L1_ERR_DMAC = 0x1000,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_PROMOTE_TO_L2	mac.h	/^	MAC_AX_ERR_L1_PROMOTE_TO_L2 = 0x1010,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RCVY_EN	mac.h	/^	MAC_AX_ERR_L1_RCVY_EN = 0x0002,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RCVY_START_REQ	mac.h	/^	MAC_AX_ERR_L1_RCVY_START_REQ = 0x0004,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RCVY_STOP_DONE	mac.h	/^	MAC_AX_ERR_L1_RCVY_STOP_DONE = 0x1011,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RCVY_STOP_REQ	mac.h	/^	MAC_AX_ERR_L1_RCVY_STOP_REQ = 0x0003,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE	mac.h	/^	MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE = 0x1001,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L1_RESET_RECOVERY_DONE	mac.h	/^	MAC_AX_ERR_L1_RESET_RECOVERY_DONE = 0x1002,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_DMA	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_DMA = 0x2100,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_HCI	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_HCI = 0x2110,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_HIOE = 0x2140,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_IDDMA = 0x2130,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_IPSEC = 0x2150,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_OTHERS = 0x2170,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_RLX4081 = 0x2120,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AHB_TO_RX4281	mac.h	/^	MAC_AX_ERR_L2_ERR_AHB_TO_RX4281 = 0x2160,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_DMA	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_DMA = 0x2000,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_HCI	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_HCI = 0x2010,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_HIOE = 0x2040,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_IDDMA = 0x2030,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_IPSEC = 0x2050,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_OTHERS = 0x2070,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_RLX4081	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_RLX4081 = 0x2020,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_AH_RX4281	mac.h	/^	MAC_AX_ERR_L2_ERR_AH_RX4281 = 0x2060,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_DMA = 0x2300,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HCI = 0x2310,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_HIOE = 0x2340,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IDDMA = 0x2330,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_IPSEC = 0x2350,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_OTHERS = 0x2370,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RLX4081 = 0x2320,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_BBRF_TO_RX4281 = 0x2360,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_AXIDMA = 0x2203,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_CPULOCAL = 0x2202,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_HIOE = 0x2204,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IDDMA = 0x2205,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_IPSEC = 0x2206,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_OTHERS = 0x220A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_UART = 0x2201,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WCMAC = 0x2209,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WDMAC = 0x2208,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WON = 0x2207,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_DMA_WVA = 0x2200,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_AXIDMA = 0x2213,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_CPULOCAL = 0x2212,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_HIOE = 0x2214,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IDDMA = 0x2215,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_IPSEC = 0x2216,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_OTHERS = 0x221A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_UART = 0x2211,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WCMAC = 0x2219,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WDMAC = 0x2218,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HCI_WVA = 0x2210,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_AXIDMA = 0x2243,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_CPULOCAL = 0x2242,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_HIOE = 0x2244,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IDDMA = 0x2245,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_IPSEC = 0x2246,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_OTHERS = 0x224A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_UART = 0x2241,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WCMAC = 0x2249,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WDMAC = 0x2248,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WON = 0x2247,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_HIOE_WVA = 0x2240,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_AXIDMA = 0x2233,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_CPULOCAL = 0x2232,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_HIOE = 0x2234,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IDDMA = 0x2235,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_IPSEC = 0x2236,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_OTHERS = 0x223A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_UART = 0x2231,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WCMAC = 0x2239,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WDMAC = 0x2238,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WON = 0x2237,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IDDMA_WVA = 0x2230,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_AXIDMA = 0x2253,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_CPULOCAL = 0x2252,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_HIOE = 0x2254,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IDDMA = 0x2255,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_IPSEC = 0x2256,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_OTHERS = 0x225A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_UART = 0x2251,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WCMAC = 0x2259,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WDMAC = 0x2258,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WON = 0x2257,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_IPSEC_WVA = 0x2250,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_AXIDMA = 0x2273,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_CPULOCAL = 0x2272,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_HIOE = 0x2274,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IDDMA = 0x2275,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_IPSEC = 0x2276,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_OTHERS = 0x227A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_UART = 0x2271,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WCMAC = 0x2279,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WDMAC = 0x2278,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WON = 0x2277,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_OTHERS_WVA = 0x2270,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_AXIDMA = 0x2223,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_CPULOCAL = 0x2222,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_HIOE = 0x2224,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IDDMA = 0x2225,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_IPSEC = 0x2226,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_OTHERS = 0x222A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_UART = 0x2221,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WCMAC = 0x2229,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WDMAC = 0x2228,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WON = 0x2227,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RLX4081_WVA = 0x2220,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_AXIDMA = 0x2263,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_CPULOCAL = 0x2262,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_HIOE = 0x2264,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IDDMA = 0x2265,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_IPSEC = 0x2266,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_OTHERS = 0x226A,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_UART = 0x2261,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WCMAC = 0x2269,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WDMAC = 0x2268,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WON = 0x2267,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA	mac.h	/^	MAC_AX_ERR_L2_ERR_APB_SA_TO_RX4281_WVA = 0x2260,$/;"	e	enum:mac_ax_err_info
MAC_AX_ERR_L2_RESET_DONE	mac.h	/^	MAC_AX_ERR_L2_RESET_DONE = 0x2400,$/;"	e	enum:mac_ax_err_info
MAC_AX_FUNC_DIS	pci.h	/^	MAC_AX_FUNC_DIS,$/;"	e	enum:mac_ax_func_sw
MAC_AX_FUNC_EN	pci.h	/^	MAC_AX_FUNC_EN,$/;"	e	enum:mac_ax_func_sw
MAC_AX_GET_ERR_MAX	mac.h	/^	MAC_AX_GET_ERR_MAX,$/;"	e	enum:mac_ax_err_info
MAC_AX_L0_TO_L1_CHIF_IDLE	mac.h	/^	MAC_AX_L0_TO_L1_CHIF_IDLE = 0,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_CMAC_DMA_IDLE	mac.h	/^	MAC_AX_L0_TO_L1_CMAC_DMA_IDLE = 1,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_DLE_STAT_HANG	mac.h	/^	MAC_AX_L0_TO_L1_DLE_STAT_HANG = 5,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_EVENT_MAX	mac.h	/^	MAC_AX_L0_TO_L1_EVENT_MAX = 15,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_PCIE_STUCK	mac.h	/^	MAC_AX_L0_TO_L1_PCIE_STUCK = 6,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_PTCL_IDLE	mac.h	/^	MAC_AX_L0_TO_L1_PTCL_IDLE = 3,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_RLS_PKID	mac.h	/^	MAC_AX_L0_TO_L1_RLS_PKID = 2,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_L0_TO_L1_RX_QTA_LOST	mac.h	/^	MAC_AX_L0_TO_L1_RX_QTA_LOST = 4,$/;"	e	enum:rtw89_mac_ax_l0_to_l1_event
MAC_AX_LEN_TH_DEF	mac.c	3228;"	d	file:
MAC_AX_LEN_TH_MAX	mac.c	3226;"	d	file:
MAC_AX_LEN_TH_SH	mac.c	3224;"	d	file:
MAC_AX_NOTIFY_PWR_MAJOR	reg.h	87;"	d
MAC_AX_NOTIFY_TP_MAJOR	reg.h	86;"	d
MAC_AX_RTK_RATE	reg.h	1477;"	d
MAC_AX_SET_ERR_MAX	mac.h	/^	MAC_AX_SET_ERR_MAX,$/;"	e	enum:mac_ax_err_info
MAC_AX_TIME_TH_DEF	mac.c	3227;"	d	file:
MAC_AX_TIME_TH_MAX	mac.c	3225;"	d	file:
MAC_AX_TIME_TH_SH	mac.c	3223;"	d	file:
MAC_DBG_SEL	mac.h	453;"	d
MAC_MEM_DUMP_PAGE_SIZE	mac.h	10;"	d
MAC_REG_POOL_COUNT	mac.h	372;"	d
MASKBYTE0	core.h	20;"	d
MASKBYTE1	core.h	21;"	d
MASKBYTE2	core.h	22;"	d
MASKBYTE3	core.h	23;"	d
MASKBYTE4	core.h	24;"	d
MASKDWORD	core.h	27;"	d
MASKHWORD	core.h	25;"	d
MASKLWORD	core.h	26;"	d
MAX_CFO_TOLERANCE	phy.h	62;"	d
MAX_RSSI	core.h	33;"	d
MDIO_PG0_G1	pci.h	10;"	d
MDIO_PG0_G2	pci.h	12;"	d
MDIO_PG1_G1	pci.h	11;"	d
MDIO_PG1_G2	pci.h	13;"	d
MDPK_IDL	rtw8852a_rfk.c	/^	MDPK_IDL	= 0x11,$/;"	e	enum:rtw8852a_dpk_id	file:
MDPK_MPA	rtw8852a_rfk.c	/^	MDPK_MPA	= 0x12,$/;"	e	enum:rtw8852a_dpk_id	file:
MLME_LINKED	coex.c	/^	MLME_LINKED,$/;"	e	enum:btc_mlme_state	file:
MLME_LINKING	coex.c	/^	MLME_LINKING,$/;"	e	enum:btc_mlme_state	file:
MLME_NO_LINK	coex.c	/^	MLME_NO_LINK,$/;"	e	enum:btc_mlme_state	file:
MS_TO_4US_RATIO	phy.h	66;"	d
NDP_RX_STANDBY_TIMER	reg.h	1209;"	d
NM_EXEC	coex.h	28;"	d
NONE_TEST	rtw8852a.h	/^	NONE_TEST,$/;"	e	enum:rtw8852a_pmac_mode
NTX_NUM_8852A	rtw8852a.h	11;"	d
NUM_OF_RTW89_FLAGS	core.h	/^	NUM_OF_RTW89_FLAGS,$/;"	e	enum:rtw89_flags
PACKET_ARP	coex.h	/^	PACKET_ARP,$/;"	e	enum:btc_pkt_type
PACKET_DHCP	coex.h	/^	PACKET_DHCP,$/;"	e	enum:btc_pkt_type
PACKET_EAPOL	coex.h	/^	PACKET_EAPOL,$/;"	e	enum:btc_pkt_type
PACKET_EAPOL_END	coex.h	/^	PACKET_EAPOL_END,$/;"	e	enum:btc_pkt_type
PACKET_ICMP	coex.h	/^	PACKET_ICMP,$/;"	e	enum:btc_pkt_type
PACKET_MAX	coex.h	/^	PACKET_MAX$/;"	e	enum:btc_pkt_type
PCIE_CLKDLY_HW_0	pci.h	/^	PCIE_CLKDLY_HW_0 = 0,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CLKDLY_HW_100US	pci.h	/^	PCIE_CLKDLY_HW_100US = 0x3,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CLKDLY_HW_150US	pci.h	/^	PCIE_CLKDLY_HW_150US = 0x4,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CLKDLY_HW_200US	pci.h	/^	PCIE_CLKDLY_HW_200US = 0x5,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CLKDLY_HW_30US	pci.h	/^	PCIE_CLKDLY_HW_30US = 0x1,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CLKDLY_HW_50US	pci.h	/^	PCIE_CLKDLY_HW_50US = 0x2,$/;"	e	enum:rtw89_pcie_clkdly_hw
PCIE_CVT_DBG_SEL	mac.h	448;"	d
PCIE_CXPL_DBG_SEL	mac.h	449;"	d
PCIE_IO_DBG_SEL	mac.h	450;"	d
PCIE_L0SDLY_1US	pci.h	/^	PCIE_L0SDLY_1US = 0,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_2US	pci.h	/^	PCIE_L0SDLY_2US = 1,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_3US	pci.h	/^	PCIE_L0SDLY_3US = 2,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_4US	pci.h	/^	PCIE_L0SDLY_4US = 3,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_5US	pci.h	/^	PCIE_L0SDLY_5US = 4,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_6US	pci.h	/^	PCIE_L0SDLY_6US = 5,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L0SDLY_7US	pci.h	/^	PCIE_L0SDLY_7US = 6,$/;"	e	enum:rtw89_pcie_l0sdly
PCIE_L1DLY_16US	pci.h	/^	PCIE_L1DLY_16US = 4,$/;"	e	enum:rtw89_pcie_l1dly
PCIE_L1DLY_32US	pci.h	/^	PCIE_L1DLY_32US = 5,$/;"	e	enum:rtw89_pcie_l1dly
PCIE_L1DLY_64US	pci.h	/^	PCIE_L1DLY_64US = 6,$/;"	e	enum:rtw89_pcie_l1dly
PCIE_L1DLY_HW_INFI	pci.h	/^	PCIE_L1DLY_HW_INFI = 7,$/;"	e	enum:rtw89_pcie_l1dly
PCIE_MISC2_DBG_SEL	mac.h	452;"	d
PCIE_MISC_DBG_SEL	mac.h	451;"	d
PCIE_PHY_GEN1	pci.h	/^	PCIE_PHY_GEN1,$/;"	e	enum:rtw89_pcie_phy
PCIE_PHY_GEN1_UNDEFINE	pci.h	/^	PCIE_PHY_GEN1_UNDEFINE = 0x7F,$/;"	e	enum:rtw89_pcie_phy
PCIE_PHY_GEN2	pci.h	/^	PCIE_PHY_GEN2,$/;"	e	enum:rtw89_pcie_phy
PCIE_RXDMA_DBG_SEL	mac.h	447;"	d
PCIE_TXDMA_DBG_SEL	mac.h	446;"	d
PCI_LTR_IDLE_TIMER_100US	reg.h	225;"	d
PCI_LTR_IDLE_TIMER_10US	reg.h	224;"	d
PCI_LTR_IDLE_TIMER_1US	reg.h	223;"	d
PCI_LTR_IDLE_TIMER_1_6MS	reg.h	229;"	d
PCI_LTR_IDLE_TIMER_200US	reg.h	226;"	d
PCI_LTR_IDLE_TIMER_3_2MS	reg.h	230;"	d
PCI_LTR_IDLE_TIMER_400US	reg.h	227;"	d
PCI_LTR_IDLE_TIMER_800US	reg.h	228;"	d
PCI_LTR_IDLE_TIMER_DEF	reg.h	232;"	d
PCI_LTR_IDLE_TIMER_IGNORE	reg.h	233;"	d
PCI_LTR_IDLE_TIMER_R_ERR	reg.h	231;"	d
PCI_LTR_SPC_100US	reg.h	236;"	d
PCI_LTR_SPC_10US	reg.h	235;"	d
PCI_LTR_SPC_1MS	reg.h	238;"	d
PCI_LTR_SPC_500US	reg.h	237;"	d
PCI_LTR_SPC_DEF	reg.h	240;"	d
PCI_LTR_SPC_IGNORE	reg.h	241;"	d
PCI_LTR_SPC_R_ERR	reg.h	239;"	d
PD_TH_BW20_CMP_VAL	phy.h	94;"	d
PD_TH_BW40_CMP_VAL	phy.h	93;"	d
PD_TH_BW80_CMP_VAL	phy.h	92;"	d
PD_TH_CMP_VAL	phy.h	95;"	d
PD_TH_MAX_RSSI	phy.h	90;"	d
PD_TH_MIN_RSSI	phy.h	91;"	d
PD_TH_SB_FLTR_CMP_VAL	phy.h	96;"	d
PERCENT	phy.h	70;"	d
PERMIL	phy.h	69;"	d
PHYREG_SET_ALL_CYCLE	reg.h	166;"	d
PHYSTS_CTRL	phy.h	99;"	d
PHYSTS_DATA	phy.h	100;"	d
PHYSTS_MGNT	phy.h	98;"	d
PHYSTS_RSVD	phy.h	101;"	d
PHY_COND_BRANCH_ELIF	phy.h	24;"	d
PHY_COND_BRANCH_ELSE	phy.h	25;"	d
PHY_COND_BRANCH_END	phy.h	26;"	d
PHY_COND_BRANCH_IF	phy.h	23;"	d
PHY_COND_CHECK	phy.h	27;"	d
PHY_COND_DONT_CARE	phy.h	28;"	d
PHY_HEADLINE_VALID	phy.h	13;"	d
PHY_STS_HDR_LEN	core.h	466;"	d
PKTS_RX	rtw8852a.h	/^	PKTS_RX,$/;"	e	enum:rtw8852a_pmac_mode
PKTS_TX	rtw8852a.h	/^	PKTS_TX,$/;"	e	enum:rtw8852a_pmac_mode
PLD_RLS_MAX_PG	mac.c	1805;"	d	file:
PLE_DLE_PORT_ID_CMAC0	mac.h	/^	PLE_DLE_PORT_ID_CMAC0 = 3,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_CMAC1	mac.h	/^	PLE_DLE_PORT_ID_CMAC1 = 4,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_CPU_IO	mac.h	/^	PLE_DLE_PORT_ID_CPU_IO = 6,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_DISPATCH	mac.h	/^	PLE_DLE_PORT_ID_DISPATCH = 0,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_END	mac.h	/^	PLE_DLE_PORT_ID_END = 8$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_MPDU	mac.h	/^	PLE_DLE_PORT_ID_MPDU = 1,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_PLRLS	mac.h	/^	PLE_DLE_PORT_ID_PLRLS = 7,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_SEC	mac.h	/^	PLE_DLE_PORT_ID_SEC = 2,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_PORT_ID_WDRLS	mac.h	/^	PLE_DLE_PORT_ID_WDRLS = 5,$/;"	e	enum:rtw89_mac_ple_dle_port_id
PLE_DLE_QUEID_NO_REPORT	mac.h	/^	PLE_DLE_QUEID_NO_REPORT = 0x0$/;"	e	enum:rtw89_mac_ple_dle_queid_plrls
PLE_MGN_INI_RDY	reg.h	451;"	d
PLE_QTAID_B0_TXPL	mac.h	/^	PLE_QTAID_B0_TXPL = 0,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_B1_TXPL	mac.h	/^	PLE_QTAID_B1_TXPL = 1,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_C2H	mac.h	/^	PLE_QTAID_C2H = 2,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_CMAC0_RX	mac.h	/^	PLE_QTAID_CMAC0_RX = 6,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_CMAC1_BBRPT	mac.h	/^	PLE_QTAID_CMAC1_BBRPT = 8,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_CMAC1_RX	mac.h	/^	PLE_QTAID_CMAC1_RX = 7,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_CPUIO	mac.h	/^	PLE_QTAID_CPUIO = 10,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_H2C	mac.h	/^	PLE_QTAID_H2C = 3,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_MPDU	mac.h	/^	PLE_QTAID_MPDU = 5,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_WDRLS	mac.h	/^	PLE_QTAID_WDRLS = 9,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PLE_QTAID_WLAN_CPU	mac.h	/^	PLE_QTAID_WLAN_CPU = 4,$/;"	e	enum:rtw89_mac_dle_ple_quota_id
PPDU_FILTER_BITMAP	phy.h	102;"	d
PS_CPWM_RSP_SEQ_NUM	reg.h	118;"	d
PS_CPWM_SEQ_NUM	reg.h	117;"	d
PS_CPWM_STATE	reg.h	119;"	d
PS_RPWM_ACK	reg.h	113;"	d
PS_RPWM_SEQ_NUM	reg.h	114;"	d
PS_RPWM_STATE	reg.h	115;"	d
PS_RPWM_TOGGLE	reg.h	112;"	d
PTCL_IDLE_POLL_CNT	mac.h	377;"	d
PWR_ACT	mac.c	1004;"	d	file:
PWR_ACT	mac.c	1040;"	d	file:
PWR_BASE_MAC	mac.h	413;"	d
PWR_BASE_PCIE	mac.h	415;"	d
PWR_BASE_SDIO	mac.h	416;"	d
PWR_BASE_USB	mac.h	414;"	d
PWR_CMD_DELAY	mac.h	405;"	d
PWR_CMD_END	mac.h	406;"	d
PWR_CMD_POLL	mac.h	404;"	d
PWR_CMD_WRITE	mac.h	403;"	d
PWR_CV_MSK_A	mac.h	418;"	d
PWR_CV_MSK_ALL	mac.h	426;"	d
PWR_CV_MSK_B	mac.h	419;"	d
PWR_CV_MSK_C	mac.h	420;"	d
PWR_CV_MSK_D	mac.h	421;"	d
PWR_CV_MSK_E	mac.h	422;"	d
PWR_CV_MSK_F	mac.h	423;"	d
PWR_CV_MSK_G	mac.h	424;"	d
PWR_CV_MSK_TEST	mac.h	425;"	d
PWR_DELAY_MS	mac.h	429;"	d
PWR_DELAY_US	mac.h	428;"	d
PWR_INTF_MSK_ALL	mac.h	411;"	d
PWR_INTF_MSK_PCIE	mac.h	410;"	d
PWR_INTF_MSK_SDIO	mac.h	408;"	d
PWR_INTF_MSK_USB	mac.h	409;"	d
PWR_POLL_CNT	mac.c	815;"	d	file:
QLNKTBL_ADDR_INFO_SEL	mac.h	484;"	d
QLNKTBL_ADDR_INFO_SEL_0	mac.h	485;"	d
QLNKTBL_ADDR_INFO_SEL_1	mac.h	486;"	d
QLNKTBL_ADDR_TBL_IDX_MASK	mac.h	487;"	d
QLNKTBL_DATA_SEL1_PKT_CNT_MASK	mac.h	488;"	d
RAC_ANA10	pci.h	14;"	d
RAC_ANA19	pci.h	15;"	d
RAC_ANA1F	pci.h	16;"	d
RAC_ANA24	pci.h	17;"	d
RAC_ANA26	pci.h	19;"	d
RAC_CTRL_PPR_V1	pci.h	21;"	d
RAC_SET_PPR_V1	pci.h	25;"	d
RA_FLOOR_TABLE_SIZE	phy.c	97;"	d	file:
RA_FLOOR_UP_GAP	phy.c	98;"	d	file:
RA_MASK_CCK_RATES	phy.h	30;"	d
RA_MASK_HE_1SS_RATES	phy.h	44;"	d
RA_MASK_HE_2SS_RATES	phy.h	45;"	d
RA_MASK_HE_3SS_RATES	phy.h	46;"	d
RA_MASK_HE_4SS_RATES	phy.h	47;"	d
RA_MASK_HE_RATES	phy.h	48;"	d
RA_MASK_HT_1SS_RATES	phy.h	34;"	d
RA_MASK_HT_2SS_RATES	phy.h	35;"	d
RA_MASK_HT_3SS_RATES	phy.h	36;"	d
RA_MASK_HT_4SS_RATES	phy.h	37;"	d
RA_MASK_HT_RATES	phy.h	38;"	d
RA_MASK_OFDM_RATES	phy.h	31;"	d
RA_MASK_SUBCCK_RATES	phy.h	32;"	d
RA_MASK_SUBOFDM_RATES	phy.h	33;"	d
RA_MASK_VHT_1SS_RATES	phy.h	39;"	d
RA_MASK_VHT_2SS_RATES	phy.h	40;"	d
RA_MASK_VHT_3SS_RATES	phy.h	41;"	d
RA_MASK_VHT_4SS_RATES	phy.h	42;"	d
RA_MASK_VHT_RATES	phy.h	43;"	d
REG_BB	core.h	/^	REG_BB = 0x1,$/;"	e	enum:rtw_btc_btf_reg_type
REG_BT_BLUEWIZE	core.h	/^	REG_BT_BLUEWIZE = 0x5,$/;"	e	enum:rtw_btc_btf_reg_type
REG_BT_LE	core.h	/^	REG_BT_LE = 0x7,$/;"	e	enum:rtw_btc_btf_reg_type
REG_BT_MODEM	core.h	/^	REG_BT_MODEM = 0x4,$/;"	e	enum:rtw_btc_btf_reg_type
REG_BT_RF	core.h	/^	REG_BT_RF = 0x3,$/;"	e	enum:rtw_btc_btf_reg_type
REG_BT_VENDOR	core.h	/^	REG_BT_VENDOR = 0x6,$/;"	e	enum:rtw_btc_btf_reg_type
REG_MAC	core.h	/^	REG_MAC = 0x0,$/;"	e	enum:rtw_btc_btf_reg_type
REG_MAX_TYPE	core.h	/^	REG_MAX_TYPE,$/;"	e	enum:rtw_btc_btf_reg_type
REG_RF	core.h	/^	REG_RF = 0x2,$/;"	e	enum:rtw_btc_btf_reg_type
RFREG_MASK	core.h	28;"	d
RF_A	core.h	/^	RF_A	= BIT(0),$/;"	e	enum:rtw89_rf_path_bit
RF_AB	core.h	/^	RF_AB	= (RF_A | RF_B),$/;"	e	enum:rtw89_rf_path_bit
RF_ABC	core.h	/^	RF_ABC	= (RF_A | RF_B | RF_C),$/;"	e	enum:rtw89_rf_path_bit
RF_ABCD	core.h	/^	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_ABD	core.h	/^	RF_ABD	= (RF_A | RF_B | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_AC	core.h	/^	RF_AC	= (RF_A | RF_C),$/;"	e	enum:rtw89_rf_path_bit
RF_ACD	core.h	/^	RF_ACD	= (RF_A | RF_C | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_AD	core.h	/^	RF_AD	= (RF_A | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_B	core.h	/^	RF_B	= BIT(1),$/;"	e	enum:rtw89_rf_path_bit
RF_BC	core.h	/^	RF_BC	= (RF_B | RF_C),$/;"	e	enum:rtw89_rf_path_bit
RF_BCD	core.h	/^	RF_BCD	= (RF_B | RF_C | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_BD	core.h	/^	RF_BD	= (RF_B | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_C	core.h	/^	RF_C	= BIT(2),$/;"	e	enum:rtw89_rf_path_bit
RF_CD	core.h	/^	RF_CD	= (RF_C | RF_D),$/;"	e	enum:rtw89_rf_path_bit
RF_D	core.h	/^	RF_D	= BIT(3),$/;"	e	enum:rtw89_rf_path_bit
RF_PATH_A	core.h	/^	RF_PATH_A = 0,$/;"	e	enum:rtw89_rf_path
RF_PATH_AB	core.h	/^	RF_PATH_AB,$/;"	e	enum:rtw89_rf_path
RF_PATH_ABC	core.h	/^	RF_PATH_ABC,$/;"	e	enum:rtw89_rf_path
RF_PATH_ABCD	core.h	/^	RF_PATH_ABCD,$/;"	e	enum:rtw89_rf_path
RF_PATH_ABD	core.h	/^	RF_PATH_ABD,$/;"	e	enum:rtw89_rf_path
RF_PATH_AC	core.h	/^	RF_PATH_AC,$/;"	e	enum:rtw89_rf_path
RF_PATH_ACD	core.h	/^	RF_PATH_ACD,$/;"	e	enum:rtw89_rf_path
RF_PATH_AD	core.h	/^	RF_PATH_AD,$/;"	e	enum:rtw89_rf_path
RF_PATH_B	core.h	/^	RF_PATH_B = 1,$/;"	e	enum:rtw89_rf_path
RF_PATH_BC	core.h	/^	RF_PATH_BC,$/;"	e	enum:rtw89_rf_path
RF_PATH_BCD	core.h	/^	RF_PATH_BCD,$/;"	e	enum:rtw89_rf_path
RF_PATH_BD	core.h	/^	RF_PATH_BD,$/;"	e	enum:rtw89_rf_path
RF_PATH_C	core.h	/^	RF_PATH_C = 2,$/;"	e	enum:rtw89_rf_path
RF_PATH_CD	core.h	/^	RF_PATH_CD,$/;"	e	enum:rtw89_rf_path
RF_PATH_D	core.h	/^	RF_PATH_D = 3,$/;"	e	enum:rtw89_rf_path
RF_PATH_MAX	core.h	467;"	d
RF_PATH_NUM_8852A	rtw8852a.h	10;"	d
RMAC_CMAC_DBG_SEL	mac.h	454;"	d
RMAC_DBG_SEL_C0	mac.h	440;"	d
RMAC_DBG_SEL_C1	mac.h	443;"	d
RPT_EN_ALL	coex.c	/^	RPT_EN_ALL = GENMASK(6, 0),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_BT_AFH_MAP	coex.c	/^	RPT_EN_BT_AFH_MAP = BIT(5),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_BT_ALL	coex.c	/^	RPT_EN_BT_ALL = GENMASK(6, 3),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_BT_DEVICE_INFO	coex.c	/^	RPT_EN_BT_DEVICE_INFO = BIT(6),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_BT_SCAN_INFO	coex.c	/^	RPT_EN_BT_SCAN_INFO = BIT(4),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_BT_VER_INFO	coex.c	/^	RPT_EN_BT_VER_INFO = BIT(3),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_CYCLE	coex.c	/^	RPT_EN_CYCLE = BIT(1),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_MREG	coex.c	/^	RPT_EN_MREG = BIT(2),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_TDMA	coex.c	/^	RPT_EN_TDMA = BIT(0),$/;"	e	enum:btc_btf_set_report_en	file:
RPT_EN_WL_ALL	coex.c	/^	RPT_EN_WL_ALL = GENMASK(2, 0),$/;"	e	enum:btc_btf_set_report_en	file:
RPWM_SEQ_NUM_MAX	reg.h	116;"	d
RR_BIAS	reg.h	1597;"	d
RR_BIASA	reg.h	1599;"	d
RR_BIASA2	reg.h	1603;"	d
RR_BIASA2_LB	reg.h	1604;"	d
RR_BIASA_A	reg.h	1602;"	d
RR_BIASA_TXA	reg.h	1601;"	d
RR_BIASA_TXG	reg.h	1600;"	d
RR_BIAS_GAPK	reg.h	1598;"	d
RR_BSPAD	reg.h	1580;"	d
RR_BTC	reg.h	1550;"	d
RR_BTC_RXBB	reg.h	1552;"	d
RR_BTC_TXBB	reg.h	1551;"	d
RR_CFGCH	reg.h	1549;"	d
RR_DCK	reg.h	1634;"	d
RR_DCK1	reg.h	1637;"	d
RR_DCK1_SEL	reg.h	1638;"	d
RR_DCK2	reg.h	1639;"	d
RR_DCK2_CYCLE	reg.h	1640;"	d
RR_DCK_FINE	reg.h	1635;"	d
RR_DCK_LV	reg.h	1636;"	d
RR_DTXLOK	reg.h	1547;"	d
RR_EN_TIA_IDA	reg.h	1630;"	d
RR_GAINTX	reg.h	1584;"	d
RR_GAINTX_ALL	reg.h	1585;"	d
RR_GAINTX_BB	reg.h	1587;"	d
RR_GAINTX_PAD	reg.h	1586;"	d
RR_LUTDBG	reg.h	1649;"	d
RR_LUTDBG_LOK	reg.h	1650;"	d
RR_LUTWA	reg.h	1566;"	d
RR_LUTWA_MASK	reg.h	1567;"	d
RR_LUTWD0	reg.h	1569;"	d
RR_LUTWD1	reg.h	1568;"	d
RR_LUTWE	reg.h	1652;"	d
RR_LUTWE2	reg.h	1651;"	d
RR_LUTWE_LOK	reg.h	1653;"	d
RR_MALSEL	reg.h	1644;"	d
RR_MIXER	reg.h	1641;"	d
RR_MIXER_GN	reg.h	1642;"	d
RR_MOD	reg.h	1527;"	d
RR_MODOPT	reg.h	1541;"	d
RR_MODOPT_M_TXPWR	reg.h	1542;"	d
RR_MOD_DPK	reg.h	1529;"	d
RR_MOD_IQK	reg.h	1528;"	d
RR_MOD_MASK	reg.h	1530;"	d
RR_MOD_M_RXBB	reg.h	1540;"	d
RR_MOD_M_RXG	reg.h	1539;"	d
RR_MOD_V_DOWN	reg.h	1531;"	d
RR_MOD_V_DPK	reg.h	1536;"	d
RR_MOD_V_RX	reg.h	1534;"	d
RR_MOD_V_RXK1	reg.h	1537;"	d
RR_MOD_V_RXK2	reg.h	1538;"	d
RR_MOD_V_STANDBY	reg.h	1532;"	d
RR_MOD_V_TX	reg.h	1533;"	d
RR_MOD_V_TXIQK	reg.h	1535;"	d
RR_RCKC	reg.h	1553;"	d
RR_RCKC_CA	reg.h	1554;"	d
RR_RCKD	reg.h	1645;"	d
RR_RCKD_BW	reg.h	1647;"	d
RR_RCKD_POW	reg.h	1646;"	d
RR_RCKO	reg.h	1556;"	d
RR_RCKO_OFF	reg.h	1557;"	d
RR_RCKS	reg.h	1555;"	d
RR_RFC	reg.h	1654;"	d
RR_RFC_CKEN	reg.h	1655;"	d
RR_RSV1	reg.h	1545;"	d
RR_RSV1_RST	reg.h	1546;"	d
RR_RSV2	reg.h	1548;"	d
RR_RSV4	reg.h	1561;"	d
RR_RSV6	reg.h	1608;"	d
RR_RXA	reg.h	1621;"	d
RR_RXA2	reg.h	1623;"	d
RR_RXA2_C1	reg.h	1625;"	d
RR_RXA2_C2	reg.h	1624;"	d
RR_RXA_DPK	reg.h	1622;"	d
RR_RXBB	reg.h	1614;"	d
RR_RXBB2	reg.h	1629;"	d
RR_RXBB2_DAC_EN	reg.h	1631;"	d
RR_RXBB_ATTC	reg.h	1618;"	d
RR_RXBB_ATTR	reg.h	1617;"	d
RR_RXBB_C1G	reg.h	1616;"	d
RR_RXBB_C2G	reg.h	1615;"	d
RR_RXIQGEN	reg.h	1626;"	d
RR_RXIQGEN_ATTH	reg.h	1628;"	d
RR_RXIQGEN_ATTL	reg.h	1627;"	d
RR_RXK	reg.h	1562;"	d
RR_RXKPLL	reg.h	1558;"	d
RR_RXKPLL_OFF	reg.h	1559;"	d
RR_RXKPLL_POW	reg.h	1560;"	d
RR_RXK_PLLEN	reg.h	1563;"	d
RR_RXK_SEL2G	reg.h	1565;"	d
RR_RXK_SEL5G	reg.h	1564;"	d
RR_RXPOW	reg.h	1612;"	d
RR_RXPOW_IQK	reg.h	1613;"	d
RR_TM	reg.h	1570;"	d
RR_TM2	reg.h	1573;"	d
RR_TM2_OFF	reg.h	1574;"	d
RR_TM_TRI	reg.h	1571;"	d
RR_TM_VAL	reg.h	1572;"	d
RR_TRXIQ	reg.h	1607;"	d
RR_TXA	reg.h	1593;"	d
RR_TXADBG	reg.h	1648;"	d
RR_TXATANK	reg.h	1605;"	d
RR_TXATANK_LBSW	reg.h	1606;"	d
RR_TXA_TRK	reg.h	1594;"	d
RR_TXG1	reg.h	1575;"	d
RR_TXG1_ATT1	reg.h	1577;"	d
RR_TXG1_ATT2	reg.h	1576;"	d
RR_TXG2	reg.h	1578;"	d
RR_TXG2_ATT0	reg.h	1579;"	d
RR_TXGA	reg.h	1581;"	d
RR_TXGA_LOK_EN	reg.h	1582;"	d
RR_TXGA_TRK_EN	reg.h	1583;"	d
RR_TXMO	reg.h	1588;"	d
RR_TXMO_COI	reg.h	1589;"	d
RR_TXMO_COQ	reg.h	1590;"	d
RR_TXMO_FII	reg.h	1591;"	d
RR_TXMO_FIQ	reg.h	1592;"	d
RR_TXPOW	reg.h	1609;"	d
RR_TXPOW_TXA	reg.h	1611;"	d
RR_TXPOW_TXG	reg.h	1610;"	d
RR_TXRSV	reg.h	1595;"	d
RR_TXRSV_GAPK	reg.h	1596;"	d
RR_WLSEL	reg.h	1543;"	d
RR_WLSEL_AG	reg.h	1544;"	d
RR_XALNA2	reg.h	1632;"	d
RR_XALNA2_SW	reg.h	1633;"	d
RR_XGLNA2	reg.h	1619;"	d
RR_XGLNA2_SW	reg.h	1620;"	d
RR_XTALX2	reg.h	1643;"	d
RSSI_FACTOR	core.h	34;"	d
RTL8852A	core.h	/^	RTL8852A,$/;"	e	enum:rtw89_core_chip_id
RTL8852B	core.h	/^	RTL8852B,$/;"	e	enum:rtw89_core_chip_id
RTL8852C	core.h	/^	RTL8852C,$/;"	e	enum:rtw89_core_chip_id
RTW8852A_DPK_KIP_REG_NUM	rtw8852a_rfk.c	1838;"	d	file:
RTW8852A_DPK_RF_PATH	rtw8852a_rfk.c	1837;"	d	file:
RTW8852A_DPK_TH_AVG_NUM	rtw8852a_rfk.c	1836;"	d	file:
RTW8852A_DPK_VER	rtw8852a_rfk.c	1835;"	d	file:
RTW8852A_IQK_CFIR_GROUP_NR	rtw8852a_rfk.c	598;"	d	file:
RTW8852A_IQK_SS	rtw8852a_rfk.c	596;"	d	file:
RTW8852A_IQK_THR_REK	rtw8852a_rfk.c	597;"	d	file:
RTW8852A_IQK_VER	rtw8852a_rfk.c	595;"	d	file:
RTW8852A_NCTL_VER	rtw8852a_rfk.c	594;"	d	file:
RTW8852A_RF_REL_VERSION	rtw8852a_rfk.c	1834;"	d	file:
RTW89_1TX	core.h	/^	RTW89_1TX	= 0,$/;"	e	enum:rtw89_ntx
RTW89_2G_BW_NUM	core.h	547;"	d
RTW89_2G_CH_NUM	core.h	353;"	d
RTW89_2TX	core.h	/^	RTW89_2TX	= 1,$/;"	e	enum:rtw89_ntx
RTW89_5G_BW_NUM	core.h	548;"	d
RTW89_5G_CH_NUM	core.h	364;"	d
RTW89_ACMA	core.h	/^	RTW89_ACMA	= 9,$/;"	e	enum:rtw89_regulation_type
RTW89_ADDR_CAM_SEC_4GROUP	core.h	/^	RTW89_ADDR_CAM_SEC_4GROUP	= 3,$/;"	e	enum:rtw89_add_cam_sec_mode
RTW89_ADDR_CAM_SEC_ALL_UNI	core.h	/^	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,$/;"	e	enum:rtw89_add_cam_sec_mode
RTW89_ADDR_CAM_SEC_NONE	core.h	/^	RTW89_ADDR_CAM_SEC_NONE		= 0,$/;"	e	enum:rtw89_add_cam_sec_mode
RTW89_ADDR_CAM_SEC_NORMAL	core.h	/^	RTW89_ADDR_CAM_SEC_NORMAL	= 2,$/;"	e	enum:rtw89_add_cam_sec_mode
RTW89_BAND_2G	core.h	/^	RTW89_BAND_2G = 0,$/;"	e	enum:rtw89_band
RTW89_BAND_5G	core.h	/^	RTW89_BAND_5G = 1,$/;"	e	enum:rtw89_band
RTW89_BAND_MAX	core.h	/^	RTW89_BAND_MAX,$/;"	e	enum:rtw89_band
RTW89_BF	core.h	/^	RTW89_BF	= 1,$/;"	e	enum:rtw89_beamforming_type
RTW89_BF_NUM	core.h	/^	RTW89_BF_NUM,$/;"	e	enum:rtw89_beamforming_type
RTW89_BSSID	core.h	/^	RTW89_BSSID$/;"	e	enum:rtw89_msk_sO_el
RTW89_BTC_DM_CNT_MAX	core.h	1180;"	d
RTW89_BTC_DM_MAXSTEP	core.h	1179;"	d
RTW89_BTC_POLICY_MAXLEN	core.h	1710;"	d
RTW89_BTC_WL_DEF_TX_PWR	core.h	1507;"	d
RTW89_BW20_SEC_NUM	core.h	/^	RTW89_BW20_SEC_NUM = 8,$/;"	e	enum:rtw89_bandwidth_section_num
RTW89_BW40_SEC_NUM	core.h	/^	RTW89_BW40_SEC_NUM = 4,$/;"	e	enum:rtw89_bandwidth_section_num
RTW89_BW80_SEC_NUM	core.h	/^	RTW89_BW80_SEC_NUM = 2,$/;"	e	enum:rtw89_bandwidth_section_num
RTW89_C2HREG_HDR_LEN	fw.h	33;"	d
RTW89_C2HREG_MAX	fw.h	32;"	d
RTW89_C2H_CAT_MAC	fw.h	/^	RTW89_C2H_CAT_MAC,$/;"	e	enum:rtw89_fw_c2h_category
RTW89_C2H_CAT_OUTSRC	fw.h	/^	RTW89_C2H_CAT_OUTSRC,$/;"	e	enum:rtw89_fw_c2h_category
RTW89_C2H_CAT_TEST	fw.h	/^	RTW89_C2H_CAT_TEST,$/;"	e	enum:rtw89_fw_c2h_category
RTW89_C2H_HEADER_LEN	fw.h	1168;"	d
RTW89_C2H_TIMEOUT	fw.h	35;"	d
RTW89_CCX_16_US	phy.h	/^	RTW89_CCX_16_US = 2,$/;"	e	enum:rtw89_ccx_unit
RTW89_CCX_32_US	phy.h	/^	RTW89_CCX_32_US = 3$/;"	e	enum:rtw89_ccx_unit
RTW89_CCX_4_US	phy.h	/^	RTW89_CCX_4_US = 0,$/;"	e	enum:rtw89_ccx_unit
RTW89_CCX_8_US	phy.h	/^	RTW89_CCX_8_US = 1,$/;"	e	enum:rtw89_ccx_unit
RTW89_CCX_EDCCA_BW20_0	core.h	/^	RTW89_CCX_EDCCA_BW20_0 = 0,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_1	core.h	/^	RTW89_CCX_EDCCA_BW20_1 = 1,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_2	core.h	/^	RTW89_CCX_EDCCA_BW20_2 = 2,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_3	core.h	/^	RTW89_CCX_EDCCA_BW20_3 = 3,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_4	core.h	/^	RTW89_CCX_EDCCA_BW20_4 = 4,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_5	core.h	/^	RTW89_CCX_EDCCA_BW20_5 = 5,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_6	core.h	/^	RTW89_CCX_EDCCA_BW20_6 = 6,$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_BW20_7	core.h	/^	RTW89_CCX_EDCCA_BW20_7 = 7$/;"	e	enum:rtw89_ccx_edcca_opt_bw_idx
RTW89_CCX_EDCCA_SEG0_P0	core.h	/^	RTW89_CCX_EDCCA_SEG0_P0 = 0,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG0_S1	core.h	/^	RTW89_CCX_EDCCA_SEG0_S1 = 1,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG0_S2	core.h	/^	RTW89_CCX_EDCCA_SEG0_S2 = 2,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG0_S3	core.h	/^	RTW89_CCX_EDCCA_SEG0_S3 = 3,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG1_P0	core.h	/^	RTW89_CCX_EDCCA_SEG1_P0 = 4,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG1_S1	core.h	/^	RTW89_CCX_EDCCA_SEG1_S1 = 5,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG1_S2	core.h	/^	RTW89_CCX_EDCCA_SEG1_S2 = 6,$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CCX_EDCCA_SEG1_S3	core.h	/^	RTW89_CCX_EDCCA_SEG1_S3 = 7$/;"	e	enum:rtw89_ccx_edcca_opt_sc_idx
RTW89_CHANNEL_WIDTH_10	core.h	/^	RTW89_CHANNEL_WIDTH_10	= 6,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_160	core.h	/^	RTW89_CHANNEL_WIDTH_160	= 3,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_20	core.h	/^	RTW89_CHANNEL_WIDTH_20	= 0,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_40	core.h	/^	RTW89_CHANNEL_WIDTH_40	= 1,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_5	core.h	/^	RTW89_CHANNEL_WIDTH_5	= 5,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_80	core.h	/^	RTW89_CHANNEL_WIDTH_80	= 2,$/;"	e	enum:rtw89_bandwidth
RTW89_CHANNEL_WIDTH_80_80	core.h	/^	RTW89_CHANNEL_WIDTH_80_80	= 4,$/;"	e	enum:rtw89_bandwidth
RTW89_CHILE	core.h	/^	RTW89_CHILE	= 8,$/;"	e	enum:rtw89_regulation_type
RTW89_CH_2G	core.h	/^	RTW89_CH_2G = 0,$/;"	e	enum:rtw89_subband
RTW89_CH_5G_BAND_1	core.h	/^	RTW89_CH_5G_BAND_1 = 1,$/;"	e	enum:rtw89_subband
RTW89_CH_5G_BAND_3	core.h	/^	RTW89_CH_5G_BAND_3 = 3,$/;"	e	enum:rtw89_subband
RTW89_CH_5G_BAND_4	core.h	/^	RTW89_CH_5G_BAND_4 = 4,$/;"	e	enum:rtw89_subband
RTW89_CMAC_SEL	mac.h	/^	RTW89_CMAC_SEL = 1,$/;"	e	enum:rtw89_mac_hwmod_sel
RTW89_CN	core.h	/^	RTW89_CN	= 12,$/;"	e	enum:rtw89_regulation_type
RTW89_COEX_ACT1_WORK_PERIOD	coex.h	31;"	d
RTW89_COEX_BT_DEVINFO_WORK_PERIOD	coex.h	32;"	d
RTW89_COEX_RFK_CHK_WORK_PERIOD	coex.h	33;"	d
RTW89_CORE_RX_TYPE_BB_SCOPE	core.h	/^	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_C2H	core.h	/^	RTW89_CORE_RX_TYPE_C2H		= 10,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_CHAN_INFO	core.h	/^	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_CQI	core.h	/^	RTW89_CORE_RX_TYPE_CQI		= 12,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_CSI	core.h	/^	RTW89_CORE_RX_TYPE_CSI		= 11,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_DFS_REPORT	core.h	/^	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_F2P_TXCMD	core.h	/^	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_PPDU_STAT	core.h	/^	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_SS2FW	core.h	/^	RTW89_CORE_RX_TYPE_SS2FW	= 5,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_TX_REL_CPU	core.h	/^	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_TX_REL_HOST	core.h	/^	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_TX_REPORT	core.h	/^	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_RX_TYPE_WIFI	core.h	/^	RTW89_CORE_RX_TYPE_WIFI		= 0,$/;"	e	enum:rtw89_core_rx_type
RTW89_CORE_TX_TYPE_DATA	core.h	/^	RTW89_CORE_TX_TYPE_DATA,$/;"	e	enum:rtw89_core_tx_type
RTW89_CORE_TX_TYPE_FWCMD	core.h	/^	RTW89_CORE_TX_TYPE_FWCMD,$/;"	e	enum:rtw89_core_tx_type
RTW89_CORE_TX_TYPE_MGMT	core.h	/^	RTW89_CORE_TX_TYPE_MGMT,$/;"	e	enum:rtw89_core_tx_type
RTW89_CTRL	mac.h	/^	RTW89_CTRL = 1,$/;"	e	enum:rtw89_machdr_frame_type
RTW89_DACK_IDX_NR	core.h	2402;"	d
RTW89_DACK_MSBK_NR	core.h	2403;"	d
RTW89_DACK_PATH_NR	core.h	2401;"	d
RTW89_DATA	mac.h	/^	RTW89_DATA = 2,$/;"	e	enum:rtw89_machdr_frame_type
RTW89_DBG_BF	debug.h	/^	RTW89_DBG_BF = BIT(14),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_BTC	debug.h	/^	RTW89_DBG_BTC = BIT(13),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_CFO	debug.h	/^	RTW89_DBG_CFO = BIT(3),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_DIG	debug.h	/^	RTW89_DBG_DIG = BIT(10),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_FW	debug.h	/^	RTW89_DBG_FW = BIT(12),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_HCI	debug.h	/^	RTW89_DBG_HCI = BIT(6),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_PHY_TRACK	debug.h	/^	RTW89_DBG_PHY_TRACK = BIT(9),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_PORT_SEL_INVALID	mac.h	/^	RTW89_DBG_PORT_SEL_INVALID = RTW89_DBG_PORT_SEL_LAST,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_LAST	mac.h	/^	RTW89_DBG_PORT_SEL_LAST,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_MAX	mac.h	/^	RTW89_DBG_PORT_SEL_MAX = RTW89_DBG_PORT_SEL_LAST,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_CVT	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_CVT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_CXPL	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_CXPL,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_IO	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_IO,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_MISC	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_MISC,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_MISC2	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_MISC2,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_RXDMA	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_RXDMA,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PCIE_TXDMA	mac.h	/^	RTW89_DBG_PORT_SEL_PCIE_TXDMA,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PKTINFO	mac.h	/^	RTW89_DBG_PORT_SEL_PKTINFO,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL	mac.h	/^	RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PTCL_C0	mac.h	/^	RTW89_DBG_PORT_SEL_PTCL_C0 = 0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_PTCL_C1	mac.h	/^	RTW89_DBG_PORT_SEL_PTCL_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMACST_C0	mac.h	/^	RTW89_DBG_PORT_SEL_RMACST_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMACST_C1	mac.h	/^	RTW89_DBG_PORT_SEL_RMACST_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMAC_C0	mac.h	/^	RTW89_DBG_PORT_SEL_RMAC_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMAC_C1	mac.h	/^	RTW89_DBG_PORT_SEL_RMAC_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMAC_PLCP_C0	mac.h	/^	RTW89_DBG_PORT_SEL_RMAC_PLCP_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_RMAC_PLCP_C1	mac.h	/^	RTW89_DBG_PORT_SEL_RMAC_PLCP_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_SCH_C0	mac.h	/^	RTW89_DBG_PORT_SEL_SCH_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_SCH_C1	mac.h	/^	RTW89_DBG_PORT_SEL_SCH_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TMAC_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TMAC_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TMAC_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TMAC_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TRXPTCL_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TRXPTCL_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TRXPTCL_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TRXPTCL_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TXTF_INFOH_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TXTF_INFOH_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TXTF_INFOH_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TXTF_INFOH_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TXTF_INFOL_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TXTF_INFOL_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TXTF_INFOL_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TXTF_INFOL_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TX_INFOH_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TX_INFOH_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TX_INFOH_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TX_INFOH_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TX_INFOL_C0	mac.h	/^	RTW89_DBG_PORT_SEL_TX_INFOL_C0,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_TX_INFOL_C1	mac.h	/^	RTW89_DBG_PORT_SEL_TX_INFOL_C1,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL	mac.h	/^	RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL,$/;"	e	enum:rtw89_mac_dbg_port_sel
RTW89_DBG_RA	debug.h	/^	RTW89_DBG_RA = BIT(7),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_REGD	debug.h	/^	RTW89_DBG_REGD = BIT(8),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_RFK	debug.h	/^	RTW89_DBG_RFK = BIT(1),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_RFK_TRACK	debug.h	/^	RTW89_DBG_RFK_TRACK = BIT(2),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_SEL_BB	debug.h	/^	RTW89_DBG_SEL_BB,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_IQK	debug.h	/^	RTW89_DBG_SEL_IQK,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_MAC_00	debug.h	/^	RTW89_DBG_SEL_MAC_00,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_MAC_40	debug.h	/^	RTW89_DBG_SEL_MAC_40,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_MAC_80	debug.h	/^	RTW89_DBG_SEL_MAC_80,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_MAC_C0	debug.h	/^	RTW89_DBG_SEL_MAC_C0,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_MAC_E0	debug.h	/^	RTW89_DBG_SEL_MAC_E0,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SEL_RFC	debug.h	/^	RTW89_DBG_SEL_RFC,$/;"	e	enum:rtw89_debug_mac_reg_sel
RTW89_DBG_SER	debug.h	/^	RTW89_DBG_SER = BIT(11),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_TSSI	debug.h	/^	RTW89_DBG_TSSI = BIT(4),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_TXPWR	debug.h	/^	RTW89_DBG_TXPWR = BIT(5),$/;"	e	enum:rtw89_debug_mask
RTW89_DBG_TXRX	debug.h	/^	RTW89_DBG_TXRX = BIT(0),$/;"	e	enum:rtw89_debug_mask
RTW89_DEF_FBTC_MREG	core.h	1392;"	d
RTW89_DIG_GAIN_LNA_A	phy.h	/^	RTW89_DIG_GAIN_LNA_A = 2,$/;"	e	enum:rtw89_dig_gain_type
RTW89_DIG_GAIN_LNA_G	phy.h	/^	RTW89_DIG_GAIN_LNA_G = 0,$/;"	e	enum:rtw89_dig_gain_type
RTW89_DIG_GAIN_LNA_IDX1	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX1 = 1,$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_LNA_IDX2	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX2 = 2,$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_LNA_IDX3	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX3 = 3,$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_LNA_IDX4	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX4 = 4,$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_LNA_IDX5	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX5 = 5,$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_LNA_IDX6	phy.h	/^	RTW89_DIG_GAIN_LNA_IDX6 = 6$/;"	e	enum:rtw89_dig_gain_lna_idx
RTW89_DIG_GAIN_MAX	phy.h	/^	RTW89_DIG_GAIN_MAX = 4$/;"	e	enum:rtw89_dig_gain_type
RTW89_DIG_GAIN_TIA_A	phy.h	/^	RTW89_DIG_GAIN_TIA_A = 3,$/;"	e	enum:rtw89_dig_gain_type
RTW89_DIG_GAIN_TIA_G	phy.h	/^	RTW89_DIG_GAIN_TIA_G = 1,$/;"	e	enum:rtw89_dig_gain_type
RTW89_DIG_GAIN_TIA_IDX0	phy.h	/^	RTW89_DIG_GAIN_TIA_IDX0 = 0,$/;"	e	enum:rtw89_dig_gain_tia_idx
RTW89_DIG_GAIN_TIA_IDX1	phy.h	/^	RTW89_DIG_GAIN_TIA_IDX1 = 1$/;"	e	enum:rtw89_dig_gain_tia_idx
RTW89_DIG_NOISY_LEVEL0	core.h	/^	RTW89_DIG_NOISY_LEVEL0 = -1,$/;"	e	enum:rtw89_dig_noisy_level
RTW89_DIG_NOISY_LEVEL1	core.h	/^	RTW89_DIG_NOISY_LEVEL1 = 0,$/;"	e	enum:rtw89_dig_noisy_level
RTW89_DIG_NOISY_LEVEL2	core.h	/^	RTW89_DIG_NOISY_LEVEL2 = 1,$/;"	e	enum:rtw89_dig_noisy_level
RTW89_DIG_NOISY_LEVEL3	core.h	/^	RTW89_DIG_NOISY_LEVEL3 = 2,$/;"	e	enum:rtw89_dig_noisy_level
RTW89_DIG_NOISY_LEVEL_MAX	core.h	/^	RTW89_DIG_NOISY_LEVEL_MAX = 3,$/;"	e	enum:rtw89_dig_noisy_level
RTW89_DMAC_SEL	mac.h	/^	RTW89_DMAC_SEL = 0,$/;"	e	enum:rtw89_mac_hwmod_sel
RTW89_DMA_ACH0	core.h	/^	RTW89_DMA_ACH0 = 0,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH1	core.h	/^	RTW89_DMA_ACH1 = 1,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH2	core.h	/^	RTW89_DMA_ACH2 = 2,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH3	core.h	/^	RTW89_DMA_ACH3 = 3,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH4	core.h	/^	RTW89_DMA_ACH4 = 4,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH5	core.h	/^	RTW89_DMA_ACH5 = 5,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH6	core.h	/^	RTW89_DMA_ACH6 = 6,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_ACH7	core.h	/^	RTW89_DMA_ACH7 = 7,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_B0HI	core.h	/^	RTW89_DMA_B0HI = 9,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_B0MG	core.h	/^	RTW89_DMA_B0MG = 8,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_B1HI	core.h	/^	RTW89_DMA_B1HI = 11,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_B1MG	core.h	/^	RTW89_DMA_B1MG = 10,$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_CH_NUM	core.h	/^	RTW89_DMA_CH_NUM = 13$/;"	e	enum:rtw89_dma_ch
RTW89_DMA_H2C	core.h	/^	RTW89_DMA_H2C = 12,$/;"	e	enum:rtw89_dma_ch
RTW89_DPK_AVG_THERMAL_NUM	core.h	2452;"	d
RTW89_DPK_BKUP_NUM	core.h	2453;"	d
RTW89_DPK_RF_PATH	core.h	2451;"	d
RTW89_EFUSE_BANK_BT	efuse.c	/^	RTW89_EFUSE_BANK_BT,$/;"	e	enum:rtw89_efuse_bank	file:
RTW89_EFUSE_BANK_WIFI	efuse.c	/^	RTW89_EFUSE_BANK_WIFI,$/;"	e	enum:rtw89_efuse_bank	file:
RTW89_ENTRY_BASED_AVG_MODE	core.h	/^	RTW89_ENTRY_BASED_AVG_MODE = 1,$/;"	e	enum:rtw89_multi_cfo_mode
RTW89_ETSI	core.h	/^	RTW89_ETSI	= 1,$/;"	e	enum:rtw89_regulation_type
RTW89_FAHM_RPT_NUM	core.h	2660;"	d
RTW89_FAHM_TH_NUM	core.h	2658;"	d
RTW89_FCC	core.h	/^	RTW89_FCC	= 2,$/;"	e	enum:rtw89_regulation_type
RTW89_FLAG_BFEE_EN	core.h	/^	RTW89_FLAG_BFEE_EN,$/;"	e	enum:rtw89_flags
RTW89_FLAG_BFEE_MON	core.h	/^	RTW89_FLAG_BFEE_MON,$/;"	e	enum:rtw89_flags
RTW89_FLAG_FW_RDY	core.h	/^	RTW89_FLAG_FW_RDY,$/;"	e	enum:rtw89_flags
RTW89_FLAG_INACTIVE_PS	core.h	/^	RTW89_FLAG_INACTIVE_PS,$/;"	e	enum:rtw89_flags
RTW89_FLAG_LEISURE_PS	core.h	/^	RTW89_FLAG_LEISURE_PS,$/;"	e	enum:rtw89_flags
RTW89_FLAG_LOW_POWER_MODE	core.h	/^	RTW89_FLAG_LOW_POWER_MODE,$/;"	e	enum:rtw89_flags
RTW89_FLAG_NAPI_RUNNING	core.h	/^	RTW89_FLAG_NAPI_RUNNING,$/;"	e	enum:rtw89_flags
RTW89_FLAG_POWERON	core.h	/^	RTW89_FLAG_POWERON,$/;"	e	enum:rtw89_flags
RTW89_FLAG_RUNNING	core.h	/^	RTW89_FLAG_RUNNING,$/;"	e	enum:rtw89_flags
RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0,$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_C2HREG_FUNC_ERR_MSG	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_ERR_MSG,$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_C2HREG_FUNC_ERR_RPT	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_ERR_RPT,$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_C2HREG_FUNC_NULL	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_C2HREG_FUNC_PHY_CAP	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_PHY_CAP,$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT	fw.h	/^	RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT,$/;"	e	enum:rtw89_mac_c2h_type
RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD,$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWCMD_H2CREG_FUNC_FWERR	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_FWERR,$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM,$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE,$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0,$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN	fw.h	/^	RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN$/;"	e	enum:rtw89_mac_h2c_type
RTW89_FWDL_CHECKSUM_FAIL	fw.h	/^	RTW89_FWDL_CHECKSUM_FAIL = 2,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_CV_NOT_MATCH	fw.h	/^	RTW89_FWDL_CV_NOT_MATCH = 4,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_FWDL_ONGOING	fw.h	/^	RTW89_FWDL_FWDL_ONGOING = 1,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_INITIAL_STATE	fw.h	/^	RTW89_FWDL_INITIAL_STATE = 0,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_RSVD0	fw.h	/^	RTW89_FWDL_RSVD0 = 5,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_SECURITY_FAIL	fw.h	/^	RTW89_FWDL_SECURITY_FAIL = 3,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_WCPU_FWDL_RDY	fw.h	/^	RTW89_FWDL_WCPU_FWDL_RDY = 6,$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWDL_WCPU_FW_INIT_RDY	fw.h	/^	RTW89_FWDL_WCPU_FW_INIT_RDY = 7$/;"	e	enum:rtw89_fw_dl_status
RTW89_FWD_DONT_CARE	mac.h	/^	RTW89_FWD_DONT_CARE    = 0,$/;"	e	enum:rtw89_mac_fwd_target
RTW89_FWD_TO_HOST	mac.h	/^	RTW89_FWD_TO_HOST      = 1,$/;"	e	enum:rtw89_mac_fwd_target
RTW89_FWD_TO_WLAN_CPU	mac.h	/^	RTW89_FWD_TO_WLAN_CPU  = 2$/;"	e	enum:rtw89_mac_fwd_target
RTW89_FW_HDR_SIZE	fw.h	1224;"	d
RTW89_FW_LOG_COMP_BB	fw.h	/^	RTW89_FW_LOG_COMP_BB,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_BTC	fw.h	/^	RTW89_FW_LOG_COMP_BTC,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_C2H	fw.h	/^	RTW89_FW_LOG_COMP_C2H,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_CNS	fw.h	/^	RTW89_FW_LOG_COMP_CNS,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_DBGPKT	fw.h	/^	RTW89_FW_LOG_COMP_DBGPKT,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_ERROR	fw.h	/^	RTW89_FW_LOG_COMP_ERROR,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_H2C	fw.h	/^	RTW89_FW_LOG_COMP_H2C,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_INIT	fw.h	/^	RTW89_FW_LOG_COMP_INIT,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_IPSEC	fw.h	/^	RTW89_FW_LOG_COMP_IPSEC,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_MCC	fw.h	/^	RTW89_FW_LOG_COMP_MCC = 20,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_PS	fw.h	/^	RTW89_FW_LOG_COMP_PS,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_RF	fw.h	/^	RTW89_FW_LOG_COMP_RF,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_RX	fw.h	/^	RTW89_FW_LOG_COMP_RX,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_SECURE_BOOT	fw.h	/^	RTW89_FW_LOG_COMP_SECURE_BOOT,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_TASK	fw.h	/^	RTW89_FW_LOG_COMP_TASK,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_TIMER	fw.h	/^	RTW89_FW_LOG_COMP_TIMER,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_TWT	fw.h	/^	RTW89_FW_LOG_COMP_TWT,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_TX	fw.h	/^	RTW89_FW_LOG_COMP_TX,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_VER	fw.h	/^	RTW89_FW_LOG_COMP_VER,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_COMP_WOWLAN	fw.h	/^	RTW89_FW_LOG_COMP_WOWLAN,$/;"	e	enum:rtw89_fw_log_comp
RTW89_FW_LOG_LEVEL_C2H	fw.h	/^	RTW89_FW_LOG_LEVEL_C2H,$/;"	e	enum:rtw89_fw_log_path
RTW89_FW_LOG_LEVEL_CRT	fw.h	/^	RTW89_FW_LOG_LEVEL_CRT,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_LOG_LEVEL_LOUD	fw.h	/^	RTW89_FW_LOG_LEVEL_LOUD,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_LOG_LEVEL_OFF	fw.h	/^	RTW89_FW_LOG_LEVEL_OFF,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_LOG_LEVEL_SER	fw.h	/^	RTW89_FW_LOG_LEVEL_SER,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_LOG_LEVEL_SNI	fw.h	/^	RTW89_FW_LOG_LEVEL_SNI,$/;"	e	enum:rtw89_fw_log_path
RTW89_FW_LOG_LEVEL_TR	fw.h	/^	RTW89_FW_LOG_LEVEL_TR,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_LOG_LEVEL_UART	fw.h	/^	RTW89_FW_LOG_LEVEL_UART,$/;"	e	enum:rtw89_fw_log_path
RTW89_FW_LOG_LEVEL_WARN	fw.h	/^	RTW89_FW_LOG_LEVEL_WARN,$/;"	e	enum:rtw89_fw_log_level
RTW89_FW_NORMAL	core.h	/^	RTW89_FW_NORMAL = 1,$/;"	e	enum:rtw89_fw_type
RTW89_FW_SECTION_HDR_SIZE	fw.h	1225;"	d
RTW89_FW_SUIT_VER_CODE	core.h	2308;"	d
RTW89_FW_VER_CODE	core.h	2306;"	d
RTW89_FW_WOWLAN	core.h	/^	RTW89_FW_WOWLAN = 3,$/;"	e	enum:rtw89_fw_type
RTW89_GET_C2H_CATEGORY	fw.h	1170;"	d
RTW89_GET_C2H_CLASS	fw.h	1172;"	d
RTW89_GET_C2H_FUNC	fw.h	1174;"	d
RTW89_GET_C2H_HDR_FUNC	fw.h	21;"	d
RTW89_GET_C2H_HDR_LEN	fw.h	23;"	d
RTW89_GET_C2H_LEN	fw.h	1176;"	d
RTW89_GET_C2H_LOG_LEN	fw.h	1180;"	d
RTW89_GET_C2H_LOG_SRT_PRT	fw.h	1179;"	d
RTW89_GET_MAC_C2H_DONE_ACK_CAT	fw.h	1182;"	d
RTW89_GET_MAC_C2H_DONE_ACK_CLASS	fw.h	1184;"	d
RTW89_GET_MAC_C2H_DONE_ACK_FUNC	fw.h	1186;"	d
RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN	fw.h	1188;"	d
RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ	fw.h	1190;"	d
RTW89_GET_MAC_C2H_REV_ACK_CAT	fw.h	1193;"	d
RTW89_GET_MAC_C2H_REV_ACK_CLASS	fw.h	1195;"	d
RTW89_GET_MAC_C2H_REV_ACK_FUNC	fw.h	1197;"	d
RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ	fw.h	1199;"	d
RTW89_GET_PHY_C2H_RA_RPT_BW	fw.h	1212;"	d
RTW89_GET_PHY_C2H_RA_RPT_GILTF	fw.h	1210;"	d
RTW89_GET_PHY_C2H_RA_RPT_MACID	fw.h	1202;"	d
RTW89_GET_PHY_C2H_RA_RPT_MCSNSS	fw.h	1206;"	d
RTW89_GET_PHY_C2H_RA_RPT_MD_SEL	fw.h	1208;"	d
RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO	fw.h	1204;"	d
RTW89_GET_PHY_STS_IE0_CFO	txrx.h	187;"	d
RTW89_GET_PHY_STS_IE_LEN	txrx.h	185;"	d
RTW89_GET_PHY_STS_IE_TYPE	txrx.h	183;"	d
RTW89_GET_PHY_STS_LEN	txrx.h	179;"	d
RTW89_GET_PHY_STS_RSSI_A	txrx.h	171;"	d
RTW89_GET_PHY_STS_RSSI_AVG	txrx.h	181;"	d
RTW89_GET_PHY_STS_RSSI_B	txrx.h	173;"	d
RTW89_GET_PHY_STS_RSSI_C	txrx.h	175;"	d
RTW89_GET_PHY_STS_RSSI_D	txrx.h	177;"	d
RTW89_GET_RXINFO_BCM	txrx.h	166;"	d
RTW89_GET_RXINFO_CTRL	txrx.h	162;"	d
RTW89_GET_RXINFO_DATA	txrx.h	160;"	d
RTW89_GET_RXINFO_FW_DEFINE	txrx.h	144;"	d
RTW89_GET_RXINFO_IS_TO_SELF	txrx.h	148;"	d
RTW89_GET_RXINFO_LONG_RXD	txrx.h	152;"	d
RTW89_GET_RXINFO_LSIG_LEN	txrx.h	146;"	d
RTW89_GET_RXINFO_MACID	txrx.h	168;"	d
RTW89_GET_RXINFO_MAC_ID_VALID	txrx.h	158;"	d
RTW89_GET_RXINFO_MGMT	txrx.h	164;"	d
RTW89_GET_RXINFO_PLCP_LEN	txrx.h	156;"	d
RTW89_GET_RXINFO_RX_CNT_VLD	txrx.h	150;"	d
RTW89_GET_RXINFO_SERVICE	txrx.h	154;"	d
RTW89_GET_RXINFO_USR_NUM	txrx.h	142;"	d
RTW89_GET_RXWD_A1_MATCH	txrx.h	121;"	d
RTW89_GET_RXWD_ADDR_CAM_ID	txrx.h	137;"	d
RTW89_GET_RXWD_ADDR_CAM_VLD	txrx.h	131;"	d
RTW89_GET_RXWD_BB_SEL	txrx.h	89;"	d
RTW89_GET_RXWD_BW	txrx.h	97;"	d
RTW89_GET_RXWD_CRC32_ERR	txrx.h	115;"	d
RTW89_GET_RXWD_DATA_RATE	txrx.h	101;"	d
RTW89_GET_RXWD_DRV_INFO_SIZE	txrx.h	83;"	d
RTW89_GET_RXWD_FRAG	txrx.h	125;"	d
RTW89_GET_RXWD_FREE_RUN_CNT	txrx.h	111;"	d
RTW89_GET_RXWD_GI_LTF	txrx.h	99;"	d
RTW89_GET_RXWD_HD_IV_LEN	txrx.h	91;"	d
RTW89_GET_RXWD_HW_DEC	txrx.h	117;"	d
RTW89_GET_RXWD_ICV_ERR	txrx.h	113;"	d
RTW89_GET_RXWD_LONG_RXD	txrx.h	81;"	d
RTW89_GET_RXWD_MAC_ID	txrx.h	135;"	d
RTW89_GET_RXWD_MAC_INFO_VALID	txrx.h	87;"	d
RTW89_GET_RXWD_PKT_SIZE	txrx.h	95;"	d
RTW89_GET_RXWD_PPDU_CNT	txrx.h	107;"	d
RTW89_GET_RXWD_PPDU_TYPE	txrx.h	109;"	d
RTW89_GET_RXWD_RPKT_TYPE	txrx.h	85;"	d
RTW89_GET_RXWD_RX_PL_ID	txrx.h	133;"	d
RTW89_GET_RXWD_SEC_CAM_ID	txrx.h	139;"	d
RTW89_GET_RXWD_SEQ	txrx.h	127;"	d
RTW89_GET_RXWD_SHIFT	txrx.h	93;"	d
RTW89_GET_RXWD_SR_EN	txrx.h	105;"	d
RTW89_GET_RXWD_SW_DEC	txrx.h	119;"	d
RTW89_GET_RXWD_TYPE	txrx.h	129;"	d
RTW89_GET_RXWD_USER_ID	txrx.h	103;"	d
RTW89_GILTF_1XHE08	core.h	/^	RTW89_GILTF_1XHE08 = 5,$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_1XHE16	core.h	/^	RTW89_GILTF_1XHE16 = 4,$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_2XHE08	core.h	/^	RTW89_GILTF_2XHE08 = 3,$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_2XHE16	core.h	/^	RTW89_GILTF_2XHE16 = 2,$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_LGI_4XHE32	core.h	/^	RTW89_GILTF_LGI_4XHE32 = 0,$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_MAX	core.h	/^	RTW89_GILTF_MAX$/;"	e	enum:rtw89_gi_ltf
RTW89_GILTF_SGI_4XHE08	core.h	/^	RTW89_GILTF_SGI_4XHE08 = 1,$/;"	e	enum:rtw89_gi_ltf
RTW89_H2CREG_HDR_LEN	fw.h	34;"	d
RTW89_H2CREG_MAX	fw.h	31;"	d
RTW89_H2C_RF_PAGE_NUM	fw.h	1252;"	d
RTW89_H2C_RF_PAGE_SIZE	fw.h	1251;"	d
RTW89_HCIFC_MODE_INVALID	core.h	/^	RTW89_HCIFC_MODE_INVALID,$/;"	e	enum:rtw89_hcifc_mode
RTW89_HCIFC_POH	core.h	/^	RTW89_HCIFC_POH = 0,$/;"	e	enum:rtw89_hcifc_mode
RTW89_HCIFC_SDIO	core.h	/^	RTW89_HCIFC_SDIO = 2,$/;"	e	enum:rtw89_hcifc_mode
RTW89_HCIFC_STF	core.h	/^	RTW89_HCIFC_STF = 1,$/;"	e	enum:rtw89_hcifc_mode
RTW89_HCI_TYPE_PCIE	core.h	/^	RTW89_HCI_TYPE_PCIE,$/;"	e	enum:rtw89_hci_type
RTW89_HCI_TYPE_SDIO	core.h	/^	RTW89_HCI_TYPE_SDIO,$/;"	e	enum:rtw89_hci_type
RTW89_HCI_TYPE_USB	core.h	/^	RTW89_HCI_TYPE_USB,$/;"	e	enum:rtw89_hci_type
RTW89_HTC_MASK_CTL_ID	core.h	40;"	d
RTW89_HTC_MASK_CTL_INFO	core.h	43;"	d
RTW89_HTC_MASK_HTC_OM_CH_WIDTH	core.h	52;"	d
RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR	core.h	56;"	d
RTW89_HTC_MASK_HTC_OM_ER_SU_DIS	core.h	55;"	d
RTW89_HTC_MASK_HTC_OM_RX_NSS	core.h	45;"	d
RTW89_HTC_MASK_HTC_OM_TX_NSTS	core.h	54;"	d
RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS	core.h	57;"	d
RTW89_HTC_MASK_HTC_OM_UL_MU_DIS	core.h	53;"	d
RTW89_HTC_MASK_VARIANT	core.h	38;"	d
RTW89_HTC_VARIANT_HE	core.h	39;"	d
RTW89_HTC_VARIANT_HE_CID_CAS	core.h	42;"	d
RTW89_HTC_VARIANT_HE_CID_OM	core.h	41;"	d
RTW89_HW_RATE_CCK1	core.h	/^	RTW89_HW_RATE_CCK1	= 0x0,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_CCK11	core.h	/^	RTW89_HW_RATE_CCK11	= 0x3,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_CCK2	core.h	/^	RTW89_HW_RATE_CCK2	= 0x1,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_CCK5_5	core.h	/^	RTW89_HW_RATE_CCK5_5	= 0x2,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS0	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS1	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS10	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS11	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS2	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS3	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS4	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS5	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS6	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS7	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS8	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS1_MCS9	core.h	/^	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS0	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS1	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS10	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS11	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS2	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS3	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS4	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS5	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS6	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS7	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS8	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS2_MCS9	core.h	/^	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS0	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS1	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS10	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS11	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS2	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS3	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS4	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS5	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS6	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS7	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS8	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS3_MCS9	core.h	/^	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS0	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS1	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS10	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS11	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS2	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS3	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS4	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS5	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS6	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS7	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS8	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_HE_NSS4_MCS9	core.h	/^	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MASK_MOD	core.h	/^	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MASK_VAL	core.h	/^	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS0	core.h	/^	RTW89_HW_RATE_MCS0	= 0x80,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS1	core.h	/^	RTW89_HW_RATE_MCS1	= 0x81,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS10	core.h	/^	RTW89_HW_RATE_MCS10	= 0x8A,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS11	core.h	/^	RTW89_HW_RATE_MCS11	= 0x8B,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS12	core.h	/^	RTW89_HW_RATE_MCS12	= 0x8C,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS13	core.h	/^	RTW89_HW_RATE_MCS13	= 0x8D,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS14	core.h	/^	RTW89_HW_RATE_MCS14	= 0x8E,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS15	core.h	/^	RTW89_HW_RATE_MCS15	= 0x8F,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS16	core.h	/^	RTW89_HW_RATE_MCS16	= 0x90,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS17	core.h	/^	RTW89_HW_RATE_MCS17	= 0x91,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS18	core.h	/^	RTW89_HW_RATE_MCS18	= 0x92,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS19	core.h	/^	RTW89_HW_RATE_MCS19	= 0x93,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS2	core.h	/^	RTW89_HW_RATE_MCS2	= 0x82,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS20	core.h	/^	RTW89_HW_RATE_MCS20	= 0x94,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS21	core.h	/^	RTW89_HW_RATE_MCS21	= 0x95,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS22	core.h	/^	RTW89_HW_RATE_MCS22	= 0x96,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS23	core.h	/^	RTW89_HW_RATE_MCS23	= 0x97,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS24	core.h	/^	RTW89_HW_RATE_MCS24	= 0x98,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS25	core.h	/^	RTW89_HW_RATE_MCS25	= 0x99,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS26	core.h	/^	RTW89_HW_RATE_MCS26	= 0x9A,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS27	core.h	/^	RTW89_HW_RATE_MCS27	= 0x9B,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS28	core.h	/^	RTW89_HW_RATE_MCS28	= 0x9C,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS29	core.h	/^	RTW89_HW_RATE_MCS29	= 0x9D,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS3	core.h	/^	RTW89_HW_RATE_MCS3	= 0x83,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS30	core.h	/^	RTW89_HW_RATE_MCS30	= 0x9E,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS31	core.h	/^	RTW89_HW_RATE_MCS31	= 0x9F,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS4	core.h	/^	RTW89_HW_RATE_MCS4	= 0x84,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS5	core.h	/^	RTW89_HW_RATE_MCS5	= 0x85,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS6	core.h	/^	RTW89_HW_RATE_MCS6	= 0x86,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS7	core.h	/^	RTW89_HW_RATE_MCS7	= 0x87,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS8	core.h	/^	RTW89_HW_RATE_MCS8	= 0x88,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_MCS9	core.h	/^	RTW89_HW_RATE_MCS9	= 0x89,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_NR	core.h	/^	RTW89_HW_RATE_NR,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM12	core.h	/^	RTW89_HW_RATE_OFDM12	= 0x6,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM18	core.h	/^	RTW89_HW_RATE_OFDM18	= 0x7,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM24	core.h	/^	RTW89_HW_RATE_OFDM24	= 0x8,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM36	core.h	/^	RTW89_HW_RATE_OFDM36	= 0x9,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM48	core.h	/^	RTW89_HW_RATE_OFDM48	= 0xA,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM54	core.h	/^	RTW89_HW_RATE_OFDM54	= 0xB,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM6	core.h	/^	RTW89_HW_RATE_OFDM6	= 0x4,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_OFDM9	core.h	/^	RTW89_HW_RATE_OFDM9	= 0x5,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS0	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS1	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS2	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS3	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS4	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS5	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS6	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS7	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS8	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS1_MCS9	core.h	/^	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS0	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS1	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS2	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS3	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS4	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS5	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS6	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS7	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS8	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS2_MCS9	core.h	/^	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS0	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS1	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS2	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS3	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS4	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS5	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS6	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS7	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS8	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS3_MCS9	core.h	/^	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS0	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS1	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS2	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS3	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS4	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS5	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS6	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS7	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS8	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,$/;"	e	enum:rtw89_hw_rate
RTW89_HW_RATE_VHT_NSS4_MCS9	core.h	/^	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,$/;"	e	enum:rtw89_hw_rate
RTW89_IC	core.h	/^	RTW89_IC	= 5,$/;"	e	enum:rtw89_regulation_type
RTW89_IFS_CLM_ACS	core.h	/^	RTW89_IFS_CLM_ACS = 2,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_BACKGROUND	core.h	/^	RTW89_IFS_CLM_BACKGROUND = 1,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_DBG	core.h	/^	RTW89_IFS_CLM_DBG = 5,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_DBG_MANUAL	core.h	/^	RTW89_IFS_CLM_DBG_MANUAL = 6$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_DIG	core.h	/^	RTW89_IFS_CLM_DIG = 3,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_INIT	core.h	/^	RTW89_IFS_CLM_INIT = 0,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IFS_CLM_NUM	core.h	2661;"	d
RTW89_IFS_CLM_TDMA_DIG	core.h	/^	RTW89_IFS_CLM_TDMA_DIG = 4,$/;"	e	enum:rtw89_ifs_clm_application
RTW89_IQK_CHS_NR	core.h	2416;"	d
RTW89_IQK_PATH_NR	core.h	2417;"	d
RTW89_KCC	core.h	/^	RTW89_KCC	= 6,$/;"	e	enum:rtw89_regulation_type
RTW89_L0DLY_MASK	pci.h	334;"	d
RTW89_L1DLY_MASK	pci.h	333;"	d
RTW89_LAST_RPWM_ACTIVE	core.h	/^	RTW89_LAST_RPWM_ACTIVE    = 0x6,$/;"	e	enum:rtw89_last_rpwm_mode
RTW89_LAST_RPWM_PS	core.h	/^	RTW89_LAST_RPWM_PS        = 0x0,$/;"	e	enum:rtw89_last_rpwm_mode
RTW89_LV1_RCVY_STEP_1	core.h	/^	RTW89_LV1_RCVY_STEP_1,$/;"	e	enum:rtw89_lv1_rcvy_step
RTW89_LV1_RCVY_STEP_2	core.h	/^	RTW89_LV1_RCVY_STEP_2,$/;"	e	enum:rtw89_lv1_rcvy_step
RTW89_MAC_0	core.h	/^	RTW89_MAC_0 = 0,$/;"	e	enum:rtw89_mac_idx
RTW89_MAC_1	core.h	/^	RTW89_MAC_1 = 1,$/;"	e	enum:rtw89_mac_idx
RTW89_MAC_AX_COEX_CSR_MODE	mac.h	316;"	d
RTW89_MAC_AX_COEX_GNT_NR	core.h	716;"	d
RTW89_MAC_AX_COEX_INNER	mac.h	318;"	d
RTW89_MAC_AX_COEX_INPUT	mac.h	320;"	d
RTW89_MAC_AX_COEX_OUTPUT	mac.h	319;"	d
RTW89_MAC_AX_COEX_RTK_MODE	mac.h	315;"	d
RTW89_MAC_AX_PLT_GNT_BT_RX	mac.h	327;"	d
RTW89_MAC_AX_PLT_GNT_BT_TX	mac.h	326;"	d
RTW89_MAC_AX_PLT_GNT_WL	mac.h	328;"	d
RTW89_MAC_AX_PLT_LTE_RX	mac.h	325;"	d
RTW89_MAC_AX_PS_MODE_ACTIVE	core.h	/^	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,$/;"	e	enum:rtw89_mac_ax_ps_mode
RTW89_MAC_AX_PS_MODE_LEGACY	core.h	/^	RTW89_MAC_AX_PS_MODE_LEGACY = 1,$/;"	e	enum:rtw89_mac_ax_ps_mode
RTW89_MAC_AX_PS_MODE_MAX	core.h	/^	RTW89_MAC_AX_PS_MODE_MAX    = 3,$/;"	e	enum:rtw89_mac_ax_ps_mode
RTW89_MAC_AX_PS_MODE_WMMPS	core.h	/^	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,$/;"	e	enum:rtw89_mac_ax_ps_mode
RTW89_MAC_BF_RRSC_12M	mac.h	/^	RTW89_MAC_BF_RRSC_12M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_18M	mac.h	/^	RTW89_MAC_BF_RRSC_18M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_24M	mac.h	/^	RTW89_MAC_BF_RRSC_24M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_36M	mac.h	/^	RTW89_MAC_BF_RRSC_36M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_48M	mac.h	/^	RTW89_MAC_BF_RRSC_48M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_54M	mac.h	/^	RTW89_MAC_BF_RRSC_54M,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_6M	mac.h	/^	RTW89_MAC_BF_RRSC_6M = 0,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_9M	mac.h	/^	RTW89_MAC_BF_RRSC_9M = 1,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC0	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC0,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC1	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC1,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC2	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC2,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC3	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC3,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC4	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC4,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC5	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC5,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC6	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC6,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HE_MSC7	mac.h	/^	RTW89_MAC_BF_RRSC_HE_MSC7 = 31,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC0	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC0,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC1	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC1,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC2	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC2,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC3	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC3,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC4	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC4,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC5	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC5,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC6	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC6,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_HT_MSC7	mac.h	/^	RTW89_MAC_BF_RRSC_HT_MSC7,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_MAX	mac.h	/^	RTW89_MAC_BF_RRSC_MAX = 32$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC0	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC0,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC1	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC1,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC2	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC2,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC3	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC3,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC4	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC4,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC5	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC5,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC6	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC6,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_BF_RRSC_VHT_MSC7	mac.h	/^	RTW89_MAC_BF_RRSC_VHT_MSC7,$/;"	e	enum:rtw89_mac_bf_rrsc_rate
RTW89_MAC_C2H_CLASS_FWDBG	mac.h	/^	RTW89_MAC_C2H_CLASS_FWDBG,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_INFO	mac.h	/^	RTW89_MAC_C2H_CLASS_INFO,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_MAX	mac.h	/^	RTW89_MAC_C2H_CLASS_MAX,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_MCC	mac.h	/^	RTW89_MAC_C2H_CLASS_MCC,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_OFLD	mac.h	/^	RTW89_MAC_C2H_CLASS_OFLD,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_TWT	mac.h	/^	RTW89_MAC_C2H_CLASS_TWT,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_CLASS_WOW	mac.h	/^	RTW89_MAC_C2H_CLASS_WOW,$/;"	e	enum:rtw89_mac_c2h_class
RTW89_MAC_C2H_FUNC_BCN_RESEND	mac.h	/^	RTW89_MAC_C2H_FUNC_BCN_RESEND,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_C2H_LOG	mac.h	/^	RTW89_MAC_C2H_FUNC_C2H_LOG,$/;"	e	enum:rtw89_mac_c2h_info_func
RTW89_MAC_C2H_FUNC_DONE_ACK	mac.h	/^	RTW89_MAC_C2H_FUNC_DONE_ACK,$/;"	e	enum:rtw89_mac_c2h_info_func
RTW89_MAC_C2H_FUNC_EFUSE_DUMP	mac.h	/^	RTW89_MAC_C2H_FUNC_EFUSE_DUMP,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_INFO_MAX	mac.h	/^	RTW89_MAC_C2H_FUNC_INFO_MAX,$/;"	e	enum:rtw89_mac_c2h_info_func
RTW89_MAC_C2H_FUNC_MACID_PAUSE	mac.h	/^	RTW89_MAC_C2H_FUNC_MACID_PAUSE,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_OFLD_MAX	mac.h	/^	RTW89_MAC_C2H_FUNC_OFLD_MAX,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP	mac.h	/^	RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_READ_RSP	mac.h	/^	RTW89_MAC_C2H_FUNC_READ_RSP,$/;"	e	enum:rtw89_mac_c2h_ofld_func
RTW89_MAC_C2H_FUNC_REC_ACK	mac.h	/^	RTW89_MAC_C2H_FUNC_REC_ACK,$/;"	e	enum:rtw89_mac_c2h_info_func
RTW89_MAC_INVALID	mac.h	/^	RTW89_MAC_INVALID,$/;"	e	enum:rtw89_mac_hwmod_sel
RTW89_MAC_LBC_TMR_128US	mac.h	/^	RTW89_MAC_LBC_TMR_128US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_16US	mac.h	/^	RTW89_MAC_LBC_TMR_16US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_1MS	mac.h	/^	RTW89_MAC_LBC_TMR_1MS,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_256US	mac.h	/^	RTW89_MAC_LBC_TMR_256US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_2MS	mac.h	/^	RTW89_MAC_LBC_TMR_2MS,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_32US	mac.h	/^	RTW89_MAC_LBC_TMR_32US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_4MS	mac.h	/^	RTW89_MAC_LBC_TMR_4MS,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_512US	mac.h	/^	RTW89_MAC_LBC_TMR_512US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_64US	mac.h	/^	RTW89_MAC_LBC_TMR_64US,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_8MS	mac.h	/^	RTW89_MAC_LBC_TMR_8MS,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_8US	mac.h	/^	RTW89_MAC_LBC_TMR_8US = 0,$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_LBC_TMR_DEF	mac.h	/^	RTW89_MAC_LBC_TMR_DEF = 0xFE$/;"	e	enum:rtw89_mac_lbc_tmr
RTW89_MAC_MEM_ADDR_CAM	mac.h	/^	RTW89_MAC_MEM_ADDR_CAM,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_BA_CAM	mac.h	/^	RTW89_MAC_MEM_BA_CAM,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_BCN_IE_CAM0	mac.h	/^	RTW89_MAC_MEM_BCN_IE_CAM0,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_BCN_IE_CAM1	mac.h	/^	RTW89_MAC_MEM_BCN_IE_CAM1,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_CMAC_TBL	mac.h	/^	RTW89_MAC_MEM_CMAC_TBL,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_DMAC_TBL	mac.h	/^	RTW89_MAC_MEM_DMAC_TBL,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_INVALID	mac.h	/^	RTW89_MAC_MEM_INVALID = RTW89_MAC_MEM_LAST,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_LAST	mac.h	/^	RTW89_MAC_MEM_LAST,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_MAX	mac.h	/^	RTW89_MAC_MEM_MAX = RTW89_MAC_MEM_LAST,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_RXPLD_FLTR_CAM	mac.h	/^	RTW89_MAC_MEM_RXPLD_FLTR_CAM,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_SECURITY_CAM	mac.h	/^	RTW89_MAC_MEM_SECURITY_CAM,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_SHARED_BUF	mac.h	/^	RTW89_MAC_MEM_SHARED_BUF,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_SHCUT_MACHDR	mac.h	/^	RTW89_MAC_MEM_SHCUT_MACHDR,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_STA_SCHED	mac.h	/^	RTW89_MAC_MEM_STA_SCHED,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_MEM_WOW_CAM	mac.h	/^	RTW89_MAC_MEM_WOW_CAM,$/;"	e	enum:rtw89_mac_mem_sel
RTW89_MAC_PAGE_SIZE	debug.c	619;"	d	file:
RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE = 0,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF = 3,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFON = 1,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFOFF = 4,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_BAND1_RFON = 2,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED = 5,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_HIOE_PWR_GATED = 7,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_MAX	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_MAX,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED	mac.h	/^	RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED = 6,$/;"	e	enum:rtw89_rpwm_req_pwr_state
RTW89_MAC_TAG_NUM_1	mac.h	/^	RTW89_MAC_TAG_NUM_1,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_2	mac.h	/^	RTW89_MAC_TAG_NUM_2,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_3	mac.h	/^	RTW89_MAC_TAG_NUM_3,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_4	mac.h	/^	RTW89_MAC_TAG_NUM_4,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_5	mac.h	/^	RTW89_MAC_TAG_NUM_5,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_6	mac.h	/^	RTW89_MAC_TAG_NUM_6,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_7	mac.h	/^	RTW89_MAC_TAG_NUM_7,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_8	mac.h	/^	RTW89_MAC_TAG_NUM_8,$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_TAG_NUM_DEF	mac.h	/^	RTW89_MAC_TAG_NUM_DEF = 0xFE$/;"	e	enum:rtw89_mac_multi_tag_num
RTW89_MAC_WD_DMA_INTVL_0S	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_0S,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_16US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_16US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_1US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_1US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_1_5US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_1_5US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_256NS	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_256NS,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_2US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_2US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_4US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_4US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_512NS	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_512NS,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_768NS	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_768NS,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_8US	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_8US,$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAC_WD_DMA_INTVL_DEF	mac.h	/^	RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE$/;"	e	enum:rtw89_mac_wd_dma_intvl
RTW89_MAX_ADDR_CAM_NUM	core.h	1854;"	d
RTW89_MAX_BSSID_CAM_NUM	core.h	1855;"	d
RTW89_MAX_CHANNEL_WIDTH	core.h	546;"	d
RTW89_MAX_HW_PORT_NUM	core.h	36;"	d
RTW89_MAX_MAC_ID_NUM	core.h	2372;"	d
RTW89_MAX_PPDU_CNT	core.h	468;"	d
RTW89_MAX_RX_AGG_NUM	core.h	1815;"	d
RTW89_MAX_SEC_CAM_NUM	core.h	1856;"	d
RTW89_MAX_TX_AGG_NUM	core.h	1816;"	d
RTW89_MEXICO	core.h	/^	RTW89_MEXICO	= 10,$/;"	e	enum:rtw89_regulation_type
RTW89_MFW_SIG	fw.h	1227;"	d
RTW89_MGNT	mac.h	/^	RTW89_MGNT = 0,$/;"	e	enum:rtw89_machdr_frame_type
RTW89_MKK	core.h	/^	RTW89_MKK	= 3,$/;"	e	enum:rtw89_regulation_type
RTW89_MK_HT_RATE	fw.h	1221;"	d
RTW89_NA	core.h	/^	RTW89_NA	= 4,$/;"	e	enum:rtw89_regulation_type
RTW89_NCC	core.h	/^	RTW89_NCC	= 7,$/;"	e	enum:rtw89_regulation_type
RTW89_NET_TYPE_AD_HOC	core.h	/^	RTW89_NET_TYPE_AD_HOC		= 1,$/;"	e	enum:rtw89_net_type
RTW89_NET_TYPE_AP_MODE	core.h	/^	RTW89_NET_TYPE_AP_MODE		= 3,$/;"	e	enum:rtw89_net_type
RTW89_NET_TYPE_INFRA	core.h	/^	RTW89_NET_TYPE_INFRA		= 2,$/;"	e	enum:rtw89_net_type
RTW89_NET_TYPE_NO_LINK	core.h	/^	RTW89_NET_TYPE_NO_LINK		= 0,$/;"	e	enum:rtw89_net_type
RTW89_NHM_RPT_NUM	core.h	2659;"	d
RTW89_NHM_TH_NUM	core.h	2657;"	d
RTW89_NONBF	core.h	/^	RTW89_NONBF	= 0,$/;"	e	enum:rtw89_beamforming_type
RTW89_NO_MSK	core.h	/^	RTW89_NO_MSK,$/;"	e	enum:rtw89_msk_sO_el
RTW89_NSS_1	core.h	/^	RTW89_NSS_1		= 0,$/;"	e	enum:rtw89_nss
RTW89_NSS_2	core.h	/^	RTW89_NSS_2		= 1,$/;"	e	enum:rtw89_nss
RTW89_NSS_3	core.h	/^	RTW89_NSS_3		= 2,$/;"	e	enum:rtw89_nss
RTW89_NSS_4	core.h	/^	RTW89_NSS_4		= 3,$/;"	e	enum:rtw89_nss
RTW89_NSS_HEDCM_MAX	core.h	/^	RTW89_NSS_HEDCM_MAX	= RTW89_NSS_2 + 1,$/;"	e	enum:rtw89_nss
RTW89_NSS_MAX	core.h	/^	RTW89_NSS_MAX,$/;"	e	enum:rtw89_nss
RTW89_NTX_NUM	core.h	/^	RTW89_NTX_NUM,$/;"	e	enum:rtw89_ntx
RTW89_NUM_OF_SER_FLAGS	core.h	/^	RTW89_NUM_OF_SER_FLAGS$/;"	e	enum:rtw89_ser_rcvy_step
RTW89_PCIE_ASPM_CTRL	pci.h	332;"	d
RTW89_PCIE_BIT_CFG_RST_MSTATE	pci.h	342;"	d
RTW89_PCIE_BIT_CLK	pci.h	338;"	d
RTW89_PCIE_BIT_L1	pci.h	339;"	d
RTW89_PCIE_BIT_L1SUB	pci.h	336;"	d
RTW89_PCIE_CLK_CTRL	pci.h	340;"	d
RTW89_PCIE_L1_CTRL	pci.h	337;"	d
RTW89_PCIE_PHY_RATE	pci.h	343;"	d
RTW89_PCIE_PHY_RATE_MASK	pci.h	344;"	d
RTW89_PCIE_RST_MSTATE	pci.h	341;"	d
RTW89_PCIE_TIMER_CTRL	pci.h	335;"	d
RTW89_PCI_ADDRINFO_MAX	pci.h	325;"	d
RTW89_PCI_ADDR_HIGH	pci.h	419;"	d
RTW89_PCI_ADDR_LS	pci.h	418;"	d
RTW89_PCI_ADDR_MSDU_LS	pci.h	417;"	d
RTW89_PCI_ADDR_NUM	pci.h	420;"	d
RTW89_PCI_MULTITAG	pci.h	329;"	d
RTW89_PCI_POLL_BDRAM_RST_CNT	pci.h	328;"	d
RTW89_PCI_RPP_MACID	pci.h	436;"	d
RTW89_PCI_RPP_POLLUTED	pci.h	428;"	d
RTW89_PCI_RPP_QSEL	pci.h	435;"	d
RTW89_PCI_RPP_SEQ	pci.h	429;"	d
RTW89_PCI_RPP_TX_STATUS	pci.h	430;"	d
RTW89_PCI_RXBD_FS	pci.h	448;"	d
RTW89_PCI_RXBD_LS	pci.h	449;"	d
RTW89_PCI_RXBD_NUM_MAX	pci.h	322;"	d
RTW89_PCI_RXBD_TAG	pci.h	451;"	d
RTW89_PCI_RXBD_WRITE_SIZE	pci.h	450;"	d
RTW89_PCI_RX_BD	pci.h	/^RTW89_PCI_RX_BD(struct rtw89_pci_rx_ring *rx_ring, u32 idx)$/;"	f
RTW89_PCI_RX_BUF_SIZE	pci.h	326;"	d
RTW89_PCI_RX_SKB_CB	pci.h	/^static inline struct rtw89_pci_rx_info *RTW89_PCI_RX_SKB_CB(struct sk_buff *skb)$/;"	f
RTW89_PCI_TXBD_NUM_MAX	pci.h	321;"	d
RTW89_PCI_TXBD_OPTION_LS	pci.h	400;"	d
RTW89_PCI_TXWD_NUM_MAX	pci.h	323;"	d
RTW89_PCI_TXWD_PAGE_SIZE	pci.h	324;"	d
RTW89_PCI_TXWP_VALID	pci.h	408;"	d
RTW89_PCI_TX_SKB_CB	pci.h	/^static inline struct rtw89_pci_tx_data *RTW89_PCI_TX_SKB_CB(struct sk_buff *skb)$/;"	f
RTW89_PCI_WR_RETRY_CNT	pci.h	38;"	d
RTW89_PHYSTS_IE00_CMN_CCK	txrx.h	/^	RTW89_PHYSTS_IE00_CMN_CCK			= 0,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE01_CMN_OFDM	txrx.h	/^	RTW89_PHYSTS_IE01_CMN_OFDM			= 1,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE02_CMN_EXT_AX	txrx.h	/^	RTW89_PHYSTS_IE02_CMN_EXT_AX			= 2,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE03_CMN_EXT_SEG_1	txrx.h	/^	RTW89_PHYSTS_IE03_CMN_EXT_SEG_1			= 3,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE04_CMN_EXT_PATH_A	txrx.h	/^	RTW89_PHYSTS_IE04_CMN_EXT_PATH_A		= 4,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE05_CMN_EXT_PATH_B	txrx.h	/^	RTW89_PHYSTS_IE05_CMN_EXT_PATH_B		= 5,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE06_CMN_EXT_PATH_C	txrx.h	/^	RTW89_PHYSTS_IE06_CMN_EXT_PATH_C		= 6,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE07_CMN_EXT_PATH_D	txrx.h	/^	RTW89_PHYSTS_IE07_CMN_EXT_PATH_D		= 7,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE08_FTR_CH	txrx.h	/^	RTW89_PHYSTS_IE08_FTR_CH			= 8,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE09_FTR_PLCP_0	txrx.h	/^	RTW89_PHYSTS_IE09_FTR_PLCP_0			= 9,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE10_FTR_PLCP_EXT	txrx.h	/^	RTW89_PHYSTS_IE10_FTR_PLCP_EXT			= 10,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM	txrx.h	/^	RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM		= 11,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE12_MU_EIGEN_INFO	txrx.h	/^	RTW89_PHYSTS_IE12_MU_EIGEN_INFO			= 12,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE13_DL_MU_DEF	txrx.h	/^	RTW89_PHYSTS_IE13_DL_MU_DEF			= 13,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE14_TB_UL_CQI	txrx.h	/^	RTW89_PHYSTS_IE14_TB_UL_CQI			= 14,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE15_TB_UL_DEF	txrx.h	/^	RTW89_PHYSTS_IE15_TB_UL_DEF			= 15,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE16_RSVD16	txrx.h	/^	RTW89_PHYSTS_IE16_RSVD16			= 16,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE17_TB_UL_CTRL	txrx.h	/^	RTW89_PHYSTS_IE17_TB_UL_CTRL			= 17,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN	txrx.h	/^	RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN		= 18,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN	txrx.h	/^	RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN		= 19,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0	txrx.h	/^	RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0	= 20,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1	txrx.h	/^	RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1	= 21,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC	txrx.h	/^	RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC		= 22,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE23_RSVD23	txrx.h	/^	RTW89_PHYSTS_IE23_RSVD23			= 23,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A	txrx.h	/^	RTW89_PHYSTS_IE24_DBG_OFDM_TD_PATH_A		= 24,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B	txrx.h	/^	RTW89_PHYSTS_IE25_DBG_OFDM_TD_PATH_B		= 25,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C	txrx.h	/^	RTW89_PHYSTS_IE26_DBG_OFDM_TD_PATH_C		= 26,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D	txrx.h	/^	RTW89_PHYSTS_IE27_DBG_OFDM_TD_PATH_D		= 27,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE28_DBG_CCK_PATH_A	txrx.h	/^	RTW89_PHYSTS_IE28_DBG_CCK_PATH_A		= 28,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE29_DBG_CCK_PATH_B	txrx.h	/^	RTW89_PHYSTS_IE29_DBG_CCK_PATH_B		= 29,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE30_DBG_CCK_PATH_C	txrx.h	/^	RTW89_PHYSTS_IE30_DBG_CCK_PATH_C		= 30,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE31_DBG_CCK_PATH_D	txrx.h	/^	RTW89_PHYSTS_IE31_DBG_CCK_PATH_D		= 31,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE_MAX	txrx.h	/^	RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHYSTS_IE_NUM	txrx.h	/^	RTW89_PHYSTS_IE_NUM,$/;"	e	enum:rtw89_phy_status_ie_type
RTW89_PHY_0	core.h	/^	RTW89_PHY_0 = 0,$/;"	e	enum:rtw89_phy_idx
RTW89_PHY_1	core.h	/^	RTW89_PHY_1 = 1,$/;"	e	enum:rtw89_phy_idx
RTW89_PHY_ADDR_OFFSET	phy.h	10;"	d
RTW89_PHY_C2H_CLASS_BTC_MAX	phy.h	/^	RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_CLASS_BTC_MIN	phy.h	/^	RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_CLASS_DM	phy.h	/^	RTW89_PHY_C2H_CLASS_DM,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_CLASS_MAX	phy.h	/^	RTW89_PHY_C2H_CLASS_MAX,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_CLASS_RA	phy.h	/^	RTW89_PHY_C2H_CLASS_RA,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_CLASS_RUA	phy.h	/^	RTW89_PHY_C2H_CLASS_RUA,$/;"	e	enum:rtw89_phy_c2h_class
RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT	phy.h	/^	RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,$/;"	e	enum:rtw89_phy_c2h_ra_func
RTW89_PHY_C2H_FUNC_RA_MAX	phy.h	/^	RTW89_PHY_C2H_FUNC_RA_MAX,$/;"	e	enum:rtw89_phy_c2h_ra_func
RTW89_PHY_C2H_FUNC_STS_RPT	phy.h	/^	RTW89_PHY_C2H_FUNC_STS_RPT,$/;"	e	enum:rtw89_phy_c2h_ra_func
RTW89_PHY_C2H_FUNC_TXSTS	phy.h	/^	RTW89_PHY_C2H_FUNC_TXSTS,$/;"	e	enum:rtw89_phy_c2h_ra_func
RTW89_PHY_DCFO_STATE_ENHANCE	core.h	/^	RTW89_PHY_DCFO_STATE_ENHANCE = 1,$/;"	e	enum:rtw89_phy_cfo_status
RTW89_PHY_DCFO_STATE_MAX	core.h	/^	RTW89_PHY_DCFO_STATE_MAX$/;"	e	enum:rtw89_phy_cfo_status
RTW89_PHY_DCFO_STATE_NORMAL	core.h	/^	RTW89_PHY_DCFO_STATE_NORMAL = 0,$/;"	e	enum:rtw89_phy_cfo_status
RTW89_PHY_ENV_MON_CCX_FAIL	phy.h	/^	RTW89_PHY_ENV_MON_CCX_FAIL = 0,$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_ENV_MON_CLM	phy.h	/^	RTW89_PHY_ENV_MON_CLM = BIT(1),$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_ENV_MON_EDCCA_CLM	phy.h	/^	RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_ENV_MON_FAHM	phy.h	/^	RTW89_PHY_ENV_MON_FAHM = BIT(2),$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_ENV_MON_IFS_CLM	phy.h	/^	RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_ENV_MON_NHM	phy.h	/^	RTW89_PHY_ENV_MON_NHM = BIT(0),$/;"	e	enum:rtw89_env_monitor_result_level
RTW89_PHY_MAX	core.h	/^	RTW89_PHY_MAX$/;"	e	enum:rtw89_phy_idx
RTW89_PKT_BASED_AVG_MODE	core.h	/^	RTW89_PKT_BASED_AVG_MODE = 0,$/;"	e	enum:rtw89_multi_cfo_mode
RTW89_PLE_PG_128	mac.h	394;"	d
RTW89_PLE_PG_256	mac.h	395;"	d
RTW89_PLE_PG_64	mac.h	393;"	d
RTW89_PORT_0	core.h	/^	RTW89_PORT_0 = 0,$/;"	e	enum:rtw89_port
RTW89_PORT_1	core.h	/^	RTW89_PORT_1 = 1,$/;"	e	enum:rtw89_port
RTW89_PORT_2	core.h	/^	RTW89_PORT_2 = 2,$/;"	e	enum:rtw89_port
RTW89_PORT_3	core.h	/^	RTW89_PORT_3 = 3,$/;"	e	enum:rtw89_port
RTW89_PORT_4	core.h	/^	RTW89_PORT_4 = 4,$/;"	e	enum:rtw89_port
RTW89_PORT_NUM	core.h	/^	RTW89_PORT_NUM$/;"	e	enum:rtw89_port
RTW89_PPDU_MAC_INFO_SIZE	core.h	1812;"	d
RTW89_PPDU_MAC_INFO_USR_SIZE	core.h	1811;"	d
RTW89_PPDU_MAC_RX_CNT_SIZE	core.h	1813;"	d
RTW89_PPDU_MAX_USR	core.h	1810;"	d
RTW89_PPE_BW_NUM	core.h	549;"	d
RTW89_PRPT_DEST_HOST	reg.h	549;"	d
RTW89_PRPT_DEST_WLCPU	reg.h	550;"	d
RTW89_PS_MODE_CLK_GATED	core.h	/^	RTW89_PS_MODE_CLK_GATED	= 2,$/;"	e	enum:rtw89_ps_mode
RTW89_PS_MODE_NONE	core.h	/^	RTW89_PS_MODE_NONE	= 0,$/;"	e	enum:rtw89_ps_mode
RTW89_PS_MODE_PWR_GATED	core.h	/^	RTW89_PS_MODE_PWR_GATED	= 3,$/;"	e	enum:rtw89_ps_mode
RTW89_PS_MODE_RFOFF	core.h	/^	RTW89_PS_MODE_RFOFF	= 1,$/;"	e	enum:rtw89_ps_mode
RTW89_QTA_DLFW	core.h	/^	RTW89_QTA_DLFW,$/;"	e	enum:rtw89_qta_mode
RTW89_QTA_INVALID	core.h	/^	RTW89_QTA_INVALID,$/;"	e	enum:rtw89_qta_mode
RTW89_QTA_SCC	core.h	/^	RTW89_QTA_SCC,$/;"	e	enum:rtw89_qta_mode
RTW89_R32_DEAD	mac.h	371;"	d
RTW89_R32_EA	mac.h	370;"	d
RTW89_RAC_LV_1	core.h	/^	RTW89_RAC_LV_1 = 1,$/;"	e	enum:rtw89_env_racing_lv
RTW89_RAC_LV_2	core.h	/^	RTW89_RAC_LV_2 = 2,$/;"	e	enum:rtw89_env_racing_lv
RTW89_RAC_LV_3	core.h	/^	RTW89_RAC_LV_3 = 3,$/;"	e	enum:rtw89_env_racing_lv
RTW89_RAC_LV_4	core.h	/^	RTW89_RAC_LV_4 = 4,$/;"	e	enum:rtw89_env_racing_lv
RTW89_RAC_MAX_NUM	core.h	/^	RTW89_RAC_MAX_NUM = 5$/;"	e	enum:rtw89_env_racing_lv
RTW89_RAC_RELEASE	core.h	/^	RTW89_RAC_RELEASE = 0,$/;"	e	enum:rtw89_env_racing_lv
RTW89_RATE_CCK_MAX	core.h	/^	RTW89_RATE_CCK_MAX	= 4,$/;"	e	enum:rtw89_rate_max
RTW89_RATE_HEDCM_MAX	core.h	/^	RTW89_RATE_HEDCM_MAX	= 4, \/* for HEDCM MCS0\/1\/3\/4 *\/$/;"	e	enum:rtw89_rate_max
RTW89_RATE_MCS_MAX	core.h	/^	RTW89_RATE_MCS_MAX	= 12,$/;"	e	enum:rtw89_rate_max
RTW89_RATE_OFDM_MAX	core.h	/^	RTW89_RATE_OFDM_MAX	= 8,$/;"	e	enum:rtw89_rate_max
RTW89_RATE_OFFSET_MAX	core.h	/^	RTW89_RATE_OFFSET_MAX	= 5, \/* for HE(HEDCM)\/VHT\/HT\/OFDM\/CCK offset *\/$/;"	e	enum:rtw89_rate_max
RTW89_RA_MODE_CCK	core.h	/^	RTW89_RA_MODE_CCK = BIT(0),$/;"	e	enum:rtw89_ra_mode
RTW89_RA_MODE_HE	core.h	/^	RTW89_RA_MODE_HE = BIT(4),$/;"	e	enum:rtw89_ra_mode
RTW89_RA_MODE_HT	core.h	/^	RTW89_RA_MODE_HT = BIT(2),$/;"	e	enum:rtw89_ra_mode
RTW89_RA_MODE_OFDM	core.h	/^	RTW89_RA_MODE_OFDM = BIT(1),$/;"	e	enum:rtw89_ra_mode
RTW89_RA_MODE_VHT	core.h	/^	RTW89_RA_MODE_VHT = BIT(3),$/;"	e	enum:rtw89_ra_mode
RTW89_RA_RATE_MASK_HT_MCS	fw.h	1220;"	d
RTW89_RA_RATE_MASK_MCS	fw.h	1219;"	d
RTW89_RA_RATE_MASK_NSS	fw.h	1218;"	d
RTW89_RA_RPT_MODE_HE	core.h	/^	RTW89_RA_RPT_MODE_HE,$/;"	e	enum:rtw89_ra_report_mode
RTW89_RA_RPT_MODE_HT	core.h	/^	RTW89_RA_RPT_MODE_HT,$/;"	e	enum:rtw89_ra_report_mode
RTW89_RA_RPT_MODE_LEGACY	core.h	/^	RTW89_RA_RPT_MODE_LEGACY,$/;"	e	enum:rtw89_ra_report_mode
RTW89_RA_RPT_MODE_VHT	core.h	/^	RTW89_RA_RPT_MODE_VHT,$/;"	e	enum:rtw89_ra_report_mode
RTW89_REGD_NUM	core.h	/^	RTW89_REGD_NUM,$/;"	e	enum:rtw89_regulation_type
RTW89_RFK_F_DELAY	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_DELAY = 4,$/;"	e	enum:rtw89_rfk_flag
RTW89_RFK_F_NUM	rtw8852a_rfk.c	/^static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);$/;"	v
RTW89_RFK_F_NUM	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_NUM,$/;"	e	enum:rtw89_rfk_flag
RTW89_RFK_F_WC	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_WC = 3,$/;"	e	enum:rtw89_rfk_flag
RTW89_RFK_F_WM	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_WM = 1,$/;"	e	enum:rtw89_rfk_flag
RTW89_RFK_F_WRF	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_WRF = 0,$/;"	e	enum:rtw89_rfk_flag
RTW89_RFK_F_WS	rtw8852a_rfk_table.h	/^	RTW89_RFK_F_WS = 2,$/;"	e	enum:rtw89_rfk_flag
RTW89_RPR_MODE_POH	core.h	/^	RTW89_RPR_MODE_POH = 0,$/;"	e	enum:rtw89_host_rpr_mode
RTW89_RPR_MODE_STF	core.h	/^	RTW89_RPR_MODE_STF$/;"	e	enum:rtw89_host_rpr_mode
RTW89_RSSI_RAW_TO_DBM	core.h	35;"	d
RTW89_RS_CCK	core.h	/^	RTW89_RS_CCK,$/;"	e	enum:rtw89_rate_section
RTW89_RS_HEDCM	core.h	/^	RTW89_RS_HEDCM,$/;"	e	enum:rtw89_rate_section
RTW89_RS_LMT_NUM	core.h	/^	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,$/;"	e	enum:rtw89_rate_section
RTW89_RS_MAX	core.h	/^	RTW89_RS_MAX,$/;"	e	enum:rtw89_rate_section
RTW89_RS_MCS	core.h	/^	RTW89_RS_MCS, \/* for HT\/VHT\/HE *\/$/;"	e	enum:rtw89_rate_section
RTW89_RS_OFDM	core.h	/^	RTW89_RS_OFDM,$/;"	e	enum:rtw89_rate_section
RTW89_RS_OFFSET	core.h	/^	RTW89_RS_OFFSET,$/;"	e	enum:rtw89_rate_section
RTW89_RU106	core.h	/^	RTW89_RU106 = 2,$/;"	e	enum:rtw89_ru_bandwidth
RTW89_RU26	core.h	/^	RTW89_RU26 = 0,$/;"	e	enum:rtw89_ru_bandwidth
RTW89_RU52	core.h	/^	RTW89_RU52 = 1,$/;"	e	enum:rtw89_ru_bandwidth
RTW89_RU_NUM	core.h	/^	RTW89_RU_NUM,$/;"	e	enum:rtw89_ru_bandwidth
RTW89_RU_SEC_NUM	core.h	452;"	d
RTW89_RXCH_MAX	txrx.h	/^	RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1$/;"	e	enum:rtw89_rx_channel
RTW89_RXCH_NUM	txrx.h	/^	RTW89_RXCH_NUM,$/;"	e	enum:rtw89_rx_channel
RTW89_RXCH_RPQ	txrx.h	/^	RTW89_RXCH_RPQ	= 1,$/;"	e	enum:rtw89_rx_channel
RTW89_RXCH_RXQ	txrx.h	/^	RTW89_RXCH_RXQ	= 0,$/;"	e	enum:rtw89_rx_channel
RTW89_RX_TAG_MAX	pci.h	495;"	d
RTW89_RX_TYPE_CTRL	core.h	/^	RTW89_RX_TYPE_CTRL = 1,$/;"	e	enum:rtw89_rx_frame_type
RTW89_RX_TYPE_DATA	core.h	/^	RTW89_RX_TYPE_DATA = 2,$/;"	e	enum:rtw89_rx_frame_type
RTW89_RX_TYPE_MGNT	core.h	/^	RTW89_RX_TYPE_MGNT = 0,$/;"	e	enum:rtw89_rx_frame_type
RTW89_RX_TYPE_RSVD	core.h	/^	RTW89_RX_TYPE_RSVD = 3,$/;"	e	enum:rtw89_rx_frame_type
RTW89_SAR_SOURCE_COMMON	core.h	/^	RTW89_SAR_SOURCE_COMMON,$/;"	e	enum:rtw89_sar_sources
RTW89_SAR_SOURCE_NONE	core.h	/^	RTW89_SAR_SOURCE_NONE,$/;"	e	enum:rtw89_sar_sources
RTW89_SAR_SOURCE_NR	core.h	/^	RTW89_SAR_SOURCE_NR,$/;"	e	enum:rtw89_sar_sources
RTW89_SAR_TXPWR_MAC_MAX	sar.h	10;"	d
RTW89_SAR_TXPWR_MAC_MIN	sar.h	11;"	d
RTW89_SBAND_IFTYPES_NR	core.c	2020;"	d	file:
RTW89_SCH_TX_SEL_ALL	core.h	/^	RTW89_SCH_TX_SEL_ALL,$/;"	e	enum:rtw89_sch_tx_sel
RTW89_SCH_TX_SEL_HIQ	core.h	/^	RTW89_SCH_TX_SEL_HIQ,$/;"	e	enum:rtw89_sch_tx_sel
RTW89_SCH_TX_SEL_MACID	core.h	/^	RTW89_SCH_TX_SEL_MACID,$/;"	e	enum:rtw89_sch_tx_sel
RTW89_SCH_TX_SEL_MG0	core.h	/^	RTW89_SCH_TX_SEL_MG0,$/;"	e	enum:rtw89_sch_tx_sel
RTW89_SC_20_LOWER	core.h	/^	RTW89_SC_20_LOWER	= 2,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_20_LOWEST	core.h	/^	RTW89_SC_20_LOWEST	= 4,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_20_UPMOST	core.h	/^	RTW89_SC_20_UPMOST	= 3,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_20_UPPER	core.h	/^	RTW89_SC_20_UPPER	= 1,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_40_LOWER	core.h	/^	RTW89_SC_40_LOWER	= 10,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_40_UPPER	core.h	/^	RTW89_SC_40_UPPER	= 9,$/;"	e	enum:rtw89_sc_offset
RTW89_SC_DONT_CARE	core.h	/^	RTW89_SC_DONT_CARE	= 0,$/;"	e	enum:rtw89_sc_offset
RTW89_SEC_CAM_IN_ADDR_CAM	core.h	1857;"	d
RTW89_SEC_CAM_LEN	cam.h	10;"	d
RTW89_SEC_KEY_TYPE_BIP_CCMP128	core.h	/^	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_CCMP128	core.h	/^	RTW89_SEC_KEY_TYPE_CCMP128	= 6,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_CCMP256	core.h	/^	RTW89_SEC_KEY_TYPE_CCMP256	= 7,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_GCMP128	core.h	/^	RTW89_SEC_KEY_TYPE_GCMP128	= 8,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_GCMP256	core.h	/^	RTW89_SEC_KEY_TYPE_GCMP256	= 9,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_GCMSMS4	core.h	/^	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_NONE	core.h	/^	RTW89_SEC_KEY_TYPE_NONE		= 0,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_TKIP	core.h	/^	RTW89_SEC_KEY_TYPE_TKIP		= 3,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_WAPI	core.h	/^	RTW89_SEC_KEY_TYPE_WAPI		= 4,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_WEP104	core.h	/^	RTW89_SEC_KEY_TYPE_WEP104	= 2,$/;"	e	enum:rtw89_sec_key_type
RTW89_SEC_KEY_TYPE_WEP40	core.h	/^	RTW89_SEC_KEY_TYPE_WEP40	= 1,$/;"	e	enum:rtw89_sec_key_type
RTW89_SELF_ROLE_AP	core.h	/^	RTW89_SELF_ROLE_AP,$/;"	e	enum:rtw89_self_role
RTW89_SELF_ROLE_AP_CLIENT	core.h	/^	RTW89_SELF_ROLE_AP_CLIENT$/;"	e	enum:rtw89_self_role
RTW89_SELF_ROLE_CLIENT	core.h	/^	RTW89_SELF_ROLE_CLIENT,$/;"	e	enum:rtw89_self_role
RTW89_SER_DRV_STOP_RUN	core.h	/^	RTW89_SER_DRV_STOP_RUN,$/;"	e	enum:rtw89_ser_rcvy_step
RTW89_SER_DRV_STOP_RX	core.h	/^	RTW89_SER_DRV_STOP_RX,$/;"	e	enum:rtw89_ser_rcvy_step
RTW89_SER_DRV_STOP_TX	core.h	/^	RTW89_SER_DRV_STOP_TX,$/;"	e	enum:rtw89_ser_rcvy_step
RTW89_SER_HAL_STOP_DMA	core.h	/^	RTW89_SER_HAL_STOP_DMA,$/;"	e	enum:rtw89_ser_rcvy_step
RTW89_SET_EDCA_AC	fw.h	245;"	d
RTW89_SET_EDCA_BAND	fw.h	241;"	d
RTW89_SET_EDCA_PARAM	fw.h	247;"	d
RTW89_SET_EDCA_SEL	fw.h	239;"	d
RTW89_SET_EDCA_WMM	fw.h	243;"	d
RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN	fw.h	1152;"	d
RTW89_SET_FWCMD_CXCTRL_IGNORE_BT	fw.h	1150;"	d
RTW89_SET_FWCMD_CXCTRL_MANUAL	fw.h	1148;"	d
RTW89_SET_FWCMD_CXCTRL_TRACE_STEP	fw.h	1154;"	d
RTW89_SET_FWCMD_CXHDR_LEN	fw.h	1057;"	d
RTW89_SET_FWCMD_CXHDR_TYPE	fw.h	1055;"	d
RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY	fw.h	1068;"	d
RTW89_SET_FWCMD_CXINIT_ANT_ISO	fw.h	1064;"	d
RTW89_SET_FWCMD_CXINIT_ANT_NUM	fw.h	1062;"	d
RTW89_SET_FWCMD_CXINIT_ANT_POS	fw.h	1066;"	d
RTW89_SET_FWCMD_CXINIT_ANT_TYPE	fw.h	1060;"	d
RTW89_SET_FWCMD_CXINIT_BT_ONLY	fw.h	1090;"	d
RTW89_SET_FWCMD_CXINIT_CX_OTHER	fw.h	1088;"	d
RTW89_SET_FWCMD_CXINIT_DBCC_EN	fw.h	1086;"	d
RTW89_SET_FWCMD_CXINIT_MOD_BT_POS	fw.h	1076;"	d
RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO	fw.h	1074;"	d
RTW89_SET_FWCMD_CXINIT_MOD_CV	fw.h	1072;"	d
RTW89_SET_FWCMD_CXINIT_MOD_RFE	fw.h	1070;"	d
RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE	fw.h	1078;"	d
RTW89_SET_FWCMD_CXINIT_WL_GCH	fw.h	1080;"	d
RTW89_SET_FWCMD_CXINIT_WL_INITOK	fw.h	1084;"	d
RTW89_SET_FWCMD_CXINIT_WL_ONLY	fw.h	1082;"	d
RTW89_SET_FWCMD_CXRFK_BAND	fw.h	1163;"	d
RTW89_SET_FWCMD_CXRFK_PATH_MAP	fw.h	1159;"	d
RTW89_SET_FWCMD_CXRFK_PHY_MAP	fw.h	1161;"	d
RTW89_SET_FWCMD_CXRFK_STATE	fw.h	1157;"	d
RTW89_SET_FWCMD_CXRFK_TYPE	fw.h	1165;"	d
RTW89_SET_FWCMD_CXROLE_ACT_BAND	fw.h	1129;"	d
RTW89_SET_FWCMD_CXROLE_ACT_BW	fw.h	1133;"	d
RTW89_SET_FWCMD_CXROLE_ACT_CH	fw.h	1137;"	d
RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS	fw.h	1131;"	d
RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED	fw.h	1121;"	d
RTW89_SET_FWCMD_CXROLE_ACT_NOA	fw.h	1127;"	d
RTW89_SET_FWCMD_CXROLE_ACT_PHY	fw.h	1125;"	d
RTW89_SET_FWCMD_CXROLE_ACT_PID	fw.h	1123;"	d
RTW89_SET_FWCMD_CXROLE_ACT_ROLE	fw.h	1135;"	d
RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL	fw.h	1141;"	d
RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE	fw.h	1145;"	d
RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL	fw.h	1139;"	d
RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE	fw.h	1143;"	d
RTW89_SET_FWCMD_CXROLE_CONNECT_CNT	fw.h	1093;"	d
RTW89_SET_FWCMD_CXROLE_LINK_MODE	fw.h	1095;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC	fw.h	1105;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER	fw.h	1107;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_AP	fw.h	1101;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_MESH	fw.h	1109;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR	fw.h	1111;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_NAN	fw.h	1119;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_NONE	fw.h	1097;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV	fw.h	1113;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC	fw.h	1115;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO	fw.h	1117;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_STA	fw.h	1099;"	d
RTW89_SET_FWCMD_CXROLE_ROLE_VAP	fw.h	1103;"	d
RTW89_SET_FWCMD_RA_BAND_NUM	fw.h	201;"	d
RTW89_SET_FWCMD_RA_BFEE_CSI_CTL	fw.h	199;"	d
RTW89_SET_FWCMD_RA_BW_CAP	fw.h	163;"	d
RTW89_SET_FWCMD_RA_CR_TBL_SEL	fw.h	207;"	d
RTW89_SET_FWCMD_RA_DCM	fw.h	167;"	d
RTW89_SET_FWCMD_RA_ER	fw.h	169;"	d
RTW89_SET_FWCMD_RA_FIXED_CSI_BW	fw.h	215;"	d
RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF	fw.h	213;"	d
RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX	fw.h	209;"	d
RTW89_SET_FWCMD_RA_FIXED_CSI_MODE	fw.h	211;"	d
RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN	fw.h	205;"	d
RTW89_SET_FWCMD_RA_GILTF	fw.h	183;"	d
RTW89_SET_FWCMD_RA_INIT_RATE_LV	fw.h	171;"	d
RTW89_SET_FWCMD_RA_IS_DIS	fw.h	159;"	d
RTW89_SET_FWCMD_RA_LDPC	fw.h	177;"	d
RTW89_SET_FWCMD_RA_MACID	fw.h	165;"	d
RTW89_SET_FWCMD_RA_MASK_0	fw.h	189;"	d
RTW89_SET_FWCMD_RA_MASK_1	fw.h	191;"	d
RTW89_SET_FWCMD_RA_MASK_2	fw.h	193;"	d
RTW89_SET_FWCMD_RA_MASK_3	fw.h	195;"	d
RTW89_SET_FWCMD_RA_MASK_4	fw.h	197;"	d
RTW89_SET_FWCMD_RA_MODE	fw.h	161;"	d
RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN	fw.h	203;"	d
RTW89_SET_FWCMD_RA_SGI	fw.h	175;"	d
RTW89_SET_FWCMD_RA_SS_NUM	fw.h	181;"	d
RTW89_SET_FWCMD_RA_STBC	fw.h	179;"	d
RTW89_SET_FWCMD_RA_UPD_ALL	fw.h	173;"	d
RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK	fw.h	185;"	d
RTW89_SET_FWCMD_RA_UPD_MASK	fw.h	187;"	d
RTW89_SET_FWCMD_SEC_EXT_KEY	fw.h	226;"	d
RTW89_SET_FWCMD_SEC_IDX	fw.h	218;"	d
RTW89_SET_FWCMD_SEC_KEY0	fw.h	230;"	d
RTW89_SET_FWCMD_SEC_KEY1	fw.h	232;"	d
RTW89_SET_FWCMD_SEC_KEY2	fw.h	234;"	d
RTW89_SET_FWCMD_SEC_KEY3	fw.h	236;"	d
RTW89_SET_FWCMD_SEC_LEN	fw.h	222;"	d
RTW89_SET_FWCMD_SEC_OFFSET	fw.h	220;"	d
RTW89_SET_FWCMD_SEC_SPP_MODE	fw.h	228;"	d
RTW89_SET_FWCMD_SEC_TYPE	fw.h	224;"	d
RTW89_SET_H2CREG_HDR_FUNC	fw.h	26;"	d
RTW89_SET_H2CREG_HDR_LEN	fw.h	28;"	d
RTW89_SMA	core.h	/^	RTW89_SMA,$/;"	e	enum:rtw89_msk_sO_el
RTW89_SUBBAND_NR	core.h	/^	RTW89_SUBBAND_NR,$/;"	e	enum:rtw89_subband
RTW89_TFC_DL	core.h	/^	RTW89_TFC_DL,$/;"	e	enum:rtw89_tfc_dir
RTW89_TFC_HIGH	core.h	/^	RTW89_TFC_HIGH,$/;"	e	enum:rtw89_tfc_lv
RTW89_TFC_IDLE	core.h	/^	RTW89_TFC_IDLE,$/;"	e	enum:rtw89_tfc_lv
RTW89_TFC_LOW	core.h	/^	RTW89_TFC_LOW,$/;"	e	enum:rtw89_tfc_lv
RTW89_TFC_MID	core.h	/^	RTW89_TFC_MID,$/;"	e	enum:rtw89_tfc_lv
RTW89_TFC_UL	core.h	/^	RTW89_TFC_UL,$/;"	e	enum:rtw89_tfc_dir
RTW89_TFC_ULTRA_LOW	core.h	/^	RTW89_TFC_ULTRA_LOW,$/;"	e	enum:rtw89_tfc_lv
RTW89_TMA	core.h	/^	RTW89_TMA,$/;"	e	enum:rtw89_msk_sO_el
RTW89_TP_BASED_AVG_MODE	core.h	/^	RTW89_TP_BASED_AVG_MODE = 2,$/;"	e	enum:rtw89_multi_cfo_mode
RTW89_TP_SHIFT	core.h	856;"	d
RTW89_TRACK_WORK_PERIOD	core.h	31;"	d
RTW89_TXCH_ACH0	txrx.h	/^	RTW89_TXCH_ACH0	= 0,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH1	txrx.h	/^	RTW89_TXCH_ACH1	= 1,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH2	txrx.h	/^	RTW89_TXCH_ACH2	= 2,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH3	txrx.h	/^	RTW89_TXCH_ACH3	= 3,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH4	txrx.h	/^	RTW89_TXCH_ACH4	= 4,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH5	txrx.h	/^	RTW89_TXCH_ACH5	= 5,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH6	txrx.h	/^	RTW89_TXCH_ACH6	= 6,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_ACH7	txrx.h	/^	RTW89_TXCH_ACH7	= 7,$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_CH10	txrx.h	/^	RTW89_TXCH_CH10	= 10, \/* MGMT Band 1 *\/$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_CH11	txrx.h	/^	RTW89_TXCH_CH11	= 11, \/* HI Band 1 *\/$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_CH12	txrx.h	/^	RTW89_TXCH_CH12	= 12, \/* FW CMD *\/$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_CH8	txrx.h	/^	RTW89_TXCH_CH8	= 8,  \/* MGMT Band 0 *\/$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_CH9	txrx.h	/^	RTW89_TXCH_CH9	= 9,  \/* HI Band 0 *\/$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_MAX	txrx.h	/^	RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1$/;"	e	enum:rtw89_tx_channel
RTW89_TXCH_NUM	txrx.h	/^	RTW89_TXCH_NUM,$/;"	e	enum:rtw89_tx_channel
RTW89_TXQ_F_AMPDU	core.h	/^	RTW89_TXQ_F_AMPDU		= 0,$/;"	e	enum:rtw89_txq_flags
RTW89_TXQ_F_BLOCK_BA	core.h	/^	RTW89_TXQ_F_BLOCK_BA		= 1,$/;"	e	enum:rtw89_txq_flags
RTW89_TXWD_BODY0_CHANNEL_DMA	txrx.h	30;"	d
RTW89_TXWD_BODY0_FW_DL	txrx.h	29;"	d
RTW89_TXWD_BODY0_HDR_LLC_LEN	txrx.h	31;"	d
RTW89_TXWD_BODY0_HW_AMSDU	txrx.h	33;"	d
RTW89_TXWD_BODY0_MORE_DATA	txrx.h	27;"	d
RTW89_TXWD_BODY0_WD_INFO_EN	txrx.h	28;"	d
RTW89_TXWD_BODY0_WD_PAGE	txrx.h	32;"	d
RTW89_TXWD_BODY0_WP_OFFSET	txrx.h	26;"	d
RTW89_TXWD_BODY1_PAYLOAD_ID	txrx.h	36;"	d
RTW89_TXWD_BODY2_MACID	txrx.h	39;"	d
RTW89_TXWD_BODY2_QSEL	txrx.h	41;"	d
RTW89_TXWD_BODY2_TID_INDICATE	txrx.h	40;"	d
RTW89_TXWD_BODY2_TXPKT_SIZE	txrx.h	42;"	d
RTW89_TXWD_BODY3_AGG_EN	txrx.h	46;"	d
RTW89_TXWD_BODY3_BK	txrx.h	45;"	d
RTW89_TXWD_BODY3_SW_SEQ	txrx.h	47;"	d
RTW89_TXWD_INFO0_DATA_BW	txrx.h	55;"	d
RTW89_TXWD_INFO0_DATA_RATE	txrx.h	57;"	d
RTW89_TXWD_INFO0_DISDATAFB	txrx.h	58;"	d
RTW89_TXWD_INFO0_GI_LTF	txrx.h	56;"	d
RTW89_TXWD_INFO0_USE_RATE	txrx.h	54;"	d
RTW89_TXWD_INFO1_A_CTRL_BSR	txrx.h	62;"	d
RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE	txrx.h	61;"	d
RTW89_TXWD_INFO1_MAX_AGGNUM	txrx.h	63;"	d
RTW89_TXWD_INFO2_AMPDU_DENSITY	txrx.h	66;"	d
RTW89_TXWD_INFO2_SEC_CAM_IDX	txrx.h	69;"	d
RTW89_TXWD_INFO2_SEC_HW_ENC	txrx.h	68;"	d
RTW89_TXWD_INFO2_SEC_TYPE	txrx.h	67;"	d
RTW89_TXWD_INFO4_HW_RTS_EN	txrx.h	75;"	d
RTW89_TXWD_INFO4_RTS_EN	txrx.h	74;"	d
RTW89_TX_DONE	pci.h	431;"	d
RTW89_TX_LIFE_TIME	pci.h	433;"	d
RTW89_TX_MACID_DROP	pci.h	434;"	d
RTW89_TX_QSEL_B0_BCN	txrx.h	/^	RTW89_TX_QSEL_B0_BCN		= 0x10,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B0_HI	txrx.h	/^	RTW89_TX_QSEL_B0_HI		= 0x11,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B0_MGMT	txrx.h	/^	RTW89_TX_QSEL_B0_MGMT		= 0x12,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B0_MGMT_FAST	txrx.h	/^	RTW89_TX_QSEL_B0_MGMT_FAST	= 0x14,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B0_NOPS	txrx.h	/^	RTW89_TX_QSEL_B0_NOPS		= 0x13,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B1_BCN	txrx.h	/^	RTW89_TX_QSEL_B1_BCN		= 0x18,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B1_HI	txrx.h	/^	RTW89_TX_QSEL_B1_HI		= 0x19,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B1_MGMT	txrx.h	/^	RTW89_TX_QSEL_B1_MGMT		= 0x1a,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B1_MGMT_FAST	txrx.h	/^	RTW89_TX_QSEL_B1_MGMT_FAST	= 0x1c,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_B1_NOPS	txrx.h	/^	RTW89_TX_QSEL_B1_NOPS		= 0x1b,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BE_0	txrx.h	/^	RTW89_TX_QSEL_BE_0		= 0x00,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BE_1	txrx.h	/^	RTW89_TX_QSEL_BE_1		= 0x04,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BE_2	txrx.h	/^	RTW89_TX_QSEL_BE_2		= 0x08,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BE_3	txrx.h	/^	RTW89_TX_QSEL_BE_3		= 0x0c,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BK_0	txrx.h	/^	RTW89_TX_QSEL_BK_0		= 0x01,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BK_1	txrx.h	/^	RTW89_TX_QSEL_BK_1		= 0x05,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BK_2	txrx.h	/^	RTW89_TX_QSEL_BK_2		= 0x09,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_BK_3	txrx.h	/^	RTW89_TX_QSEL_BK_3		= 0x0d,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VI_0	txrx.h	/^	RTW89_TX_QSEL_VI_0		= 0x02,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VI_1	txrx.h	/^	RTW89_TX_QSEL_VI_1		= 0x06,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VI_2	txrx.h	/^	RTW89_TX_QSEL_VI_2		= 0x0a,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VI_3	txrx.h	/^	RTW89_TX_QSEL_VI_3		= 0x0e,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VO_0	txrx.h	/^	RTW89_TX_QSEL_VO_0		= 0x03,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VO_1	txrx.h	/^	RTW89_TX_QSEL_VO_1		= 0x07,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VO_2	txrx.h	/^	RTW89_TX_QSEL_VO_2		= 0x0b,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_QSEL_VO_3	txrx.h	/^	RTW89_TX_QSEL_VO_3		= 0x0f,$/;"	e	enum:rtw89_tx_qsel
RTW89_TX_RETRY_LIMIT	pci.h	432;"	d
RTW89_TYPE_MAPPING	core.c	1765;"	d	file:
RTW89_UKRAINE	core.h	/^	RTW89_UKRAINE	= 11,$/;"	e	enum:rtw89_regulation_type
RTW89_VIF_CON_DISCONN	core.h	/^	RTW89_VIF_CON_DISCONN$/;"	e	enum:rtw89_upd_mode
RTW89_VIF_CREATE	core.h	/^	RTW89_VIF_CREATE,$/;"	e	enum:rtw89_upd_mode
RTW89_VIF_INFO_CHANGE	core.h	/^	RTW89_VIF_INFO_CHANGE,$/;"	e	enum:rtw89_upd_mode
RTW89_VIF_REMOVE	core.h	/^	RTW89_VIF_REMOVE,$/;"	e	enum:rtw89_upd_mode
RTW89_VIF_TYPE_CHANGE	core.h	/^	RTW89_VIF_TYPE_CHANGE,$/;"	e	enum:rtw89_upd_mode
RTW89_WDE_PG_128	mac.h	386;"	d
RTW89_WDE_PG_256	mac.h	387;"	d
RTW89_WDE_PG_64	mac.h	385;"	d
RTW89_WIFI_ROLE_ADHOC	core.h	/^	RTW89_WIFI_ROLE_ADHOC,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_ADHOC_MASTER	core.h	/^	RTW89_WIFI_ROLE_ADHOC_MASTER,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_AP	core.h	/^	RTW89_WIFI_ROLE_AP,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_AP_VLAN	core.h	/^	RTW89_WIFI_ROLE_AP_VLAN,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_MESH_POINT	core.h	/^	RTW89_WIFI_ROLE_MESH_POINT,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_MLME_MAX	core.h	/^	RTW89_WIFI_ROLE_MLME_MAX$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_MONITOR	core.h	/^	RTW89_WIFI_ROLE_MONITOR,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_NAN	core.h	/^	RTW89_WIFI_ROLE_NAN,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_NONE	core.h	/^	RTW89_WIFI_ROLE_NONE,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_P2P_CLIENT	core.h	/^	RTW89_WIFI_ROLE_P2P_CLIENT,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_P2P_DEVICE	core.h	/^	RTW89_WIFI_ROLE_P2P_DEVICE,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_P2P_GO	core.h	/^	RTW89_WIFI_ROLE_P2P_GO,$/;"	e	enum:rtw89_wifi_role
RTW89_WIFI_ROLE_STATION	core.h	/^	RTW89_WIFI_ROLE_STATION,$/;"	e	enum:rtw89_wifi_role
RTW89_WW	core.h	/^	RTW89_WW	= 0,$/;"	e	enum:rtw89_regulation_type
RXB_IDX_MAX	phy.h	87;"	d
RXB_IDX_MIN	phy.h	88;"	d
RXDCK_VER_8852A	rtw8852a_rfk.c	1743;"	d	file:
RXPLD_FLTR_CAM_BASE_ADDR	mac.h	231;"	d
RX_FLTR_FRAME_DROP	reg.h	1307;"	d
RX_FLTR_FRAME_TO_HOST	reg.h	1308;"	d
RX_FLTR_FRAME_TO_WLCPU	reg.h	1309;"	d
RX_MAX_LEN_UNIT	mac.c	1804;"	d	file:
R_2P4G_BAND	reg.h	1931;"	d
R_ADC_FIFO	reg.h	1796;"	d
R_ANAPAR	reg.h	1666;"	d
R_ANAPAR_PW15	reg.h	1662;"	d
R_AX_ACH0_BDRAM_CTRL	pci.h	184;"	d
R_AX_ACH0_PAGE_CTRL	reg.h	331;"	d
R_AX_ACH0_PAGE_INFO	reg.h	346;"	d
R_AX_ACH0_TXBD_DESA_H	pci.h	137;"	d
R_AX_ACH0_TXBD_DESA_L	pci.h	136;"	d
R_AX_ACH0_TXBD_IDX	pci.h	120;"	d
R_AX_ACH0_TXBD_NUM	pci.h	170;"	d
R_AX_ACH1_BDRAM_CTRL	pci.h	185;"	d
R_AX_ACH1_PAGE_CTRL	reg.h	332;"	d
R_AX_ACH1_PAGE_INFO	reg.h	347;"	d
R_AX_ACH1_TXBD_DESA_H	pci.h	139;"	d
R_AX_ACH1_TXBD_DESA_L	pci.h	138;"	d
R_AX_ACH1_TXBD_IDX	pci.h	121;"	d
R_AX_ACH1_TXBD_NUM	pci.h	171;"	d
R_AX_ACH2_BDRAM_CTRL	pci.h	186;"	d
R_AX_ACH2_PAGE_CTRL	reg.h	333;"	d
R_AX_ACH2_PAGE_INFO	reg.h	348;"	d
R_AX_ACH2_TXBD_DESA_H	pci.h	141;"	d
R_AX_ACH2_TXBD_DESA_L	pci.h	140;"	d
R_AX_ACH2_TXBD_IDX	pci.h	122;"	d
R_AX_ACH2_TXBD_NUM	pci.h	172;"	d
R_AX_ACH3_BDRAM_CTRL	pci.h	187;"	d
R_AX_ACH3_PAGE_CTRL	reg.h	334;"	d
R_AX_ACH3_PAGE_INFO	reg.h	349;"	d
R_AX_ACH3_TXBD_DESA_H	pci.h	143;"	d
R_AX_ACH3_TXBD_DESA_L	pci.h	142;"	d
R_AX_ACH3_TXBD_IDX	pci.h	123;"	d
R_AX_ACH3_TXBD_NUM	pci.h	173;"	d
R_AX_ACH4_BDRAM_CTRL	pci.h	188;"	d
R_AX_ACH4_PAGE_CTRL	reg.h	335;"	d
R_AX_ACH4_PAGE_INFO	reg.h	350;"	d
R_AX_ACH4_TXBD_DESA_H	pci.h	145;"	d
R_AX_ACH4_TXBD_DESA_L	pci.h	144;"	d
R_AX_ACH4_TXBD_IDX	pci.h	124;"	d
R_AX_ACH4_TXBD_NUM	pci.h	174;"	d
R_AX_ACH5_BDRAM_CTRL	pci.h	189;"	d
R_AX_ACH5_PAGE_CTRL	reg.h	336;"	d
R_AX_ACH5_PAGE_INFO	reg.h	351;"	d
R_AX_ACH5_TXBD_DESA_H	pci.h	147;"	d
R_AX_ACH5_TXBD_DESA_L	pci.h	146;"	d
R_AX_ACH5_TXBD_IDX	pci.h	125;"	d
R_AX_ACH5_TXBD_NUM	pci.h	175;"	d
R_AX_ACH6_BDRAM_CTRL	pci.h	190;"	d
R_AX_ACH6_PAGE_CTRL	reg.h	337;"	d
R_AX_ACH6_PAGE_INFO	reg.h	352;"	d
R_AX_ACH6_TXBD_DESA_H	pci.h	149;"	d
R_AX_ACH6_TXBD_DESA_L	pci.h	148;"	d
R_AX_ACH6_TXBD_IDX	pci.h	126;"	d
R_AX_ACH6_TXBD_NUM	pci.h	176;"	d
R_AX_ACH7_BDRAM_CTRL	pci.h	191;"	d
R_AX_ACH7_PAGE_CTRL	reg.h	338;"	d
R_AX_ACH7_PAGE_INFO	reg.h	353;"	d
R_AX_ACH7_TXBD_DESA_H	pci.h	151;"	d
R_AX_ACH7_TXBD_DESA_L	pci.h	150;"	d
R_AX_ACH7_TXBD_IDX	pci.h	127;"	d
R_AX_ACH7_TXBD_NUM	pci.h	177;"	d
R_AX_ACTION_FWD0	reg.h	541;"	d
R_AX_ADDR_CAM_CTRL	reg.h	1311;"	d
R_AX_ADDR_CAM_CTRL_C1	reg.h	1312;"	d
R_AX_AFE_CTRL1	reg.h	621;"	d
R_AX_AGG_LEN_HT_0	reg.h	973;"	d
R_AX_AGG_LEN_HT_0_C1	reg.h	974;"	d
R_AX_AMPDU_AGG_LIMIT	reg.h	967;"	d
R_AX_BBRPT_CHINFO_ERR_IMR_ISR	reg.h	486;"	d
R_AX_BBRPT_COM_ERR_IMR_ISR	reg.h	485;"	d
R_AX_BBRPT_DFS_ERR_IMR_ISR	reg.h	487;"	d
R_AX_BCNERLYINT_CFG_P0	reg.h	850;"	d
R_AX_BCNERLYINT_CFG_P1	reg.h	851;"	d
R_AX_BCNERLYINT_CFG_P2	reg.h	852;"	d
R_AX_BCNERLYINT_CFG_P3	reg.h	853;"	d
R_AX_BCNERLYINT_CFG_P4	reg.h	854;"	d
R_AX_BCN_AREA_P0	reg.h	842;"	d
R_AX_BCN_AREA_P1	reg.h	843;"	d
R_AX_BCN_AREA_P2	reg.h	844;"	d
R_AX_BCN_AREA_P3	reg.h	845;"	d
R_AX_BCN_AREA_P4	reg.h	846;"	d
R_AX_BCN_CNT_TMR_P0	reg.h	926;"	d
R_AX_BCN_CNT_TMR_P1	reg.h	927;"	d
R_AX_BCN_CNT_TMR_P2	reg.h	928;"	d
R_AX_BCN_CNT_TMR_P3	reg.h	929;"	d
R_AX_BCN_CNT_TMR_P4	reg.h	930;"	d
R_AX_BCN_ERR_CNT_P0	reg.h	888;"	d
R_AX_BCN_ERR_CNT_P1	reg.h	889;"	d
R_AX_BCN_ERR_CNT_P2	reg.h	890;"	d
R_AX_BCN_ERR_CNT_P3	reg.h	891;"	d
R_AX_BCN_ERR_CNT_P4	reg.h	892;"	d
R_AX_BCN_ERR_FLAG_P0	reg.h	898;"	d
R_AX_BCN_ERR_FLAG_P1	reg.h	899;"	d
R_AX_BCN_ERR_FLAG_P2	reg.h	900;"	d
R_AX_BCN_ERR_FLAG_P3	reg.h	901;"	d
R_AX_BCN_ERR_FLAG_P4	reg.h	902;"	d
R_AX_BCN_FORCETX_P0	reg.h	879;"	d
R_AX_BCN_FORCETX_P1	reg.h	880;"	d
R_AX_BCN_FORCETX_P2	reg.h	881;"	d
R_AX_BCN_FORCETX_P3	reg.h	882;"	d
R_AX_BCN_FORCETX_P4	reg.h	883;"	d
R_AX_BCN_SPACE_CFG_P0	reg.h	871;"	d
R_AX_BCN_SPACE_CFG_P1	reg.h	872;"	d
R_AX_BCN_SPACE_CFG_P2	reg.h	873;"	d
R_AX_BCN_SPACE_CFG_P3	reg.h	874;"	d
R_AX_BCN_SPACE_CFG_P4	reg.h	875;"	d
R_AX_BFMEE_RESP_OPTION	reg.h	1202;"	d
R_AX_BFMEE_RESP_OPTION_C1	reg.h	1203;"	d
R_AX_BFMER_CTRL_0	reg.h	1194;"	d
R_AX_BFMER_CTRL_0_C1	reg.h	1195;"	d
R_AX_BOOT_DBG	reg.h	194;"	d
R_AX_BOOT_REASON	reg.h	122;"	d
R_AX_BTC_CFG	reg.h	1416;"	d
R_AX_BTC_FUNC_EN	reg.h	1422;"	d
R_AX_BTC_FUNC_EN_C1	reg.h	1423;"	d
R_AX_BT_COEX_CFG_2	reg.h	1433;"	d
R_AX_BT_COEX_CFG_2_C1	reg.h	1434;"	d
R_AX_BT_COEX_CFG_5	reg.h	1473;"	d
R_AX_BT_COEX_CFG_5_C1	reg.h	1474;"	d
R_AX_BT_PLT	reg.h	1011;"	d
R_AX_BT_PLT_C1	reg.h	1012;"	d
R_AX_BT_STAST_HIGH	reg.h	1454;"	d
R_AX_BT_STAST_LOW	reg.h	1457;"	d
R_AX_C2HREG_CTRL	reg.h	186;"	d
R_AX_C2HREG_DATA0	reg.h	180;"	d
R_AX_C2HREG_DATA1	reg.h	181;"	d
R_AX_C2HREG_DATA2	reg.h	182;"	d
R_AX_C2HREG_DATA3	reg.h	183;"	d
R_AX_CCA_CFG_0	reg.h	720;"	d
R_AX_CCA_CFG_0_C1	reg.h	721;"	d
R_AX_CCA_CONTROL	reg.h	768;"	d
R_AX_CCA_CONTROL_C1	reg.h	769;"	d
R_AX_CH10_BDRAM_CTRL	pci.h	194;"	d
R_AX_CH10_PAGE_CTRL	reg.h	341;"	d
R_AX_CH10_PAGE_INFO	reg.h	356;"	d
R_AX_CH10_TXBD_DESA_H	pci.h	157;"	d
R_AX_CH10_TXBD_DESA_L	pci.h	156;"	d
R_AX_CH10_TXBD_IDX	pci.h	130;"	d
R_AX_CH10_TXBD_NUM	pci.h	180;"	d
R_AX_CH11_BDRAM_CTRL	pci.h	195;"	d
R_AX_CH11_PAGE_CTRL	reg.h	342;"	d
R_AX_CH11_PAGE_INFO	reg.h	357;"	d
R_AX_CH11_TXBD_DESA_H	pci.h	159;"	d
R_AX_CH11_TXBD_DESA_L	pci.h	158;"	d
R_AX_CH11_TXBD_IDX	pci.h	131;"	d
R_AX_CH11_TXBD_NUM	pci.h	181;"	d
R_AX_CH12_BDRAM_CTRL	pci.h	196;"	d
R_AX_CH12_PAGE_INFO	reg.h	358;"	d
R_AX_CH12_TXBD_DESA_H	pci.h	161;"	d
R_AX_CH12_TXBD_DESA_L	pci.h	160;"	d
R_AX_CH12_TXBD_IDX	pci.h	132;"	d
R_AX_CH12_TXBD_NUM	pci.h	182;"	d
R_AX_CH8_BDRAM_CTRL	pci.h	192;"	d
R_AX_CH8_PAGE_CTRL	reg.h	339;"	d
R_AX_CH8_PAGE_INFO	reg.h	354;"	d
R_AX_CH8_TXBD_DESA_H	pci.h	153;"	d
R_AX_CH8_TXBD_DESA_L	pci.h	152;"	d
R_AX_CH8_TXBD_IDX	pci.h	128;"	d
R_AX_CH8_TXBD_NUM	pci.h	178;"	d
R_AX_CH9_BDRAM_CTRL	pci.h	193;"	d
R_AX_CH9_PAGE_CTRL	reg.h	340;"	d
R_AX_CH9_PAGE_INFO	reg.h	355;"	d
R_AX_CH9_TXBD_DESA_H	pci.h	155;"	d
R_AX_CH9_TXBD_DESA_L	pci.h	154;"	d
R_AX_CH9_TXBD_IDX	pci.h	129;"	d
R_AX_CH9_TXBD_NUM	pci.h	179;"	d
R_AX_CH_PAGE_CTRL	reg.h	324;"	d
R_AX_CK_EN	reg.h	651;"	d
R_AX_CK_EN_C1	reg.h	652;"	d
R_AX_CMAC_ERR_ISR	reg.h	685;"	d
R_AX_CMAC_ERR_ISR_C1	reg.h	686;"	d
R_AX_CMAC_FUNC_EN	reg.h	637;"	d
R_AX_CMAC_FUNC_EN_C1	reg.h	638;"	d
R_AX_CMAC_REG_END	reg.h	1485;"	d
R_AX_CMAC_REG_START	reg.h	635;"	d
R_AX_CPUIO_ERR_IMR	reg.h	524;"	d
R_AX_CPUIO_ERR_ISR	reg.h	525;"	d
R_AX_CPU_DISPATCHER_ERR_IMR	reg.h	310;"	d
R_AX_CPU_DISPATCHER_ERR_ISR	reg.h	302;"	d
R_AX_CPWM	reg.h	188;"	d
R_AX_CSR_MODE	reg.h	1440;"	d
R_AX_CSR_MODE_C1	reg.h	1441;"	d
R_AX_CTN_TXEN	reg.h	730;"	d
R_AX_CTN_TXEN_C1	reg.h	731;"	d
R_AX_CTRL_FLTR	reg.h	1301;"	d
R_AX_CTRL_FLTR_C1	reg.h	1302;"	d
R_AX_CUT_AMSDU_CTRL	reg.h	552;"	d
R_AX_DATA_FLTR	reg.h	1305;"	d
R_AX_DATA_FLTR_C1	reg.h	1306;"	d
R_AX_DBGSEL_TRXPTCL	reg.h	1171;"	d
R_AX_DBGSEL_TRXPTCL_C1	reg.h	1172;"	d
R_AX_DBG_CTRL	reg.h	64;"	d
R_AX_DBG_ERR_FLAG	pci.h	297;"	d
R_AX_DBG_FUN_INTF_CTL	reg.h	614;"	d
R_AX_DBG_FUN_INTF_DATA	reg.h	618;"	d
R_AX_DBG_PORT_SEL	reg.h	89;"	d
R_AX_DBI_FLAG	pci.h	27;"	d
R_AX_DBI_RDATA	pci.h	33;"	d
R_AX_DBI_WDATA	pci.h	32;"	d
R_AX_DISPATCHER_GLOBAL_SETTING_0	reg.h	297;"	d
R_AX_DLE_CTRL	reg.h	1062;"	d
R_AX_DLE_CTRL_C1	reg.h	1063;"	d
R_AX_DLE_EMPTY0	reg.h	262;"	d
R_AX_DLK_PROTECT_CTL	reg.h	1257;"	d
R_AX_DLK_PROTECT_CTL_C1	reg.h	1258;"	d
R_AX_DMAC_CLK_EN	reg.h	212;"	d
R_AX_DMAC_ERR_ISR	reg.h	284;"	d
R_AX_DMAC_FUNC_EN	reg.h	196;"	d
R_AX_DTIM_CTRL_P0	reg.h	911;"	d
R_AX_DTIM_CTRL_P1	reg.h	912;"	d
R_AX_DTIM_CTRL_P2	reg.h	913;"	d
R_AX_DTIM_CTRL_P3	reg.h	914;"	d
R_AX_DTIM_CTRL_P4	reg.h	915;"	d
R_AX_EFUSE_CTRL	reg.h	37;"	d
R_AX_EFUSE_CTRL_1	reg.h	25;"	d
R_AX_FILTER_MODEL_ADDR	reg.h	155;"	d
R_AX_GID_POSITION0	reg.h	666;"	d
R_AX_GID_POSITION0_C1	reg.h	667;"	d
R_AX_GID_POSITION1	reg.h	668;"	d
R_AX_GID_POSITION1_C1	reg.h	669;"	d
R_AX_GID_POSITION2	reg.h	670;"	d
R_AX_GID_POSITION2_C1	reg.h	671;"	d
R_AX_GID_POSITION3	reg.h	672;"	d
R_AX_GID_POSITION3_C1	reg.h	673;"	d
R_AX_GID_POSITION_EN0	reg.h	674;"	d
R_AX_GID_POSITION_EN0_C1	reg.h	675;"	d
R_AX_GID_POSITION_EN1	reg.h	676;"	d
R_AX_GID_POSITION_EN1_C1	reg.h	677;"	d
R_AX_GPIO0_7_FUNC_SEL	reg.h	139;"	d
R_AX_GPIO_MUXCFG	reg.h	44;"	d
R_AX_H2CREG_CTRL	reg.h	184;"	d
R_AX_H2CREG_DATA0	reg.h	176;"	d
R_AX_H2CREG_DATA1	reg.h	177;"	d
R_AX_H2CREG_DATA2	reg.h	178;"	d
R_AX_H2CREG_DATA3	reg.h	179;"	d
R_AX_HALT_C2H	reg.h	102;"	d
R_AX_HALT_C2H_CTRL	reg.h	101;"	d
R_AX_HALT_H2C	reg.h	99;"	d
R_AX_HALT_H2C_CTRL	reg.h	98;"	d
R_AX_HCI_FC_CTRL	reg.h	315;"	d
R_AX_HCI_FUNC_EN	reg.h	190;"	d
R_AX_HD0IMR	reg.h	168;"	d
R_AX_HD0ISR	reg.h	173;"	d
R_AX_HIMR0	pci.h	41;"	d
R_AX_HISR0	pci.h	43;"	d
R_AX_HOST_DISPATCHER_ERR_IMR	reg.h	306;"	d
R_AX_HOST_DISPATCHER_ERR_ISR	reg.h	301;"	d
R_AX_HW_RPT_FWD	reg.h	547;"	d
R_AX_IC_PWR_STATE	reg.h	147;"	d
R_AX_INDIR_ACCESS_ENTRY	mac.h	228;"	d
R_AX_INT_MIT_RX	pci.h	286;"	d
R_AX_LA_ERRFLAG	reg.h	488;"	d
R_AX_LBC_WATCHDOG	pci.h	308;"	d
R_AX_LDM	reg.h	125;"	d
R_AX_LTE_CTRL	reg.h	1479;"	d
R_AX_LTE_RDATA	reg.h	1481;"	d
R_AX_LTE_SW_CFG_1	reg.h	1487;"	d
R_AX_LTE_SW_CFG_1_C1	reg.h	1488;"	d
R_AX_LTE_SW_CFG_2	reg.h	1515;"	d
R_AX_LTE_SW_CFG_2_C1	reg.h	1516;"	d
R_AX_LTE_WDATA	reg.h	1480;"	d
R_AX_LTR_ACTIVE_LATENCY	reg.h	257;"	d
R_AX_LTR_CTRL_0	reg.h	243;"	d
R_AX_LTR_CTRL_1	reg.h	251;"	d
R_AX_LTR_IDLE_LATENCY	reg.h	255;"	d
R_AX_MACID_SLEEP_0	reg.h	695;"	d
R_AX_MACID_SLEEP_0_C1	reg.h	696;"	d
R_AX_MACID_SLEEP_1	reg.h	700;"	d
R_AX_MACID_SLEEP_1_C1	reg.h	701;"	d
R_AX_MACID_SLEEP_2	reg.h	705;"	d
R_AX_MACID_SLEEP_2_C1	reg.h	706;"	d
R_AX_MACID_SLEEP_3	reg.h	710;"	d
R_AX_MACID_SLEEP_3_C1	reg.h	711;"	d
R_AX_MACTX_DBG_SEL_CNT	reg.h	1086;"	d
R_AX_MACTX_DBG_SEL_CNT_C1	reg.h	1087;"	d
R_AX_MAC_LOOPBACK	reg.h	1143;"	d
R_AX_MAC_LOOPBACK_C1	reg.h	1144;"	d
R_AX_MBSSID_CTRL	reg.h	947;"	d
R_AX_MBSSID_CTRL_C1	reg.h	948;"	d
R_AX_MBSSID_DROP_0	reg.h	1004;"	d
R_AX_MBSSID_DROP_0_C1	reg.h	1005;"	d
R_AX_MDIO_CFG	pci.h	45;"	d
R_AX_MDIO_RDATA	pci.h	36;"	d
R_AX_MDIO_WDATA	pci.h	35;"	d
R_AX_MGNT_FLTR	reg.h	1303;"	d
R_AX_MGNT_FLTR_C1	reg.h	1304;"	d
R_AX_MPDU_PROC	reg.h	537;"	d
R_AX_MPDU_RX_ERR_IMR	reg.h	556;"	d
R_AX_MPDU_RX_ERR_ISR	reg.h	555;"	d
R_AX_MPDU_TX_ERR_IMR	reg.h	535;"	d
R_AX_MPDU_TX_ERR_ISR	reg.h	534;"	d
R_AX_MUEDCA_BE_PARAM_0	reg.h	749;"	d
R_AX_MUEDCA_BE_PARAM_0_C1	reg.h	750;"	d
R_AX_MUEDCA_BK_PARAM_0	reg.h	755;"	d
R_AX_MUEDCA_BK_PARAM_0_C1	reg.h	756;"	d
R_AX_MUEDCA_EN	reg.h	762;"	d
R_AX_MUEDCA_EN_C1	reg.h	763;"	d
R_AX_MUEDCA_VI_PARAM_0	reg.h	757;"	d
R_AX_MUEDCA_VI_PARAM_0_C1	reg.h	758;"	d
R_AX_MUEDCA_VO_PARAM_0	reg.h	759;"	d
R_AX_MUEDCA_VO_PARAM_0_C1	reg.h	760;"	d
R_AX_OTHER_DISPATCHER_ERR_IMR	reg.h	313;"	d
R_AX_OTHER_DISPATCHER_ERR_ISR	reg.h	300;"	d
R_AX_PCIE_DBG_CTRL	reg.h	157;"	d
R_AX_PCIE_DMA_BUSY1	pci.h	268;"	d
R_AX_PCIE_DMA_BUSY2	pci.h	274;"	d
R_AX_PCIE_DMA_STOP1	pci.h	221;"	d
R_AX_PCIE_DMA_STOP2	pci.h	239;"	d
R_AX_PCIE_EXP_CTRL	pci.h	313;"	d
R_AX_PCIE_HIMR00	pci.h	51;"	d
R_AX_PCIE_HIMR10	pci.h	107;"	d
R_AX_PCIE_HISR00	pci.h	79;"	d
R_AX_PCIE_HISR10	pci.h	112;"	d
R_AX_PCIE_HRPWM	reg.h	111;"	d
R_AX_PCIE_INIT_CFG1	pci.h	201;"	d
R_AX_PCIE_INIT_CFG2	pci.h	279;"	d
R_AX_PCIE_PS_CTRL	pci.h	283;"	d
R_AX_PCIE_RX_PREF_ADV	pci.h	318;"	d
R_AX_PHYINFO_ERR_IMR	reg.h	1175;"	d
R_AX_PHYINFO_ERR_IMR_C1	reg.h	1176;"	d
R_AX_PHYINFO_ERR_ISR	reg.h	1191;"	d
R_AX_PHYINFO_ERR_ISR_C1	reg.h	1192;"	d
R_AX_PHYREG_SET	reg.h	165;"	d
R_AX_PKTIN_ERR_IMR	reg.h	531;"	d
R_AX_PKTIN_ERR_ISR	reg.h	532;"	d
R_AX_PKTIN_SETTING	reg.h	529;"	d
R_AX_PLATFORM_ENABLE	reg.h	78;"	d
R_AX_PLCP_HDR_FLTR	reg.h	1262;"	d
R_AX_PLCP_HDR_FLTR_C1	reg.h	1263;"	d
R_AX_PLE_DBG_FUN_INTF_CTL	reg.h	452;"	d
R_AX_PLE_DBG_FUN_INTF_DATA	reg.h	456;"	d
R_AX_PLE_ERR_FLAG_CFG	reg.h	426;"	d
R_AX_PLE_ERR_FLAG_ISR	reg.h	431;"	d
R_AX_PLE_ERR_IMR	reg.h	428;"	d
R_AX_PLE_INI_STATUS	reg.h	448;"	d
R_AX_PLE_PKTBUF_CFG	reg.h	422;"	d
R_AX_PLE_QTA0_CFG	reg.h	434;"	d
R_AX_PLE_QTA10_CFG	reg.h	446;"	d
R_AX_PLE_QTA1_CFG	reg.h	435;"	d
R_AX_PLE_QTA2_CFG	reg.h	436;"	d
R_AX_PLE_QTA3_CFG	reg.h	437;"	d
R_AX_PLE_QTA4_CFG	reg.h	438;"	d
R_AX_PLE_QTA5_CFG	reg.h	439;"	d
R_AX_PLE_QTA6_CFG	reg.h	440;"	d
R_AX_PLE_QTA7_CFG	reg.h	443;"	d
R_AX_PLE_QTA8_CFG	reg.h	444;"	d
R_AX_PLE_QTA9_CFG	reg.h	445;"	d
R_AX_PL_BUF_REQ	reg.h	491;"	d
R_AX_PL_BUF_STATUS	reg.h	497;"	d
R_AX_PL_CPUQ_OP_0	reg.h	502;"	d
R_AX_PL_CPUQ_OP_1	reg.h	509;"	d
R_AX_PL_CPUQ_OP_2	reg.h	516;"	d
R_AX_PL_CPUQ_OP_STATUS	reg.h	521;"	d
R_AX_PORT_CFG_P0	reg.h	812;"	d
R_AX_PORT_CFG_P1	reg.h	813;"	d
R_AX_PORT_CFG_P2	reg.h	814;"	d
R_AX_PORT_CFG_P3	reg.h	815;"	d
R_AX_PORT_CFG_P4	reg.h	816;"	d
R_AX_PPDU_STAT	reg.h	1324;"	d
R_AX_PPDU_STAT_C1	reg.h	1325;"	d
R_AX_PPWRBIT_SETTING	reg.h	1083;"	d
R_AX_PPWRBIT_SETTING_C1	reg.h	1084;"	d
R_AX_PREBKF_CFG_0	reg.h	716;"	d
R_AX_PREBKF_CFG_0_C1	reg.h	717;"	d
R_AX_PTCL_BSS_COLOR_0	reg.h	1025;"	d
R_AX_PTCL_BSS_COLOR_0_C1	reg.h	1026;"	d
R_AX_PTCL_BSS_COLOR_1	reg.h	1032;"	d
R_AX_PTCL_BSS_COLOR_1_C1	reg.h	1033;"	d
R_AX_PTCL_DBG	reg.h	1057;"	d
R_AX_PTCL_DBG_C1	reg.h	1058;"	d
R_AX_PTCL_DBG_INFO	reg.h	1054;"	d
R_AX_PTCL_DBG_INFO_C1	reg.h	1055;"	d
R_AX_PTCL_FSM_MON	reg.h	1045;"	d
R_AX_PTCL_FSM_MON_C1	reg.h	1046;"	d
R_AX_PTCL_IMR0	reg.h	1036;"	d
R_AX_PTCL_IMR0_C1	reg.h	1037;"	d
R_AX_PTCL_ISR0	reg.h	1041;"	d
R_AX_PTCL_ISR0_C1	reg.h	1042;"	d
R_AX_PTCL_TX_CTN_SEL	reg.h	1050;"	d
R_AX_PTCL_TX_CTN_SEL_C1	reg.h	1051;"	d
R_AX_PUB_PAGE_CTRL1	reg.h	364;"	d
R_AX_PUB_PAGE_CTRL2	reg.h	368;"	d
R_AX_PUB_PAGE_INFO1	reg.h	371;"	d
R_AX_PUB_PAGE_INFO2	reg.h	375;"	d
R_AX_PUB_PAGE_INFO3	reg.h	360;"	d
R_AX_PWR_BY_RATE	reg.h	1398;"	d
R_AX_PWR_BY_RATE_MAX	reg.h	1399;"	d
R_AX_PWR_BY_RATE_TABLE0	reg.h	1396;"	d
R_AX_PWR_BY_RATE_TABLE10	reg.h	1397;"	d
R_AX_PWR_COEXT_CTRL	reg.h	1382;"	d
R_AX_PWR_LMT	reg.h	1402;"	d
R_AX_PWR_LMT_MAX	reg.h	1403;"	d
R_AX_PWR_LMT_TABLE0	reg.h	1400;"	d
R_AX_PWR_LMT_TABLE19	reg.h	1401;"	d
R_AX_PWR_MACID_LMT_TABLE0	reg.h	1408;"	d
R_AX_PWR_MACID_LMT_TABLE127	reg.h	1409;"	d
R_AX_PWR_RATE_CTRL	reg.h	1376;"	d
R_AX_PWR_RATE_CTRL_C1	reg.h	1377;"	d
R_AX_PWR_RATE_OFST_CTRL	reg.h	1381;"	d
R_AX_PWR_RU_LMT	reg.h	1406;"	d
R_AX_PWR_RU_LMT_MAX	reg.h	1407;"	d
R_AX_PWR_RU_LMT_TABLE0	reg.h	1404;"	d
R_AX_PWR_RU_LMT_TABLE11	reg.h	1405;"	d
R_AX_PWR_UL_CTRL0	reg.h	1386;"	d
R_AX_PWR_UL_CTRL2	reg.h	1387;"	d
R_AX_PWR_UL_TB_1T	reg.h	1392;"	d
R_AX_PWR_UL_TB_2T	reg.h	1394;"	d
R_AX_PWR_UL_TB_CTRL	reg.h	1390;"	d
R_AX_RCR	reg.h	1251;"	d
R_AX_RCR_C1	reg.h	1252;"	d
R_AX_RESPBA_CAM_CTRL	reg.h	1320;"	d
R_AX_RESPBA_CAM_CTRL_C1	reg.h	1321;"	d
R_AX_RLSRPT0_CFG0	reg.h	463;"	d
R_AX_RLSRPT0_CFG1	reg.h	469;"	d
R_AX_RMAC_ERR_ISR	reg.h	1346;"	d
R_AX_RMAC_ERR_ISR_C1	reg.h	1347;"	d
R_AX_RMAC_PLCP_MON	reg.h	1366;"	d
R_AX_RMAC_PLCP_MON_C1	reg.h	1367;"	d
R_AX_RPQ_RXBD_DESA_H	pci.h	165;"	d
R_AX_RPQ_RXBD_DESA_L	pci.h	164;"	d
R_AX_RPQ_RXBD_IDX	pci.h	119;"	d
R_AX_RPQ_RXBD_NUM	pci.h	169;"	d
R_AX_RPWM	reg.h	110;"	d
R_AX_RSP_CHK_SIG	reg.h	1108;"	d
R_AX_RSP_CHK_SIG_C1	reg.h	1109;"	d
R_AX_RSV_CTRL	reg.h	21;"	d
R_AX_RXBD_RWPTR_CLR	pci.h	258;"	d
R_AX_RXDMA_ADDR_H	pci.h	219;"	d
R_AX_RXDMA_PKT_INFO_0	reg.h	1066;"	d
R_AX_RXDMA_PKT_INFO_1	reg.h	1067;"	d
R_AX_RXDMA_PKT_INFO_2	reg.h	1068;"	d
R_AX_RXQ_RXBD_DESA_H	pci.h	163;"	d
R_AX_RXQ_RXBD_DESA_L	pci.h	162;"	d
R_AX_RXQ_RXBD_IDX	pci.h	118;"	d
R_AX_RXQ_RXBD_NUM	pci.h	168;"	d
R_AX_RXTRIG_TEST_USER_2	reg.h	1147;"	d
R_AX_RXTRIG_TEST_USER_2_C1	reg.h	1148;"	d
R_AX_RX_DEBUG_SELECT	reg.h	1372;"	d
R_AX_RX_DEBUG_SELECT_C1	reg.h	1373;"	d
R_AX_RX_FLTR_OPT	reg.h	1273;"	d
R_AX_RX_FLTR_OPT_C1	reg.h	1274;"	d
R_AX_RX_SR_CTRL	reg.h	1334;"	d
R_AX_RX_SR_CTRL_C1	reg.h	1335;"	d
R_AX_RX_STATE_MONITOR	reg.h	1338;"	d
R_AX_RX_STATE_MONITOR_C1	reg.h	1339;"	d
R_AX_SCHEDULE_ERR_IMR	reg.h	794;"	d
R_AX_SCHEDULE_ERR_IMR_C1	reg.h	795;"	d
R_AX_SCHEDULE_ERR_ISR	reg.h	799;"	d
R_AX_SCHEDULE_ERR_ISR_C1	reg.h	800;"	d
R_AX_SCH_DBG	reg.h	808;"	d
R_AX_SCH_DBG_C1	reg.h	809;"	d
R_AX_SCH_DBG_SEL	reg.h	802;"	d
R_AX_SCH_DBG_SEL_C1	reg.h	803;"	d
R_AX_SCOREBOARD	reg.h	81;"	d
R_AX_SEC_CAM_ACCESS	reg.h	574;"	d
R_AX_SEC_CAM_RDATA	reg.h	575;"	d
R_AX_SEC_CAM_WDATA	reg.h	576;"	d
R_AX_SEC_DEBUG	reg.h	577;"	d
R_AX_SEC_ENG_CTRL	reg.h	558;"	d
R_AX_SEC_ERR_IMR_ISR	reg.h	527;"	d
R_AX_SEC_MPDU_PROC	reg.h	570;"	d
R_AX_SEC_RX_DEBUG	reg.h	579;"	d
R_AX_SEC_TRX_BLK_CNT	reg.h	581;"	d
R_AX_SEC_TRX_PKT_CNT	reg.h	580;"	d
R_AX_SEC_TX_DEBUG	reg.h	578;"	d
R_AX_SER_DBG_INFO	reg.h	259;"	d
R_AX_SIFS_SETTING	reg.h	980;"	d
R_AX_SIFS_SETTING_C1	reg.h	981;"	d
R_AX_SPSLDO_ON_CTRL0	reg.h	34;"	d
R_AX_SS_CTRL	reg.h	583;"	d
R_AX_SS_MACID_PAUSE_0	reg.h	588;"	d
R_AX_SS_MACID_PAUSE_1	reg.h	592;"	d
R_AX_SS_MACID_PAUSE_2	reg.h	596;"	d
R_AX_SS_MACID_PAUSE_3	reg.h	600;"	d
R_AX_STA_SCHEDULER_ERR_IMR	reg.h	604;"	d
R_AX_STA_SCHEDULER_ERR_ISR	reg.h	605;"	d
R_AX_SYS_CFG1	reg.h	92;"	d
R_AX_SYS_CLK_CTRL	reg.h	18;"	d
R_AX_SYS_FUNC_EN	reg.h	11;"	d
R_AX_SYS_ISO_CTRL_EXTEND	reg.h	629;"	d
R_AX_SYS_PW_CTRL	reg.h	15;"	d
R_AX_SYS_SDIO_CTRL	reg.h	72;"	d
R_AX_SYS_STATUS1	reg.h	95;"	d
R_AX_SYS_WL_EFUSE_CTRL	reg.h	8;"	d
R_AX_TBTTERLYINT_CFG_P0	reg.h	857;"	d
R_AX_TBTTERLYINT_CFG_P1	reg.h	858;"	d
R_AX_TBTTERLYINT_CFG_P2	reg.h	859;"	d
R_AX_TBTTERLYINT_CFG_P3	reg.h	860;"	d
R_AX_TBTTERLYINT_CFG_P4	reg.h	861;"	d
R_AX_TBTT_AGG_P0	reg.h	864;"	d
R_AX_TBTT_AGG_P1	reg.h	865;"	d
R_AX_TBTT_AGG_P2	reg.h	866;"	d
R_AX_TBTT_AGG_P3	reg.h	867;"	d
R_AX_TBTT_AGG_P4	reg.h	868;"	d
R_AX_TBTT_PROHIB_P0	reg.h	834;"	d
R_AX_TBTT_PROHIB_P1	reg.h	835;"	d
R_AX_TBTT_PROHIB_P2	reg.h	836;"	d
R_AX_TBTT_PROHIB_P3	reg.h	837;"	d
R_AX_TBTT_PROHIB_P4	reg.h	838;"	d
R_AX_TBTT_SHIFT_P0	reg.h	919;"	d
R_AX_TBTT_SHIFT_P1	reg.h	920;"	d
R_AX_TBTT_SHIFT_P2	reg.h	921;"	d
R_AX_TBTT_SHIFT_P3	reg.h	922;"	d
R_AX_TBTT_SHIFT_P4	reg.h	923;"	d
R_AX_TCR1	reg.h	1070;"	d
R_AX_TCR1_C1	reg.h	1071;"	d
R_AX_TDMA_MODE	reg.h	1461;"	d
R_AX_TDMA_MODE_C1	reg.h	1462;"	d
R_AX_TF_FWD	reg.h	544;"	d
R_AX_TMAC_ERR_IMR_ISR	reg.h	1168;"	d
R_AX_TMAC_ERR_IMR_ISR_C1	reg.h	1169;"	d
R_AX_TRXPTCL_RESP_0	reg.h	1121;"	d
R_AX_TRXPTCL_RESP_0_C1	reg.h	1122;"	d
R_AX_TRXPTCL_RESP_CSI_CTRL_0	reg.h	1214;"	d
R_AX_TRXPTCL_RESP_CSI_CTRL_0_C1	reg.h	1215;"	d
R_AX_TRXPTCL_RESP_CSI_CTRL_1	reg.h	1216;"	d
R_AX_TRXPTCL_RESP_CSI_CTRL_1_C1	reg.h	1217;"	d
R_AX_TRXPTCL_RESP_CSI_RATE	reg.h	1242;"	d
R_AX_TRXPTCL_RESP_CSI_RATE_C1	reg.h	1243;"	d
R_AX_TRXPTCL_RESP_CSI_RRSC	reg.h	1238;"	d
R_AX_TRXPTCL_RESP_CSI_RRSC_C1	reg.h	1239;"	d
R_AX_TSFTR_HIGH_P0	reg.h	940;"	d
R_AX_TSFTR_HIGH_P1	reg.h	941;"	d
R_AX_TSFTR_HIGH_P2	reg.h	942;"	d
R_AX_TSFTR_HIGH_P3	reg.h	943;"	d
R_AX_TSFTR_HIGH_P4	reg.h	944;"	d
R_AX_TSFTR_LOW_P0	reg.h	933;"	d
R_AX_TSFTR_LOW_P1	reg.h	934;"	d
R_AX_TSFTR_LOW_P2	reg.h	935;"	d
R_AX_TSFTR_LOW_P3	reg.h	936;"	d
R_AX_TSFTR_LOW_P4	reg.h	937;"	d
R_AX_TXBD_RWPTR_CLR1	pci.h	244;"	d
R_AX_TXBD_RWPTR_CLR2	pci.h	263;"	d
R_AX_TXCNT	reg.h	998;"	d
R_AX_TXCNT_C1	reg.h	999;"	d
R_AX_TXDMA_ADDR_H	pci.h	218;"	d
R_AX_TXPKTCTL_ERR_IMR_ISR	reg.h	607;"	d
R_AX_TXPKTCTL_ERR_IMR_ISR_B1	reg.h	608;"	d
R_AX_TXPWR_IMR	reg.h	1411;"	d
R_AX_TXPWR_IMR_C1	reg.h	1412;"	d
R_AX_TXPWR_ISR	reg.h	1413;"	d
R_AX_TXPWR_ISR_C1	reg.h	1414;"	d
R_AX_TXRATE_CHK	reg.h	990;"	d
R_AX_TXRATE_CHK_C1	reg.h	991;"	d
R_AX_TX_ADDRESS_INFO_MODE_SETTING	reg.h	303;"	d
R_AX_TX_SUB_CARRIER_VALUE	reg.h	679;"	d
R_AX_TX_SUB_CARRIER_VALUE_C1	reg.h	680;"	d
R_AX_UDM0	reg.h	128;"	d
R_AX_UDM1	reg.h	129;"	d
R_AX_UDM2	reg.h	130;"	d
R_AX_UDM3	reg.h	131;"	d
R_AX_WCPU_FW_CTRL	reg.h	104;"	d
R_AX_WDE_DBG_FUN_INTF_CTL	reg.h	415;"	d
R_AX_WDE_DBG_FUN_INTF_DATA	reg.h	419;"	d
R_AX_WDE_ERR_FLAG_CFG	reg.h	392;"	d
R_AX_WDE_ERR_IMR	reg.h	393;"	d
R_AX_WDE_ERR_ISR	reg.h	394;"	d
R_AX_WDE_INI_STATUS	reg.h	411;"	d
R_AX_WDE_PKTBUF_CFG	reg.h	388;"	d
R_AX_WDE_QTA0_CFG	reg.h	398;"	d
R_AX_WDE_QTA1_CFG	reg.h	399;"	d
R_AX_WDE_QTA2_CFG	reg.h	400;"	d
R_AX_WDE_QTA3_CFG	reg.h	401;"	d
R_AX_WDE_QTA4_CFG	reg.h	402;"	d
R_AX_WDRLS_CFG	reg.h	459;"	d
R_AX_WDRLS_ERR_IMR	reg.h	473;"	d
R_AX_WDRLS_ERR_ISR	reg.h	483;"	d
R_AX_WD_BUF_REQ	reg.h	490;"	d
R_AX_WD_BUF_STATUS	reg.h	496;"	d
R_AX_WD_CPUQ_OP_0	reg.h	501;"	d
R_AX_WD_CPUQ_OP_1	reg.h	508;"	d
R_AX_WD_CPUQ_OP_2	reg.h	515;"	d
R_AX_WD_CPUQ_OP_STATUS	reg.h	520;"	d
R_AX_WLRF_CTRL	reg.h	141;"	d
R_AX_WL_PRI_MSK	reg.h	1419;"	d
R_AX_WMAC_RFMOD	reg.h	662;"	d
R_AX_WMAC_RFMOD_C1	reg.h	663;"	d
R_AX_WMAC_TX_CTRL_DEBUG	reg.h	1096;"	d
R_AX_WMAC_TX_CTRL_DEBUG_C1	reg.h	1097;"	d
R_AX_WMAC_TX_INFO0_DEBUG	reg.h	1100;"	d
R_AX_WMAC_TX_INFO0_DEBUG_C1	reg.h	1101;"	d
R_AX_WMAC_TX_INFO1_DEBUG	reg.h	1104;"	d
R_AX_WMAC_TX_INFO1_DEBUG_C1	reg.h	1105;"	d
R_AX_WMAC_TX_TF_INFO_0	reg.h	1156;"	d
R_AX_WMAC_TX_TF_INFO_0_C1	reg.h	1157;"	d
R_AX_WMAC_TX_TF_INFO_1	reg.h	1160;"	d
R_AX_WMAC_TX_TF_INFO_1_C1	reg.h	1161;"	d
R_AX_WMAC_TX_TF_INFO_2	reg.h	1164;"	d
R_AX_WMAC_TX_TF_INFO_2_C1	reg.h	1165;"	d
R_AX_WP_PAGE_CTRL1	reg.h	378;"	d
R_AX_WP_PAGE_CTRL2	reg.h	382;"	d
R_AX_WP_PAGE_INFO1	reg.h	385;"	d
R_AX_XTAL_ON_CTRL0	reg.h	133;"	d
R_BANDEDGE	reg.h	1858;"	d
R_BRK_ASYNC_RST_EN_1	reg.h	1735;"	d
R_BRK_ASYNC_RST_EN_2	reg.h	1736;"	d
R_BRK_ASYNC_RST_EN_3	reg.h	1737;"	d
R_BSS_CLR_MAP	reg.h	1845;"	d
R_BTC_BREAK_TABLE	reg.h	1427;"	d
R_BTC_BT_COEX_MSK_TABLE	reg.h	1430;"	d
R_CCX	reg.h	1698;"	d
R_CFIR_LUT	reg.h	2104;"	d
R_CFIR_MAP	reg.h	2103;"	d
R_CFIR_SYS	reg.h	2085;"	d
R_CFO_COMP_SEG0_CTRL	reg.h	1754;"	d
R_CFO_COMP_SEG0_H	reg.h	1753;"	d
R_CFO_COMP_SEG0_L	reg.h	1752;"	d
R_CFO_COMP_SEG1_CTRL	reg.h	1941;"	d
R_CFO_COMP_SEG1_H	reg.h	1940;"	d
R_CFO_COMP_SEG1_L	reg.h	1939;"	d
R_CFO_TRK0	reg.h	1849;"	d
R_CFO_TRK1	reg.h	1850;"	d
R_CHBW_MOD	reg.h	1936;"	d
R_COEF_SEL	reg.h	2082;"	d
R_DBG32_D	reg.h	1755;"	d
R_DCFO	reg.h	1839;"	d
R_DCFO_COMP_S0	reg.h	1852;"	d
R_DCFO_OPT	reg.h	1856;"	d
R_DCFO_WEIGHT	reg.h	1854;"	d
R_DPD_BND	reg.h	2111;"	d
R_DPD_CH0	reg.h	2110;"	d
R_DPD_CH0A	reg.h	2112;"	d
R_DPD_COM	reg.h	2115;"	d
R_DPD_OFT_ADDR	reg.h	1947;"	d
R_DPD_OFT_EN	reg.h	1945;"	d
R_DPD_V1	reg.h	2109;"	d
R_DPK_CFG	reg.h	2061;"	d
R_DPK_CFG2	reg.h	2063;"	d
R_DPK_CFG3	reg.h	2065;"	d
R_DPK_CTL	reg.h	2059;"	d
R_DPK_TRK	reg.h	2073;"	d
R_FC0_BW	reg.h	1933;"	d
R_GAPK	reg.h	2070;"	d
R_IFSCNT	reg.h	1783;"	d
R_IFS_AVG_H	reg.h	1774;"	d
R_IFS_AVG_L	reg.h	1771;"	d
R_IFS_CCA_H	reg.h	1780;"	d
R_IFS_CCA_L	reg.h	1777;"	d
R_IFS_CLM_CCA	reg.h	1760;"	d
R_IFS_CLM_FA	reg.h	1763;"	d
R_IFS_CLM_TX_CNT	reg.h	1757;"	d
R_IFS_COUNTER	reg.h	1703;"	d
R_IFS_HIS	reg.h	1766;"	d
R_IFS_T1	reg.h	1708;"	d
R_IFS_T2	reg.h	1712;"	d
R_IFS_T3	reg.h	1716;"	d
R_IFS_T4	reg.h	1720;"	d
R_IOQ_IQK_DPK	reg.h	1726;"	d
R_IQKCH	reg.h	2151;"	d
R_IQKINF	reg.h	2142;"	d
R_IQKINF2	reg.h	2155;"	d
R_IQK_CFG	reg.h	2045;"	d
R_IQK_COM	reg.h	2035;"	d
R_IQK_DIF	reg.h	2036;"	d
R_IQK_DIF1	reg.h	2038;"	d
R_IQK_DIF2	reg.h	2040;"	d
R_IQK_DIF4	reg.h	2042;"	d
R_IQK_RES	reg.h	2086;"	d
R_KIP	reg.h	2095;"	d
R_KIP_CLK	reg.h	2055;"	d
R_KIP_IQP	reg.h	2116;"	d
R_KIP_RPT	reg.h	2118;"	d
R_KIP_RPT1	reg.h	2067;"	d
R_KIP_SYSCFG	reg.h	2054;"	d
R_KPATH_CFG	reg.h	2066;"	d
R_LDL_NORM	reg.h	2056;"	d
R_LOAD_COEF	reg.h	2121;"	d
R_MAC_SEL	reg.h	1686;"	d
R_MDPK_RX_DCK	reg.h	2052;"	d
R_MDPK_SYNC	reg.h	2049;"	d
R_NCTL_CFG	reg.h	2028;"	d
R_NCTL_N1	reg.h	2032;"	d
R_NCTL_N2	reg.h	2034;"	d
R_NCTL_RPT	reg.h	2030;"	d
R_NCTL_RW	reg.h	2053;"	d
R_NDP_BRK0	reg.h	1732;"	d
R_NDP_BRK1	reg.h	1733;"	d
R_P0_EN_SOUND_WO_NDP	reg.h	1728;"	d
R_P0_NBIIDX	reg.h	1908;"	d
R_P0_NRBW	reg.h	1742;"	d
R_P0_RFCTM	reg.h	1959;"	d
R_P0_RFCTM_RDY	reg.h	1961;"	d
R_P0_RXCK	reg.h	1738;"	d
R_P0_TMETER	reg.h	1949;"	d
R_P0_TSSI_AVG	reg.h	1957;"	d
R_P0_TSSI_BASE	reg.h	1972;"	d
R_P0_TSSI_MV_AVG	reg.h	1967;"	d
R_P0_TSSI_TRK	reg.h	1953;"	d
R_P0_TXDPD	reg.h	1962;"	d
R_P0_TXPW_RSTB	reg.h	1964;"	d
R_P1_DBGMOD	reg.h	1824;"	d
R_P1_EN_SOUND_WO_NDP	reg.h	1822;"	d
R_P1_MODE	reg.h	1911;"	d
R_P1_NBIIDX	reg.h	1925;"	d
R_P1_RFCTM	reg.h	2001;"	d
R_P1_RFCTM_RDY	reg.h	2002;"	d
R_P1_TMETER	reg.h	1991;"	d
R_P1_TSSI_AVG	reg.h	1999;"	d
R_P1_TSSI_MV_AVG	reg.h	2007;"	d
R_P1_TSSI_TRK	reg.h	1995;"	d
R_P1_TXPW_RSTB	reg.h	2004;"	d
R_PATH0_BTG	reg.h	1900;"	d
R_PATH0_IB_PBK	reg.h	1894;"	d
R_PATH0_IB_PKPW	reg.h	1866;"	d
R_PATH0_LNA_ERR1	reg.h	1868;"	d
R_PATH0_LNA_ERR2	reg.h	1872;"	d
R_PATH0_LNA_ERR3	reg.h	1876;"	d
R_PATH0_LNA_ERR4	reg.h	1881;"	d
R_PATH0_LNA_ERR5	reg.h	1885;"	d
R_PATH0_LNA_INIT	reg.h	1898;"	d
R_PATH0_P20_FOLLOW_BY_PAGCUGC	reg.h	1904;"	d
R_PATH0_RXB_INIT	reg.h	1896;"	d
R_PATH0_S20_FOLLOW_BY_PAGCUGC	reg.h	1906;"	d
R_PATH0_TIA_ERR_G0	reg.h	1887;"	d
R_PATH0_TIA_ERR_G1	reg.h	1890;"	d
R_PATH0_TIA_INIT	reg.h	1902;"	d
R_PATH1_BTG	reg.h	1917;"	d
R_PATH1_LNA_INIT	reg.h	1913;"	d
R_PATH1_P20_FOLLOW_BY_PAGCUGC	reg.h	1921;"	d
R_PATH1_RXB_INIT	reg.h	1919;"	d
R_PATH1_S20_FOLLOW_BY_PAGCUGC	reg.h	1923;"	d
R_PATH1_TIA_INIT	reg.h	1915;"	d
R_PD_CTRL	reg.h	1724;"	d
R_PMAC_GNT	reg.h	1677;"	d
R_PMAC_RXMOD	reg.h	1684;"	d
R_PMAC_RX_CFG1	reg.h	1682;"	d
R_PMAC_TX_CNT	reg.h	1696;"	d
R_PMAC_TX_CTRL	reg.h	1690;"	d
R_PMAC_TX_PRD	reg.h	1692;"	d
R_RFGAIN	reg.h	2098;"	d
R_RFGAIN_BND	reg.h	2101;"	d
R_RPT_COM	reg.h	2075;"	d
R_RPT_PER	reg.h	2125;"	d
R_RSTB_ASYNC	reg.h	1675;"	d
R_RSTB_WATCH_DOG	reg.h	1658;"	d
R_RXCCA	reg.h	1814;"	d
R_RXCFIR_P0C0	reg.h	2126;"	d
R_RXCFIR_P0C1	reg.h	2127;"	d
R_RXCFIR_P0C2	reg.h	2128;"	d
R_RXCFIR_P0C3	reg.h	2129;"	d
R_RXCFIR_P1C0	reg.h	2134;"	d
R_RXCFIR_P1C1	reg.h	2135;"	d
R_RXCFIR_P1C2	reg.h	2136;"	d
R_RXCFIR_P1C3	reg.h	2137;"	d
R_RXIQC	reg.h	2090;"	d
R_RXSC	reg.h	1816;"	d
R_RXSCOBC	reg.h	1818;"	d
R_RXSCOCCK	reg.h	1820;"	d
R_S0_ADDCK	reg.h	1793;"	d
R_S0_DACKI	reg.h	1973;"	d
R_S0_DACKI2	reg.h	1976;"	d
R_S0_DACKI7	reg.h	1978;"	d
R_S0_DACKI8	reg.h	1980;"	d
R_S0_DACKQ	reg.h	1982;"	d
R_S0_DACKQ2	reg.h	1985;"	d
R_S0_DACKQ7	reg.h	1987;"	d
R_S0_DACKQ8	reg.h	1989;"	d
R_S0_RXDC	reg.h	1744;"	d
R_S0_RXDC2	reg.h	1747;"	d
R_S1_ADDCK	reg.h	1836;"	d
R_S1_DACKI	reg.h	2010;"	d
R_S1_DACKI2	reg.h	2013;"	d
R_S1_DACKI7	reg.h	2015;"	d
R_S1_DACKI8	reg.h	2017;"	d
R_S1_DACKQ	reg.h	2019;"	d
R_S1_DACKQ2	reg.h	2022;"	d
R_S1_DACKQ7	reg.h	2024;"	d
R_S1_DACKQ8	reg.h	2026;"	d
R_S1_RXDC	reg.h	1826;"	d
R_S1_RXDC2	reg.h	1829;"	d
R_SEG0CSI	reg.h	1841;"	d
R_SEG0CSI_EN	reg.h	1843;"	d
R_SEG0R_PD	reg.h	1928;"	d
R_SPOOF_ASYNC_RST	reg.h	1730;"	d
R_SRAM_IQRX	reg.h	2069;"	d
R_SRAM_IQRX2	reg.h	2072;"	d
R_TPG_MOD	reg.h	2047;"	d
R_TSSI_THER	reg.h	1788;"	d
R_TSSI_THOF	reg.h	2009;"	d
R_TXAGC_BB	reg.h	1790;"	d
R_TXAGC_BB_S1	reg.h	1833;"	d
R_TXAGC_RFK	reg.h	2113;"	d
R_TXAGC_TP	reg.h	1786;"	d
R_TXCFIR_P0C0	reg.h	2130;"	d
R_TXCFIR_P0C1	reg.h	2131;"	d
R_TXCFIR_P0C2	reg.h	2132;"	d
R_TXCFIR_P0C3	reg.h	2133;"	d
R_TXCFIR_P1C0	reg.h	2138;"	d
R_TXCFIR_P1C1	reg.h	2139;"	d
R_TXCFIR_P1C2	reg.h	2140;"	d
R_TXCFIR_P1C3	reg.h	2141;"	d
R_TXFIR0	reg.h	1798;"	d
R_TXFIR2	reg.h	1800;"	d
R_TXFIR4	reg.h	1802;"	d
R_TXFIR6	reg.h	1804;"	d
R_TXFIR8	reg.h	1806;"	d
R_TXFIRA	reg.h	1808;"	d
R_TXFIRC	reg.h	1810;"	d
R_TXFIRE	reg.h	1812;"	d
R_TXGAIN_SCALE	reg.h	1969;"	d
R_TXIQC	reg.h	2089;"	d
R_TXNSS_MAP	reg.h	1864;"	d
R_TXPATH_SEL	reg.h	1860;"	d
R_TXPWR	reg.h	1862;"	d
R_TX_COUNTER	reg.h	1756;"	d
R_UPD_CLK_ADC	reg.h	1672;"	d
R_UPD_P0	reg.h	1657;"	d
R_W_COEF	reg.h	2120;"	d
SCH_PREBKF_24US	reg.h	715;"	d
SDIO_LOCAL_BASE_ADDR	mac.h	401;"	d
SECURITY_CAM_BASE_ADDR	mac.h	232;"	d
SER_DO_HCI_ST	ser.c	/^	SER_DO_HCI_ST,$/;"	e	enum:ser_state	file:
SER_EV_DO_RECOVERY	ser.c	/^	SER_EV_DO_RECOVERY, \/* M3 *\/$/;"	e	enum:ser_evt	file:
SER_EV_FW_M5_TIMEOUT	ser.c	/^	SER_EV_FW_M5_TIMEOUT,$/;"	e	enum:ser_evt	file:
SER_EV_L0_RESET	ser.c	/^	SER_EV_L0_RESET,$/;"	e	enum:ser_evt	file:
SER_EV_L1_RESET	ser.c	/^	SER_EV_L1_RESET, \/* M1 *\/$/;"	e	enum:ser_evt	file:
SER_EV_L2_RECFG_DONE	ser.c	/^	SER_EV_L2_RECFG_DONE,$/;"	e	enum:ser_evt	file:
SER_EV_L2_RECFG_TIMEOUT	ser.c	/^	SER_EV_L2_RECFG_TIMEOUT,$/;"	e	enum:ser_evt	file:
SER_EV_L2_RESET	ser.c	/^	SER_EV_L2_RESET,$/;"	e	enum:ser_evt	file:
SER_EV_M3_TIMEOUT	ser.c	/^	SER_EV_M3_TIMEOUT,$/;"	e	enum:ser_evt	file:
SER_EV_MAC_RESET_DONE	ser.c	/^	SER_EV_MAC_RESET_DONE, \/* M5 *\/$/;"	e	enum:ser_evt	file:
SER_EV_MAXX	ser.c	/^	SER_EV_MAXX$/;"	e	enum:ser_evt	file:
SER_EV_NONE	ser.c	/^	SER_EV_NONE,$/;"	e	enum:ser_evt	file:
SER_EV_STATE_IN	ser.c	/^	SER_EV_STATE_IN,$/;"	e	enum:ser_evt	file:
SER_EV_STATE_OUT	ser.c	/^	SER_EV_STATE_OUT,$/;"	e	enum:ser_evt	file:
SER_IDLE_ST	ser.c	/^	SER_IDLE_ST,$/;"	e	enum:ser_state	file:
SER_L2_RESET_ST	ser.c	/^	SER_L2_RESET_ST,$/;"	e	enum:ser_state	file:
SER_RECFG_TIMEOUT	ser.c	12;"	d	file:
SER_RESET_TRX_ST	ser.c	/^	SER_RESET_TRX_ST,$/;"	e	enum:ser_state	file:
SER_ST_MAX_ST	ser.c	/^	SER_ST_MAX_ST$/;"	e	enum:ser_state	file:
SET_BA_CAM_BMAP_SIZE	fw.h	989;"	d
SET_BA_CAM_ENTRY_IDX	fw.h	983;"	d
SET_BA_CAM_INIT_REQ	fw.h	981;"	d
SET_BA_CAM_MACID	fw.h	987;"	d
SET_BA_CAM_SSN	fw.h	991;"	d
SET_BA_CAM_TID	fw.h	985;"	d
SET_BA_CAM_VALID	fw.h	979;"	d
SET_BT_GOLDEN_RX_RANGE	fw.h	/^	SET_BT_GOLDEN_RX_RANGE,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_IGNORE_WLAN_ACT	fw.h	/^	SET_BT_IGNORE_WLAN_ACT,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_INFO_REPORT	fw.h	/^	SET_BT_INFO_REPORT,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_LNA_CONSTRAIN	fw.h	/^	SET_BT_LNA_CONSTRAIN,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_PSD_REPORT	fw.h	/^	SET_BT_PSD_REPORT,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_RREG_ADDR	fw.h	/^	SET_BT_RREG_ADDR,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_TX_PWR	fw.h	/^	SET_BT_TX_PWR,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_WL_CH_INFO	fw.h	/^	SET_BT_WL_CH_INFO,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_WREG_ADDR	fw.h	/^	SET_BT_WREG_ADDR,$/;"	e	enum:rtw89_btc_btf_set
SET_BT_WREG_VAL	fw.h	/^	SET_BT_WREG_VAL,$/;"	e	enum:rtw89_btc_btf_set
SET_CMC_TBL_ACQ_RPT_EN	fw.h	335;"	d
SET_CMC_TBL_ADDR_CAM_INDEX	fw.h	776;"	d
SET_CMC_TBL_ALL_ACK_SUPPORT	fw.h	699;"	d
SET_CMC_TBL_AMPDU_DENSITY	fw.h	384;"	d
SET_CMC_TBL_AMPDU_LEN_SEL	fw.h	405;"	d
SET_CMC_TBL_AMPDU_MAX_LEN	fw.h	503;"	d
SET_CMC_TBL_AMPDU_MAX_TIME	fw.h	517;"	d
SET_CMC_TBL_AMPDU_TIME_SEL	fw.h	398;"	d
SET_CMC_TBL_ANTSEL_A	fw.h	748;"	d
SET_CMC_TBL_ANTSEL_B	fw.h	755;"	d
SET_CMC_TBL_ANTSEL_C	fw.h	762;"	d
SET_CMC_TBL_ANTSEL_D	fw.h	769;"	d
SET_CMC_TBL_ARFR_CTRL	fw.h	328;"	d
SET_CMC_TBL_A_CTRL_BQR	fw.h	636;"	d
SET_CMC_TBL_A_CTRL_BSR	fw.h	650;"	d
SET_CMC_TBL_A_CTRL_CAS	fw.h	657;"	d
SET_CMC_TBL_A_CTRL_UPH	fw.h	643;"	d
SET_CMC_TBL_BA_BMAP	fw.h	531;"	d
SET_CMC_TBL_BE_LFTIME_SEL	fw.h	552;"	d
SET_CMC_TBL_BK_LFTIME_SEL	fw.h	559;"	d
SET_CMC_TBL_BMC	fw.h	580;"	d
SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT	fw.h	706;"	d
SET_CMC_TBL_CB	fw.h	851;"	d
SET_CMC_TBL_CCA_RTS	fw.h	482;"	d
SET_CMC_TBL_CS	fw.h	858;"	d
SET_CMC_TBL_CSI_BW	fw.h	914;"	d
SET_CMC_TBL_CSI_FIX_RATE	fw.h	893;"	d
SET_CMC_TBL_CSI_GID_SEL	fw.h	907;"	d
SET_CMC_TBL_CSI_GI_LTF	fw.h	900;"	d
SET_CMC_TBL_CSI_LDPC_EN	fw.h	879;"	d
SET_CMC_TBL_CSI_PARA_EN	fw.h	886;"	d
SET_CMC_TBL_CSI_STBC_EN	fw.h	872;"	d
SET_CMC_TBL_CSI_TXBF_EN	fw.h	865;"	d
SET_CMC_TBL_CTRL_CNT	fw.h	685;"	d
SET_CMC_TBL_CTRL_CNT_VLD	fw.h	678;"	d
SET_CMC_TBL_CTS2SELF_EN	fw.h	475;"	d
SET_CMC_TBL_DARF_TC_INDEX	fw.h	321;"	d
SET_CMC_TBL_DATARATE	fw.h	293;"	d
SET_CMC_TBL_DATA_BW	fw.h	307;"	d
SET_CMC_TBL_DATA_BW_ER	fw.h	664;"	d
SET_CMC_TBL_DATA_DCM	fw.h	608;"	d
SET_CMC_TBL_DATA_ER	fw.h	615;"	d
SET_CMC_TBL_DATA_GI_LTF	fw.h	314;"	d
SET_CMC_TBL_DATA_LDPC	fw.h	622;"	d
SET_CMC_TBL_DATA_RTY_LOWEST_RATE	fw.h	391;"	d
SET_CMC_TBL_DATA_STBC	fw.h	629;"	d
SET_CMC_TBL_DATA_TXCNT_LMT_SEL	fw.h	454;"	d
SET_CMC_TBL_DATA_TX_CNT_LMT	fw.h	447;"	d
SET_CMC_TBL_DISDATAFB	fw.h	370;"	d
SET_CMC_TBL_DISRTSFB	fw.h	363;"	d
SET_CMC_TBL_DOPPLER_CTRL	fw.h	797;"	d
SET_CMC_TBL_FORCE_TXOP	fw.h	300;"	d
SET_CMC_TBL_HW_RTS_EN	fw.h	489;"	d
SET_CMC_TBL_LSIG_TXOP_EN	fw.h	671;"	d
SET_CMC_TBL_MASK_ACQ_RPT_EN	fw.h	334;"	d
SET_CMC_TBL_MASK_ADDR_CAM_INDEX	fw.h	775;"	d
SET_CMC_TBL_MASK_ALL_ACK_SUPPORT	fw.h	698;"	d
SET_CMC_TBL_MASK_AMPDU_DENSITY	fw.h	383;"	d
SET_CMC_TBL_MASK_AMPDU_LEN_SEL	fw.h	404;"	d
SET_CMC_TBL_MASK_AMPDU_MAX_LEN	fw.h	502;"	d
SET_CMC_TBL_MASK_AMPDU_MAX_TIME	fw.h	516;"	d
SET_CMC_TBL_MASK_AMPDU_TIME_SEL	fw.h	397;"	d
SET_CMC_TBL_MASK_ANTSEL_A	fw.h	747;"	d
SET_CMC_TBL_MASK_ANTSEL_B	fw.h	754;"	d
SET_CMC_TBL_MASK_ANTSEL_C	fw.h	761;"	d
SET_CMC_TBL_MASK_ANTSEL_D	fw.h	768;"	d
SET_CMC_TBL_MASK_ARFR_CTRL	fw.h	327;"	d
SET_CMC_TBL_MASK_A_CTRL_BQR	fw.h	635;"	d
SET_CMC_TBL_MASK_A_CTRL_BSR	fw.h	649;"	d
SET_CMC_TBL_MASK_A_CTRL_CAS	fw.h	656;"	d
SET_CMC_TBL_MASK_A_CTRL_UPH	fw.h	642;"	d
SET_CMC_TBL_MASK_BA_BMAP	fw.h	530;"	d
SET_CMC_TBL_MASK_BE_LFTIME_SEL	fw.h	551;"	d
SET_CMC_TBL_MASK_BK_LFTIME_SEL	fw.h	558;"	d
SET_CMC_TBL_MASK_BMC	fw.h	579;"	d
SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT	fw.h	705;"	d
SET_CMC_TBL_MASK_CB	fw.h	850;"	d
SET_CMC_TBL_MASK_CCA_RTS	fw.h	481;"	d
SET_CMC_TBL_MASK_CS	fw.h	857;"	d
SET_CMC_TBL_MASK_CSI_BW	fw.h	913;"	d
SET_CMC_TBL_MASK_CSI_FIX_RATE	fw.h	892;"	d
SET_CMC_TBL_MASK_CSI_GID_SEL	fw.h	906;"	d
SET_CMC_TBL_MASK_CSI_GI_LTF	fw.h	899;"	d
SET_CMC_TBL_MASK_CSI_LDPC_EN	fw.h	878;"	d
SET_CMC_TBL_MASK_CSI_PARA_EN	fw.h	885;"	d
SET_CMC_TBL_MASK_CSI_STBC_EN	fw.h	871;"	d
SET_CMC_TBL_MASK_CSI_TXBF_EN	fw.h	864;"	d
SET_CMC_TBL_MASK_CTRL_CNT	fw.h	684;"	d
SET_CMC_TBL_MASK_CTRL_CNT_VLD	fw.h	677;"	d
SET_CMC_TBL_MASK_CTS2SELF_EN	fw.h	474;"	d
SET_CMC_TBL_MASK_DARF_TC_INDEX	fw.h	320;"	d
SET_CMC_TBL_MASK_DATARATE	fw.h	292;"	d
SET_CMC_TBL_MASK_DATA_BW	fw.h	306;"	d
SET_CMC_TBL_MASK_DATA_BW_ER	fw.h	663;"	d
SET_CMC_TBL_MASK_DATA_DCM	fw.h	607;"	d
SET_CMC_TBL_MASK_DATA_ER	fw.h	614;"	d
SET_CMC_TBL_MASK_DATA_GI_LTF	fw.h	313;"	d
SET_CMC_TBL_MASK_DATA_LDPC	fw.h	621;"	d
SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE	fw.h	390;"	d
SET_CMC_TBL_MASK_DATA_STBC	fw.h	628;"	d
SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL	fw.h	453;"	d
SET_CMC_TBL_MASK_DATA_TX_CNT_LMT	fw.h	446;"	d
SET_CMC_TBL_MASK_DISDATAFB	fw.h	369;"	d
SET_CMC_TBL_MASK_DISRTSFB	fw.h	362;"	d
SET_CMC_TBL_MASK_DOPPLER_CTRL	fw.h	796;"	d
SET_CMC_TBL_MASK_FORCE_TXOP	fw.h	299;"	d
SET_CMC_TBL_MASK_HW_RTS_EN	fw.h	488;"	d
SET_CMC_TBL_MASK_LSIG_TXOP_EN	fw.h	670;"	d
SET_CMC_TBL_MASK_MAX_AGG_NUM	fw.h	523;"	d
SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL	fw.h	460;"	d
SET_CMC_TBL_MASK_MBSSID	fw.h	586;"	d
SET_CMC_TBL_MASK_MGQ_RPT_EN	fw.h	341;"	d
SET_CMC_TBL_MASK_MULTI_PORT_ID	fw.h	572;"	d
SET_CMC_TBL_MASK_NAVUSEHDR	fw.h	593;"	d
SET_CMC_TBL_MASK_NC	fw.h	829;"	d
SET_CMC_TBL_MASK_NG	fw.h	843;"	d
SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING	fw.h	803;"	d
SET_CMC_TBL_MASK_NR	fw.h	836;"	d
SET_CMC_TBL_MASK_NTX_PATH_EN	fw.h	712;"	d
SET_CMC_TBL_MASK_PAID	fw.h	782;"	d
SET_CMC_TBL_MASK_PATH_MAP_A	fw.h	719;"	d
SET_CMC_TBL_MASK_PATH_MAP_B	fw.h	726;"	d
SET_CMC_TBL_MASK_PATH_MAP_C	fw.h	733;"	d
SET_CMC_TBL_MASK_PATH_MAP_D	fw.h	740;"	d
SET_CMC_TBL_MASK_RESP_REF_RATE	fw.h	691;"	d
SET_CMC_TBL_MASK_RTSRATE	fw.h	425;"	d
SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE	fw.h	495;"	d
SET_CMC_TBL_MASK_RTS_EN	fw.h	467;"	d
SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE	fw.h	439;"	d
SET_CMC_TBL_MASK_RTS_TXCNT_LMT	fw.h	418;"	d
SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL	fw.h	411;"	d
SET_CMC_TBL_MASK_SECTYPE	fw.h	565;"	d
SET_CMC_TBL_MASK_TRYRATE	fw.h	376;"	d
SET_CMC_TBL_MASK_TWTQ_RPT_EN	fw.h	355;"	d
SET_CMC_TBL_MASK_TXPWR_MODE	fw.h	600;"	d
SET_CMC_TBL_MASK_TXPWR_TOLERENCE	fw.h	816;"	d
SET_CMC_TBL_MASK_ULDL	fw.h	789;"	d
SET_CMC_TBL_MASK_ULQ_RPT_EN	fw.h	348;"	d
SET_CMC_TBL_MASK_UL_MU_DIS	fw.h	509;"	d
SET_CMC_TBL_MASK_VCS_STBC	fw.h	432;"	d
SET_CMC_TBL_MASK_VI_LFTIME_SEL	fw.h	544;"	d
SET_CMC_TBL_MASK_VO_LFTIME_SEL	fw.h	537;"	d
SET_CMC_TBL_MAX_AGG_NUM	fw.h	524;"	d
SET_CMC_TBL_MAX_AGG_NUM_SEL	fw.h	461;"	d
SET_CMC_TBL_MBSSID	fw.h	587;"	d
SET_CMC_TBL_MGQ_RPT_EN	fw.h	342;"	d
SET_CMC_TBL_MULTI_PORT_ID	fw.h	573;"	d
SET_CMC_TBL_NAVUSEHDR	fw.h	594;"	d
SET_CMC_TBL_NC	fw.h	830;"	d
SET_CMC_TBL_NG	fw.h	844;"	d
SET_CMC_TBL_NOMINAL_PKT_PADDING	fw.h	804;"	d
SET_CMC_TBL_NOMINAL_PKT_PADDING40	fw.h	810;"	d
SET_CMC_TBL_NOMINAL_PKT_PADDING80	fw.h	823;"	d
SET_CMC_TBL_NR	fw.h	837;"	d
SET_CMC_TBL_NTX_PATH_EN	fw.h	713;"	d
SET_CMC_TBL_PAID	fw.h	783;"	d
SET_CMC_TBL_PATH_MAP_A	fw.h	720;"	d
SET_CMC_TBL_PATH_MAP_B	fw.h	727;"	d
SET_CMC_TBL_PATH_MAP_C	fw.h	734;"	d
SET_CMC_TBL_PATH_MAP_D	fw.h	741;"	d
SET_CMC_TBL_RESP_REF_RATE	fw.h	692;"	d
SET_CMC_TBL_RTSRATE	fw.h	426;"	d
SET_CMC_TBL_RTS_DROP_DATA_MODE	fw.h	496;"	d
SET_CMC_TBL_RTS_EN	fw.h	468;"	d
SET_CMC_TBL_RTS_RTY_LOWEST_RATE	fw.h	440;"	d
SET_CMC_TBL_RTS_TXCNT_LMT	fw.h	419;"	d
SET_CMC_TBL_RTS_TXCNT_LMT_SEL	fw.h	412;"	d
SET_CMC_TBL_SECTYPE	fw.h	566;"	d
SET_CMC_TBL_TRYRATE	fw.h	377;"	d
SET_CMC_TBL_TWTQ_RPT_EN	fw.h	356;"	d
SET_CMC_TBL_TXPWR_MODE	fw.h	601;"	d
SET_CMC_TBL_TXPWR_TOLERENCE	fw.h	817;"	d
SET_CMC_TBL_ULDL	fw.h	790;"	d
SET_CMC_TBL_ULQ_RPT_EN	fw.h	349;"	d
SET_CMC_TBL_UL_MU_DIS	fw.h	510;"	d
SET_CMC_TBL_VCS_STBC	fw.h	433;"	d
SET_CMC_TBL_VI_LFTIME_SEL	fw.h	545;"	d
SET_CMC_TBL_VO_LFTIME_SEL	fw.h	538;"	d
SET_CTRL_INFO_MACID	fw.h	288;"	d
SET_CTRL_INFO_OPERATION	fw.h	290;"	d
SET_CX_POLICY	fw.h	/^	SET_CX_POLICY,$/;"	e	enum:rtw89_btc_btf_set
SET_DRV_EVENT	fw.h	/^	SET_DRV_EVENT,$/;"	e	enum:rtw89_btc_btf_set
SET_DRV_INFO	fw.h	/^	SET_DRV_INFO,$/;"	e	enum:rtw89_btc_btf_set
SET_FWROLE_MAINTAIN_MACID	fw.h	921;"	d
SET_FWROLE_MAINTAIN_SELF_ROLE	fw.h	923;"	d
SET_FWROLE_MAINTAIN_UPD_MODE	fw.h	925;"	d
SET_FWROLE_MAINTAIN_WIFI_ROLE	fw.h	927;"	d
SET_FW_HDR_PART_SIZE	fw.h	285;"	d
SET_GENERAL_PKT_CTS2SELF_ID	fw.h	967;"	d
SET_GENERAL_PKT_MACID	fw.h	957;"	d
SET_GENERAL_PKT_NULL_ID	fw.h	963;"	d
SET_GENERAL_PKT_PROBRSP_ID	fw.h	959;"	d
SET_GENERAL_PKT_PSPOLL_ID	fw.h	961;"	d
SET_GENERAL_PKT_QOS_NULL_ID	fw.h	965;"	d
SET_GPIO_DBG	fw.h	/^	SET_GPIO_DBG,$/;"	e	enum:rtw89_btc_btf_set
SET_H2C_TEST	fw.h	/^	SET_H2C_TEST,$/;"	e	enum:rtw89_btc_btf_set
SET_JOININFO_BAND	fw.h	934;"	d
SET_JOININFO_DLBW	fw.h	942;"	d
SET_JOININFO_DL_T_PE	fw.h	946;"	d
SET_JOININFO_ISHESTA	fw.h	940;"	d
SET_JOININFO_MACID	fw.h	930;"	d
SET_JOININFO_NET_TYPE	fw.h	950;"	d
SET_JOININFO_OP	fw.h	932;"	d
SET_JOININFO_PORT_ID	fw.h	948;"	d
SET_JOININFO_SELF_ROLE	fw.h	954;"	d
SET_JOININFO_TF_MAC_PAD	fw.h	944;"	d
SET_JOININFO_TGR	fw.h	938;"	d
SET_JOININFO_WIFI_ROLE	fw.h	952;"	d
SET_JOININFO_WMM	fw.h	936;"	d
SET_LOG_CFG_COMP	fw.h	974;"	d
SET_LOG_CFG_COMP_EXT	fw.h	976;"	d
SET_LOG_CFG_LEVEL	fw.h	970;"	d
SET_LOG_CFG_PATH	fw.h	972;"	d
SET_LPS_PARM_AWAKEINTERVAL	fw.h	1002;"	d
SET_LPS_PARM_BEUAPSD	fw.h	1008;"	d
SET_LPS_PARM_BKUAPSD	fw.h	1010;"	d
SET_LPS_PARM_LASTRPWM	fw.h	1012;"	d
SET_LPS_PARM_MACID	fw.h	994;"	d
SET_LPS_PARM_PSMODE	fw.h	996;"	d
SET_LPS_PARM_RLBM	fw.h	998;"	d
SET_LPS_PARM_SMARTPS	fw.h	1000;"	d
SET_LPS_PARM_VIUAPSD	fw.h	1006;"	d
SET_LPS_PARM_VOUAPSD	fw.h	1004;"	d
SET_MAX1	fw.h	/^	SET_MAX1,$/;"	e	enum:rtw89_btc_btf_set
SET_MREG_TABLE	fw.h	/^	SET_MREG_TABLE,$/;"	e	enum:rtw89_btc_btf_set
SET_QUOTA	mac.c	1303;"	d	file:
SET_QUOTA	mac.c	1340;"	d	file:
SET_QUOTA_VAL	mac.c	1293;"	d	file:
SET_REPORT_EN	fw.h	/^	SET_REPORT_EN = 0x0,$/;"	e	enum:rtw89_btc_btf_set
SET_SLOT_TABLE	fw.h	/^	SET_SLOT_TABLE,$/;"	e	enum:rtw89_btc_btf_set
SHARED_BUF_BASE_ADDR	mac.h	239;"	d
SHCUT_MACHDR_BASE_ADDR	mac.h	241;"	d
SLOT_ISO	core.h	/^	SLOT_ISO = 0x1, \/* no accept BT Lower-Pri Tx\/Rx request 0x778 = d*\/$/;"	e	enum:btc_slot_type
SLOT_MIX	core.h	/^	SLOT_MIX = 0x0, \/* accept BT Lower-Pri Tx\/Rx request 0x778 = 1 *\/$/;"	e	enum:btc_slot_type
SS_CTRL1_R_NEXT_LINK	mac.h	435;"	d
SS_CTRL1_R_TX_LEN	mac.h	434;"	d
SS_LINK_SIZE	mac.h	436;"	d
SS_MACID_SH	mac.h	432;"	d
SS_TX_LEN_MSK	mac.h	433;"	d
STA_SCHED_BASE_ADDR	mac.h	230;"	d
SW_CVR_CNT	mac.h	379;"	d
SW_CVR_DUR_US	mac.h	378;"	d
SYNC	rtw8852a_rfk.c	/^	SYNC		= 0x10,$/;"	e	enum:rtw8852a_dpk_id	file:
S_AX_CTS2S_TH_1K	reg.h	988;"	d
S_AX_CTS2S_TH_SEC_256B	reg.h	979;"	d
S_AX_PLE_PAGE_SEL_128	mac.h	398;"	d
S_AX_PLE_PAGE_SEL_256	mac.h	399;"	d
S_AX_PLE_PAGE_SEL_64	mac.h	397;"	d
S_AX_PTCL_TO_2MS	reg.h	1044;"	d
S_AX_WDE_PAGE_SEL_128	mac.h	390;"	d
S_AX_WDE_PAGE_SEL_256	mac.h	391;"	d
S_AX_WDE_PAGE_SEL_64	mac.h	389;"	d
TBTT_ERLY_DEF	mac.c	2747;"	d	file:
TIA0_GAIN_A	phy.h	75;"	d
TIA0_GAIN_G	phy.h	76;"	d
TIA_GAIN_NUM	core.h	2506;"	d
TIA_IDX_MAX	phy.h	85;"	d
TIA_IDX_MIN	phy.h	86;"	d
TMAC_DBG_SEL_C0	mac.h	439;"	d
TMAC_DBG_SEL_C1	mac.h	442;"	d
TRXCFG_MPDU_PROC_ACT_FRWD	reg.h	542;"	d
TRXCFG_MPDU_PROC_CUT_CTRL	reg.h	553;"	d
TRXCFG_MPDU_PROC_TF_FRWD	reg.h	545;"	d
TRXCFG_RMAC_CCA_TO	mac.c	1802;"	d	file:
TRXCFG_RMAC_DATA_TO	mac.c	1803;"	d	file:
TRXCFG_WAIT_CNT	mac.h	383;"	d
TRXPTCL_DBG_SEL_C0	mac.h	441;"	d
TRXPTCL_DBG_SEL_C1	mac.h	444;"	d
TRXPTRL_DBG_SEL_RMAC	mac.h	458;"	d
TRXPTRL_DBG_SEL_TMAC	mac.h	457;"	d
TSSI_CCK_CH_GROUP_NUM	core.h	2573;"	d
TSSI_EXTRA_GET_GROUP_IDX1	rtw8852a_rfk.c	3237;"	d	file:
TSSI_EXTRA_GET_GROUP_IDX2	rtw8852a_rfk.c	3238;"	d	file:
TSSI_EXTRA_GROUP	rtw8852a_rfk.c	3235;"	d	file:
TSSI_EXTRA_GROUP_BIT	rtw8852a_rfk.c	3234;"	d	file:
TSSI_MCS_2G_CH_GROUP_NUM	core.h	2574;"	d
TSSI_MCS_5G_CH_GROUP_NUM	core.h	2575;"	d
TSSI_MCS_CH_GROUP_NUM	core.h	2576;"	d
TSSI_TRIM_CH_GROUP_NUM	core.h	2571;"	d
TXBD_HOST_IDX_MASK	pci.h	134;"	d
TXBD_HW_IDX_MASK	pci.h	133;"	d
U4_MAX_BIT	phy.h	78;"	d
U8_MAX_BIT	phy.h	79;"	d
VAR_LEN	core.c	858;"	d	file:
VAR_LEN_UNIT	core.c	859;"	d	file:
WB_RSSI_BASE	phy.c	2587;"	d	file:
WDE_DLE_PORT_ID_CMAC0	mac.h	/^	WDE_DLE_PORT_ID_CMAC0 = 3,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_CMAC1	mac.h	/^	WDE_DLE_PORT_ID_CMAC1 = 4,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_CPU_IO	mac.h	/^	WDE_DLE_PORT_ID_CPU_IO = 6,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_DISPATCH	mac.h	/^	WDE_DLE_PORT_ID_DISPATCH = 0,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_END	mac.h	/^	WDE_DLE_PORT_ID_END = 8$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_PKTIN	mac.h	/^	WDE_DLE_PORT_ID_PKTIN = 1,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_PORT_ID_WDRLS	mac.h	/^	WDE_DLE_PORT_ID_WDRLS = 7,$/;"	e	enum:rtw89_mac_wde_dle_port_id
WDE_DLE_QUEID_DROP_LIFETIME_TO	mac.h	/^	WDE_DLE_QUEID_DROP_LIFETIME_TO = 2,$/;"	e	enum:rtw89_mac_wde_dle_queid_wdrls
WDE_DLE_QUEID_DROP_MACID_DROP	mac.h	/^	WDE_DLE_QUEID_DROP_MACID_DROP = 3,$/;"	e	enum:rtw89_mac_wde_dle_queid_wdrls
WDE_DLE_QUEID_DROP_RETRY_LIMIT	mac.h	/^	WDE_DLE_QUEID_DROP_RETRY_LIMIT = 1,$/;"	e	enum:rtw89_mac_wde_dle_queid_wdrls
WDE_DLE_QUEID_NO_REPORT	mac.h	/^	WDE_DLE_QUEID_NO_REPORT = 4$/;"	e	enum:rtw89_mac_wde_dle_queid_wdrls
WDE_DLE_QUEID_TXOK	mac.h	/^	WDE_DLE_QUEID_TXOK = 0,$/;"	e	enum:rtw89_mac_wde_dle_queid_wdrls
WDE_MGN_INI_RDY	reg.h	414;"	d
WDE_QTAID_CPUIO	mac.h	/^	WDE_QTAID_CPUIO = 4,$/;"	e	enum:rtw89_mac_dle_wde_quota_id
WDE_QTAID_DATA_CPU	mac.h	/^	WDE_QTAID_DATA_CPU = 2,$/;"	e	enum:rtw89_mac_dle_wde_quota_id
WDE_QTAID_HOST_IF	mac.h	/^	WDE_QTAID_HOST_IF = 0,$/;"	e	enum:rtw89_mac_dle_wde_quota_id
WDE_QTAID_PKTIN	mac.h	/^	WDE_QTAID_PKTIN = 3,$/;"	e	enum:rtw89_mac_dle_wde_quota_id
WDE_QTAID_WLAN_CPU	mac.h	/^	WDE_QTAID_WLAN_CPU = 1,$/;"	e	enum:rtw89_mac_dle_wde_quota_id
WL_TX_POWER_ALL_TIME	coex.c	1457;"	d	file:
WL_TX_POWER_FRA_PART	coex.c	1460;"	d	file:
WL_TX_POWER_INT_PART	coex.c	1459;"	d	file:
WL_TX_POWER_NO_BTC_CTRL	coex.c	1456;"	d	file:
WL_TX_POWER_WITH_BT	coex.c	1458;"	d	file:
WMAC_SPEC_SIFS_CCK	reg.h	1141;"	d
WMAC_SPEC_SIFS_OFDM_52A	reg.h	1138;"	d
WMAC_SPEC_SIFS_OFDM_52B	reg.h	1139;"	d
WMAC_SPEC_SIFS_OFDM_52C	reg.h	1140;"	d
WOW_CAM_BASE_ADDR	mac.h	233;"	d
_4way	core.h	/^	u32 _4way: 1;$/;"	m	struct:rtw89_btc_wl_smap
__CPY_LE16	coex.c	798;"	d	file:
__CPY_LE16	coex.c	830;"	d	file:
__CPY_LE16S	coex.c	799;"	d	file:
__CPY_LE16S	coex.c	831;"	d	file:
__CPY_LE32	coex.c	801;"	d	file:
__CPY_LE32	coex.c	832;"	d	file:
__CPY_LE32S	coex.c	802;"	d	file:
__CPY_LE32S	coex.c	833;"	d	file:
__CPY_U8	coex.c	797;"	d	file:
__CPY_U8	coex.c	829;"	d	file:
__DEF_FBTC_SLOT	coex.c	74;"	d	file:
__DE_MASK	rtw8852a_rfk.c	3409;"	d	file:
__DE_MASK	rtw8852a_rfk.c	3467;"	d	file:
__GEN_TXPWR_ENT2	debug.c	345;"	d	file:
__GEN_TXPWR_ENT4	debug.c	348;"	d	file:
__GEN_TXPWR_ENT8	debug.c	351;"	d	file:
__MAC_TXPWR_LMT_PAGE_SIZE	rtw8852a.c	1365;"	d	file:
__MAC_TXPWR_LMT_PAGE_SIZE	rtw8852a.c	1390;"	d	file:
__MAC_TXPWR_LMT_RU_PAGE_SIZE	rtw8852a.c	1396;"	d	file:
__MAC_TXPWR_LMT_RU_PAGE_SIZE	rtw8852a.c	1423;"	d	file:
__RTW89_8852A_H__	rtw8852a.h	6;"	d
__RTW89_8852A_RFK_H__	rtw8852a_rfk.h	6;"	d
__RTW89_8852A_RFK_TABLE_H__	rtw8852a_rfk_table.h	6;"	d
__RTW89_8852A_TABLE_H__	rtw8852a_table.h	6;"	d
__RTW89_CAM_H__	cam.h	6;"	d
__RTW89_COEX_H__	coex.h	6;"	d
__RTW89_CORE_H__	core.h	6;"	d
__RTW89_DEBUG_H__	debug.h	6;"	d
__RTW89_EFUSE_H__	efuse.h	6;"	d
__RTW89_FW_H__	fw.h	6;"	d
__RTW89_MAC_H__	mac.h	6;"	d
__RTW89_PCI_H__	pci.h	6;"	d
__RTW89_PHY_H__	phy.h	6;"	d
__RTW89_PS_H_	ps.h	6;"	d
__RTW89_REG_H__	reg.h	6;"	d
__RTW89_SAR_H__	sar.h	6;"	d
__RTW89_TXRX_H__	txrx.h	6;"	d
__RTW89_UTIL_H__	util.h	5;"	d
__SER_H__	ser.h	5;"	d
____rtw89_conf_tx_edca	mac80211.c	/^static void ____rtw89_conf_tx_edca(struct rtw89_dev *rtwdev,$/;"	f	file:
____rtw89_conf_tx_mu_edca	mac80211.c	/^static void ____rtw89_conf_tx_mu_edca(struct rtw89_dev *rtwdev,$/;"	f	file:
__btc_ctrl_gen_all_time	rtw8852a.c	/^static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val)$/;"	f	file:
__btc_ctrl_gen_gnt_bt	rtw8852a.c	/^static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val)$/;"	f	file:
__btc_ctrl_rst_all_time	rtw8852a.c	/^static inline u32 __btc_ctrl_rst_all_time(u32 cur)$/;"	f	file:
__btc_ctrl_rst_gnt_bt	rtw8852a.c	/^static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur)$/;"	f	file:
__btc_ctrl_val_all_time	rtw8852a.c	/^static inline u32 __btc_ctrl_val_all_time(u32 ctrl)$/;"	f	file:
__btc_ctrl_val_gnt_bt	rtw8852a.c	/^static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl)$/;"	f	file:
__check_rate_pattern	phy.c	/^static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,$/;"	f	file:
__do_clr	rtw8852a.c	1801;"	d	file:
__do_clr	rtw8852a.c	1824;"	d	file:
__fill_txpwr_limit_nonbf_bf	phy.c	1117;"	d	file:
__get_sta_he_pkt_padding	fw.c	/^static void __get_sta_he_pkt_padding(struct rtw89_dev *rtwdev,$/;"	f	file:
__get_target	pci.c	/^__get_target(struct rtw89_dev *rtwdev, u16 *target, enum rtw89_pcie_phy phy_rate)$/;"	f	file:
__get_val	rtw8852a_rfk.c	2956;"	d	file:
__get_val	rtw8852a_rfk.c	3106;"	d	file:
__handle	rtw8852a.c	1802;"	d	file:
__handle	rtw8852a.c	1823;"	d	file:
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:btc_fbtc_1slot
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_btf_set_mon_reg
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_btf_set_report
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_btf_set_slot_table
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_btf_tlv
__packed	coex.c	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_prpt
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_btafh
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_btdevinfo
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_btscan
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_btver
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_cynullsta
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_cysta
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_gpio_dbg
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_mreg
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_mreg_val
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_rpt_ctrl
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_slot
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_slots
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_step
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_steps
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_fbtc_tdma
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_rpt_cmn_info
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_btc_wl_afh_info
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_rxdesc_long
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_rxdesc_short
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_txwd_body
__packed	core.h	/^} __packed;$/;"	v	typeref:struct:rtw89_txwd_info
__packed	fw.h	/^} __packed;$/;"	v	typeref:struct:rtw89_c2h_phy_cap
__packed	fw.h	/^} __packed;$/;"	v	typeref:struct:rtw89_fw_macid_pause_grp
__packed	fw.h	/^} __packed;$/;"	v	typeref:struct:rtw89_h2creg_sch_tx_en
__packed	fw.h	/^} __packed;$/;"	v	typeref:struct:rtw89_mfw_hdr
__packed	fw.h	/^} __packed;$/;"	v	typeref:struct:rtw89_mfw_info
__packed	pci.h	/^} __packed;$/;"	v	typeref:struct:rtw89_pci_rpp_fmt
__packed	pci.h	/^} __packed;$/;"	v	typeref:struct:rtw89_pci_rx_bd_32
__packed	pci.h	/^} __packed;$/;"	v	typeref:struct:rtw89_pci_tx_addr_info_32
__packed	pci.h	/^} __packed;$/;"	v	typeref:struct:rtw89_pci_tx_bd_32
__packed	pci.h	/^} __packed;$/;"	v	typeref:struct:rtw89_pci_tx_wp_info
__packed	rtw8852a.h	/^} __packed;$/;"	v	typeref:struct:rtw8852a_efuse
__packed	rtw8852a.h	/^} __packed;$/;"	v	typeref:struct:rtw8852a_tssi_offset
__pci_flush_txch	pci.c	/^static void __pci_flush_txch(struct rtw89_dev *rtwdev, u8 txch, bool drop)$/;"	f	file:
__print_regd	debug.c	/^static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev)$/;"	f	file:
__print_txpwr_ent	debug.c	/^static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,$/;"	f	file:
__print_txpwr_map	debug.c	/^static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_conf_tx	mac80211.c	/^static void __rtw89_conf_tx(struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_core_tx_adjust_he_qos_htc	core.c	/^__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_core_tx_check_he_qos_htc	core.c	/^__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_debug	debug.c	/^EXPORT_SYMBOL(__rtw89_debug);$/;"	v
__rtw89_debug	debug.c	/^void __rtw89_debug(struct rtw89_dev *rtwdev,$/;"	f
__rtw89_enter_lps	ps.c	/^static void __rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id)$/;"	f	file:
__rtw89_enter_ps_mode	ps.c	/^static void __rtw89_enter_ps_mode(struct rtw89_dev *rtwdev)$/;"	f	file:
__rtw89_fw_download_hdr	fw.c	/^static int __rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len)$/;"	f	file:
__rtw89_fw_download_main	fw.c	/^static int __rtw89_fw_download_main(struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_fw_recognize	fw.c	/^int __rtw89_fw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type)$/;"	f	file:
__rtw89_leave_lps	ps.c	/^static void __rtw89_leave_lps(struct rtw89_dev *rtwdev, u8 mac_id)$/;"	f	file:
__rtw89_leave_ps_mode	ps.c	/^void __rtw89_leave_ps_mode(struct rtw89_dev *rtwdev)$/;"	f
__rtw89_mac_set_tx_time	mac.c	/^__rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,$/;"	f	file:
__rtw89_ops_sta_state	mac80211.c	/^static int __rtw89_ops_sta_state(struct ieee80211_hw *hw,$/;"	f	file:
__rtw89_pci_check_and_reclaim_tx_fwcmd_resource	pci.c	/^u32 __rtw89_pci_check_and_reclaim_tx_fwcmd_resource(struct rtw89_dev *rtwdev)$/;"	f	file:
__rtw89_pci_check_and_reclaim_tx_resource	pci.c	/^static u32 __rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,$/;"	f	file:
__rtw89_pci_ops_flush_txchs	pci.c	/^static void __rtw89_pci_ops_flush_txchs(struct rtw89_dev *rtwdev, u32 txchs,$/;"	f	file:
__rtw89_pci_tx_kick_off	pci.c	/^static void __rtw89_pci_tx_kick_off(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring)$/;"	f	file:
__rtw89_ser_dequeue_msg	ser.c	/^static struct ser_msg *__rtw89_ser_dequeue_msg(struct rtw89_ser *ser)$/;"	f	file:
__thm_setting	rtw8852a.c	495;"	d	file:
__thm_setting	rtw8852a.c	518;"	d	file:
__txpwr_ent_byr	debug.c	/^static const struct txpwr_ent __txpwr_ent_byr[] = {$/;"	v	typeref:struct:txpwr_ent	file:
__txpwr_ent_lmt	debug.c	/^static const struct txpwr_ent __txpwr_ent_lmt[] = {$/;"	v	typeref:struct:txpwr_ent	file:
__txpwr_ent_lmt_ru	debug.c	/^static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {$/;"	v	typeref:struct:txpwr_ent	file:
__txpwr_map_byr	debug.c	/^static const struct txpwr_map __txpwr_map_byr = {$/;"	v	typeref:struct:txpwr_map	file:
__txpwr_map_lmt	debug.c	/^static const struct txpwr_map __txpwr_map_lmt = {$/;"	v	typeref:struct:txpwr_map	file:
__txpwr_map_lmt_ru	debug.c	/^static const struct txpwr_map __txpwr_map_lmt_ru = {$/;"	v	typeref:struct:txpwr_map	file:
_action_bt_a2dp	coex.c	/^static void _action_bt_a2dp(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_a2dp_hid	coex.c	/^static void _action_bt_a2dp_hid(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_a2dp_pan	coex.c	/^static void _action_bt_a2dp_pan(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_a2dp_pan_hid	coex.c	/^static void _action_bt_a2dp_pan_hid(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_a2dpsink	coex.c	/^static void _action_bt_a2dpsink(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_hfp	coex.c	/^static void _action_bt_hfp(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_hid	coex.c	/^static void _action_bt_hid(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_idle	coex.c	/^static void _action_bt_idle(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_off	coex.c	/^static void _action_bt_off(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_pan	coex.c	/^static void _action_bt_pan(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_pan_hid	coex.c	/^static void _action_bt_pan_hid(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_bt_whql	coex.c	/^static void _action_bt_whql(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_by_bt	coex.c	/^static void _action_by_bt(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_common	coex.c	/^static void _action_common(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_freerun	coex.c	/^static void _action_freerun(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_25g_mcc	coex.c	/^static void _action_wl_25g_mcc(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_ap	coex.c	/^static void _action_wl_2g_ap(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_gc	coex.c	/^static void _action_wl_2g_gc(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_go	coex.c	/^static void _action_wl_2g_go(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_mcc	coex.c	/^static void _action_wl_2g_mcc(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_nan	coex.c	/^static void _action_wl_2g_nan(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_scc	coex.c	/^static void _action_wl_2g_scc(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_2g_sta	coex.c	/^static void _action_wl_2g_sta(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_5g	coex.c	/^static void _action_wl_5g(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_init	coex.c	/^static void _action_wl_init(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_nc	coex.c	/^static void _action_wl_nc(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_off	coex.c	/^static void _action_wl_off(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_only	coex.c	/^static void _action_wl_only(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_other	coex.c	/^static void _action_wl_other(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_rfk	coex.c	/^static void _action_wl_rfk(struct rtw89_dev *rtwdev)$/;"	f	file:
_action_wl_scan	coex.c	/^static void _action_wl_scan(struct rtw89_dev *rtwdev)$/;"	f	file:
_addck	rtw8852a_rfk.c	/^static void _addck(struct rtw89_dev *rtwdev)$/;"	f	file:
_addck_backup	rtw8852a_rfk.c	/^static void _addck_backup(struct rtw89_dev *rtwdev)$/;"	f	file:
_addck_reload	rtw8852a_rfk.c	/^static void _addck_reload(struct rtw89_dev *rtwdev)$/;"	f	file:
_afe_init	rtw8852a_rfk.c	/^static void _afe_init(struct rtw89_dev *rtwdev)$/;"	f	file:
_append_slot	coex.c	/^static void _append_slot(struct rtw89_dev *rtwdev)$/;"	f	file:
_append_tdma	coex.c	/^static void _append_tdma(struct rtw89_dev *rtwdev)$/;"	f	file:
_byr_chk	phy.c	1020;"	d	file:
_byr_idx	phy.c	1019;"	d	file:
_byr_of_rs	phy.c	/^static const u8 _byr_of_rs[] = {$/;"	v	file:
_byr_seek	phy.c	1018;"	d	file:
_check_addc	rtw8852a_rfk.c	/^static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)$/;"	f	file:
_check_dadc	rtw8852a_rfk.c	/^static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)$/;"	f	file:
_check_freerun	coex.c	/^static bool _check_freerun(struct rtw89_dev *rtwdev)$/;"	f	file:
_chk_btc_err	coex.c	/^static void _chk_btc_err(struct rtw89_dev *rtwdev, u8 type, u32 cnt)$/;"	f	file:
_chk_btc_report	coex.c	/^static u32 _chk_btc_report(struct rtw89_dev *rtwdev,$/;"	f	file:
_chk_wl_rfk_request	coex.c	/^static bool _chk_wl_rfk_request(struct rtw89_dev *rtwdev)$/;"	f	file:
_dac_cal	rtw8852a_rfk.c	/^static void _dac_cal(struct rtw89_dev *rtwdev, bool force)$/;"	f	file:
_dack	rtw8852a_rfk.c	/^static void _dack(struct rtw89_dev *rtwdev)$/;"	f	file:
_dack_backup_s0	rtw8852a_rfk.c	/^static void _dack_backup_s0(struct rtw89_dev *rtwdev)$/;"	f	file:
_dack_backup_s1	rtw8852a_rfk.c	/^static void _dack_backup_s1(struct rtw89_dev *rtwdev)$/;"	f	file:
_dack_dump	rtw8852a_rfk.c	/^static void _dack_dump(struct rtw89_dev *rtwdev)$/;"	f	file:
_dack_reload	rtw8852a_rfk.c	/^static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)$/;"	f	file:
_dack_reload_by_path	rtw8852a_rfk.c	/^static void _dack_reload_by_path(struct rtw89_dev *rtwdev,$/;"	f	file:
_dack_s0	rtw8852a_rfk.c	/^static void _dack_s0(struct rtw89_dev *rtwdev)$/;"	f	file:
_dack_s1	rtw8852a_rfk.c	/^static void _dack_s1(struct rtw89_dev *rtwdev)$/;"	f	file:
_doiqk	rtw8852a_rfk.c	/^static void _doiqk(struct rtw89_dev *rtwdev, bool force,$/;"	f	file:
_dpk	rtw8852a_rfk.c	/^static void _dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool force)$/;"	f	file:
_dpk_agc	rtw8852a_rfk.c	/^static u8 _dpk_agc(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_bb_afe_restore	rtw8852a_rfk.c	/^static void _dpk_bb_afe_restore(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_bb_afe_setting	rtw8852a_rfk.c	/^static void _dpk_bb_afe_setting(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_bkup_kip	rtw8852a_rfk.c	/^static void _dpk_bkup_kip(struct rtw89_dev *rtwdev, u32 *reg,$/;"	f	file:
_dpk_bypass_check	rtw8852a_rfk.c	/^static bool _dpk_bypass_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_dpk_bypass_rxcfir	rtw8852a_rfk.c	/^static void _dpk_bypass_rxcfir(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_cal_select	rtw8852a_rfk.c	/^static void _dpk_cal_select(struct rtw89_dev *rtwdev, bool force,$/;"	f	file:
_dpk_dgain_mapping	rtw8852a_rfk.c	/^static s8 _dpk_dgain_mapping(struct rtw89_dev *rtwdev, u16 dgain)$/;"	f	file:
_dpk_dgain_read	rtw8852a_rfk.c	/^static u16 _dpk_dgain_read(struct rtw89_dev *rtwdev)$/;"	f	file:
_dpk_fill_result	rtw8852a_rfk.c	/^static void _dpk_fill_result(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_force_bypass	rtw8852a_rfk.c	/^static void _dpk_force_bypass(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_dpk_gainloss	rtw8852a_rfk.c	/^static void _dpk_gainloss(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_gainloss_read	rtw8852a_rfk.c	/^static u8 _dpk_gainloss_read(struct rtw89_dev *rtwdev)$/;"	f	file:
_dpk_get_thermal	rtw8852a_rfk.c	/^static void _dpk_get_thermal(struct rtw89_dev *rtwdev, u8 kidx,$/;"	f	file:
_dpk_idl_mpa	rtw8852a_rfk.c	/^static void _dpk_idl_mpa(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_information	rtw8852a_rfk.c	/^static void _dpk_information(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_kip_restore	rtw8852a_rfk.c	/^static void _dpk_kip_restore(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_kip_setting	rtw8852a_rfk.c	/^static void _dpk_kip_setting(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_lbk_rxiqk	rtw8852a_rfk.c	/^static void _dpk_lbk_rxiqk(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_main	rtw8852a_rfk.c	/^static bool _dpk_main(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_manual_txcfir	rtw8852a_rfk.c	/^static void _dpk_manual_txcfir(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_one_shot	rtw8852a_rfk.c	/^static u8 _dpk_one_shot(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_onoff	rtw8852a_rfk.c	/^static void _dpk_onoff(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_pas_read	rtw8852a_rfk.c	/^static u8 _dpk_pas_read(struct rtw89_dev *rtwdev, bool is_check)$/;"	f	file:
_dpk_reload_check	rtw8852a_rfk.c	/^static bool _dpk_reload_check(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_reload_kip	rtw8852a_rfk.c	/^static void _dpk_reload_kip(struct rtw89_dev *rtwdev, u32 *reg,$/;"	f	file:
_dpk_rf_setting	rtw8852a_rfk.c	/^static void _dpk_rf_setting(struct rtw89_dev *rtwdev, u8 gain,$/;"	f	file:
_dpk_rx_dck	rtw8852a_rfk.c	/^static void _dpk_rx_dck(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_set_mdpd_para	rtw8852a_rfk.c	/^static void _dpk_set_mdpd_para(struct rtw89_dev *rtwdev, u8 order)$/;"	f	file:
_dpk_set_offset	rtw8852a_rfk.c	/^static u8 _dpk_set_offset(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_set_tx_pwr	rtw8852a_rfk.c	/^static u8 _dpk_set_tx_pwr(struct rtw89_dev *rtwdev, u8 gain,$/;"	f	file:
_dpk_sync	rtw8852a_rfk.c	/^static bool _dpk_sync(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_dpk_sync_check	rtw8852a_rfk.c	/^static bool _dpk_sync_check(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_table_select	rtw8852a_rfk.c	/^static void _dpk_table_select(struct rtw89_dev *rtwdev,$/;"	f	file:
_dpk_tpg_sel	rtw8852a_rfk.c	/^void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx)$/;"	f	file:
_dpk_track	rtw8852a_rfk.c	/^static void _dpk_track(struct rtw89_dev *rtwdev)$/;"	f	file:
_dpk_tssi_pause	rtw8852a_rfk.c	/^static void _dpk_tssi_pause(struct rtw89_dev *rtwdev,$/;"	f	file:
_fw_get_rdy	fw.c	/^static u8 _fw_get_rdy(struct rtw89_dev *rtwdev)$/;"	f	file:
_fw_set_drv_info	coex.c	/^static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type)$/;"	f	file:
_fw_set_policy	coex.c	/^static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type,$/;"	f	file:
_iqk	rtw8852a_rfk.c	/^static void _iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, bool force)$/;"	f	file:
_iqk_afebb_restore	rtw8852a_rfk.c	/^static void _iqk_afebb_restore(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_by_path	rtw8852a_rfk.c	/^void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path)$/;"	f	file:
_iqk_check_cal	rtw8852a_rfk.c	/^static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype)$/;"	f	file:
_iqk_dbcc	rtw8852a_rfk.c	/^static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_get_ch_info	rtw8852a_rfk.c	/^static void _iqk_get_ch_info(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_info_iqk	rtw8852a_rfk.c	/^static void _iqk_info_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,$/;"	f	file:
_iqk_init	rtw8852a_rfk.c	/^static void _iqk_init(struct rtw89_dev *rtwdev)$/;"	f	file:
_iqk_lok	rtw8852a_rfk.c	/^static bool _iqk_lok(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_macbb_setting	rtw8852a_rfk.c	/^static void _iqk_macbb_setting(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_nbrxk	rtw8852a_rfk.c	/^static bool _iqk_nbrxk(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_nbtxk	rtw8852a_rfk.c	/^static bool _iqk_nbtxk(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_one_shot	rtw8852a_rfk.c	/^static bool _iqk_one_shot(struct rtw89_dev *rtwdev,$/;"	f	file:
_iqk_preset	rtw8852a_rfk.c	/^static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_read_fft_dbcc0	rtw8852a_rfk.c	/^static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_read_rxcfir_dbcc0	rtw8852a_rfk.c	/^static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,$/;"	f	file:
_iqk_read_txcfir_dbcc0	rtw8852a_rfk.c	/^static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path,$/;"	f	file:
_iqk_read_xym_dbcc0	rtw8852a_rfk.c	/^static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_restore	rtw8852a_rfk.c	/^static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_rxclk_setting	rtw8852a_rfk.c	/^static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_rxk_setting	rtw8852a_rfk.c	/^static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_sram	rtw8852a_rfk.c	/^static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_start_iqk	rtw8852a_rfk.c	/^static void _iqk_start_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,$/;"	f	file:
_iqk_track	rtw8852a_rfk.c	/^static void _iqk_track(struct rtw89_dev *rtwdev)$/;"	f	file:
_iqk_txclk_setting	rtw8852a_rfk.c	/^static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_iqk_txk_setting	rtw8852a_rfk.c	/^static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_kpath	rtw8852a_rfk.c	/^static u8 _kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)$/;"	f	file:
_lok_finetune_check	rtw8852a_rfk.c	/^static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path)$/;"	f	file:
_lok_res_table	rtw8852a_rfk.c	/^static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias)$/;"	f	file:
_ntfy_wl_rfk	coex.c	/^static bool _ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_path,$/;"	f	file:
_parse_btc_report	coex.c	/^static void _parse_btc_report(struct rtw89_dev *rtwdev,$/;"	f	file:
_patch_dis_resp_chk	mac.c	/^static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
_phy_txpwr_rf_to_mac	phy.c	1043;"	d	file:
_rck	rtw8852a_rfk.c	/^static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path)$/;"	f	file:
_read_scbd	coex.c	/^static u32 _read_scbd(struct rtw89_dev *rtwdev)$/;"	f	file:
_reset_btc_var	coex.c	/^static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type)$/;"	f	file:
_rf_direct_cntrl	rtw8852a_rfk.c	/^static void _rf_direct_cntrl(struct rtw89_dev *rtwdev,$/;"	f	file:
_rfk_backup_bb_reg	rtw8852a_rfk.c	/^static void _rfk_backup_bb_reg(struct rtw89_dev *rtwdev, u32 backup_bb_reg_val[])$/;"	f	file:
_rfk_backup_rf_reg	rtw8852a_rfk.c	/^static void _rfk_backup_rf_reg(struct rtw89_dev *rtwdev, u32 backup_rf_reg_val[],$/;"	f	file:
_rfk_delay	rtw8852a_rfk.c	/^_rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)$/;"	f	file:
_rfk_handler	rtw8852a_rfk.c	/^(*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {$/;"	v	file:
_rfk_restore_bb_reg	rtw8852a_rfk.c	/^static void _rfk_restore_bb_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
_rfk_restore_rf_reg	rtw8852a_rfk.c	/^static void _rfk_restore_rf_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
_rfk_write32_clr	rtw8852a_rfk.c	/^_rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)$/;"	f	file:
_rfk_write32_mask	rtw8852a_rfk.c	/^_rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)$/;"	f	file:
_rfk_write32_set	rtw8852a_rfk.c	/^_rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)$/;"	f	file:
_rfk_write_rf	rtw8852a_rfk.c	/^_rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)$/;"	f	file:
_rtw8852a_tssi_avg_scan	rtw8852a_rfk.c	/^void _rtw8852a_tssi_avg_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_rtw8852a_tssi_set_avg	rtw8852a_rfk.c	/^void _rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_rtw89_mac_bf_monitor_track	mac.c	/^void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)$/;"	f
_run_coex	coex.c	/^void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason)$/;"	f	file:
_rx_dck	rtw8852a_rfk.c	/^static void _rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_rxk_group_sel	rtw8852a_rfk.c	/^static bool _rxk_group_sel(struct rtw89_dev *rtwdev,$/;"	f	file:
_send_fw_cmd	coex.c	/^static void _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func,$/;"	f	file:
_set_ant	coex.c	/^static void _set_ant(struct rtw89_dev *rtwdev, bool force_exec,$/;"	f	file:
_set_bt_afh_info	coex.c	/^static void _set_bt_afh_info(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_bt_ignore_wlan_act	coex.c	/^static void _set_bt_ignore_wlan_act(struct rtw89_dev *rtwdev, u8 enable)$/;"	f	file:
_set_bt_plut	coex.c	/^static void _set_bt_plut(struct rtw89_dev *rtwdev, u8 phy_map,$/;"	f	file:
_set_bt_rx_agc	coex.c	/^static void _set_bt_rx_agc(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_bt_rx_gain	coex.c	/^static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level)$/;"	f	file:
_set_bt_tx_power	coex.c	/^static void _set_bt_tx_power(struct rtw89_dev *rtwdev, u8 level)$/;"	f	file:
_set_btg_ctrl	coex.c	/^static void _set_btg_ctrl(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_gnt_bt	coex.c	/^static void _set_gnt_bt(struct rtw89_dev *rtwdev, u8 phy_map, u8 state)$/;"	f	file:
_set_gnt_wl	coex.c	/^static void _set_gnt_wl(struct rtw89_dev *rtwdev, u8 phy_map, u8 state)$/;"	f	file:
_set_init_info	coex.c	/^static void _set_init_info(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_policy	coex.c	/^static void _set_policy(struct rtw89_dev *rtwdev, u16 policy_type,$/;"	f	file:
_set_rf_trx_para	coex.c	/^static void _set_rf_trx_para(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_rx_dck	rtw8852a_rfk.c	/^static void _set_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_set_wl_rx_gain	coex.c	/^static void _set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)$/;"	f	file:
_set_wl_tx_limit	coex.c	/^static void _set_wl_tx_limit(struct rtw89_dev *rtwdev)$/;"	f	file:
_set_wl_tx_power	coex.c	/^static void _set_wl_tx_power(struct rtw89_dev *rtwdev, u32 level)$/;"	f	file:
_show_bt_info	coex.c	/^static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_bt_profile_info	coex.c	/^static void _show_bt_profile_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_cx_info	coex.c	/^static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_dm_info	coex.c	/^static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_dm_step	coex.c	/^static void _show_dm_step(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_error	coex.c	/^static void _show_error(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fbtc_cysta	coex.c	/^static void _show_fbtc_cysta(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fbtc_nullsta	coex.c	/^static void _show_fbtc_nullsta(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fbtc_slots	coex.c	/^static void _show_fbtc_slots(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fbtc_step	coex.c	/^static void _show_fbtc_step(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fbtc_tdma	coex.c	/^static void _show_fbtc_tdma(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_fw_dm_msg	coex.c	/^static void _show_fw_dm_msg(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_mreg	coex.c	/^static void _show_mreg(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_summary	coex.c	/^static void _show_summary(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_wl_info	coex.c	/^static void _show_wl_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_show_wl_role_info	coex.c	/^static void _show_wl_role_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f	file:
_slot_set	coex.c	1793;"	d	file:
_slot_set_dur	coex.c	1802;"	d	file:
_slot_set_tbl	coex.c	1803;"	d	file:
_slot_set_type	coex.c	1804;"	d	file:
_tdma_set_flctrl	coex.c	1789;"	d	file:
_tdma_set_lek	coex.c	1791;"	d	file:
_tdma_set_tog	coex.c	1790;"	d	file:
_tssi_disable	rtw8852a_rfk.c	/^static void _tssi_disable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_tssi_enable	rtw8852a_rfk.c	/^static void _tssi_enable(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_tssi_get_cck_group	rtw8852a_rfk.c	/^static u32 _tssi_get_cck_group(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
_tssi_get_ofdm_de	rtw8852a_rfk.c	/^static s8 _tssi_get_ofdm_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_get_ofdm_group	rtw8852a_rfk.c	/^static u32 _tssi_get_ofdm_group(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
_tssi_get_ofdm_trim_de	rtw8852a_rfk.c	/^static s8 _tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,$/;"	f	file:
_tssi_get_trim_group	rtw8852a_rfk.c	/^static u32 _tssi_get_trim_group(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
_tssi_high_power	rtw8852a_rfk.c	/^static void _tssi_high_power(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_tssi_hw_tx	rtw8852a_rfk.c	/^static void _tssi_hw_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_ini_txpwr_ctrl_bb	rtw8852a_rfk.c	/^static void _tssi_ini_txpwr_ctrl_bb(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_ini_txpwr_ctrl_bb_he_tb	rtw8852a_rfk.c	/^static void _tssi_ini_txpwr_ctrl_bb_he_tb(struct rtw89_dev *rtwdev,$/;"	f	file:
_tssi_pak	rtw8852a_rfk.c	/^static void _tssi_pak(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_pre_tx	rtw8852a_rfk.c	/^static void _tssi_pre_tx(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_tssi_rf_setting	rtw8852a_rfk.c	/^static void _tssi_rf_setting(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_dac_gain_tbl	rtw8852a_rfk.c	/^static void _tssi_set_dac_gain_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_dck	rtw8852a_rfk.c	/^static void _tssi_set_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_efuse_to_de	rtw8852a_rfk.c	/^static void _tssi_set_efuse_to_de(struct rtw89_dev *rtwdev,$/;"	f	file:
_tssi_set_rf_gap_tbl	rtw8852a_rfk.c	/^static void _tssi_set_rf_gap_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_slope	rtw8852a_rfk.c	/^static void _tssi_set_slope(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_sys	rtw8852a_rfk.c	/^static void _tssi_set_sys(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f	file:
_tssi_set_tmeter_tbl	rtw8852a_rfk.c	/^static void _tssi_set_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_track	rtw8852a_rfk.c	/^static void _tssi_set_track(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_set_txagc_offset_mv_avg	rtw8852a_rfk.c	/^static void _tssi_set_txagc_offset_mv_avg(struct rtw89_dev *rtwdev,$/;"	f	file:
_tssi_slope_cal_org	rtw8852a_rfk.c	/^static void _tssi_slope_cal_org(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy,$/;"	f	file:
_tssi_track	rtw8852a_rfk.c	/^static void _tssi_track(struct rtw89_dev *rtwdev)$/;"	f	file:
_txk_group_sel	rtw8852a_rfk.c	/^static bool _txk_group_sel(struct rtw89_dev *rtwdev,$/;"	f	file:
_txpwr_track_delta_swingidx_2g_cck_a_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2g_cck_a_n[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2g_cck_a_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2g_cck_a_p[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2g_cck_b_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2g_cck_b_n[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2g_cck_b_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2g_cck_b_p[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2ga_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2ga_n[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2ga_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2ga_p[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2gb_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2gb_n[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_2gb_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_2gb_p[] = {$/;"	v	file:
_txpwr_track_delta_swingidx_5ga_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_5ga_n[][DELTA_SWINGIDX_SIZE] = {$/;"	v	file:
_txpwr_track_delta_swingidx_5ga_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_5ga_p[][DELTA_SWINGIDX_SIZE] = {$/;"	v	file:
_txpwr_track_delta_swingidx_5gb_n	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_5gb_n[][DELTA_SWINGIDX_SIZE] = {$/;"	v	file:
_txpwr_track_delta_swingidx_5gb_p	rtw8852a_table.c	/^static const u8 _txpwr_track_delta_swingidx_5gb_p[][DELTA_SWINGIDX_SIZE] = {$/;"	v	file:
_update_bt_info	coex.c	/^static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len)$/;"	f	file:
_update_bt_report	coex.c	/^static void _update_bt_report(struct rtw89_dev *rtwdev, u8 rpt_type, u8 *pfinfo)$/;"	f	file:
_update_bt_scbd	coex.c	/^static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update)$/;"	f	file:
_update_btc_state_map	coex.c	/^static void _update_btc_state_map(struct rtw89_dev *rtwdev)$/;"	f	file:
_update_dbcc_band	coex.c	/^void _update_dbcc_band(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)$/;"	f	file:
_update_dm_step	coex.c	/^static void _update_dm_step(struct rtw89_dev *rtwdev,$/;"	f	file:
_update_rssi_state	coex.c	/^_update_rssi_state(struct rtw89_dev *rtwdev, u8 pre_state, u8 rssi, u8 thresh)$/;"	f	file:
_update_wl_info	coex.c	/^static void _update_wl_info(struct rtw89_dev *rtwdev)$/;"	f	file:
_wait_rx_mode	rtw8852a_rfk.c	/^static void _wait_rx_mode(struct rtw89_dev *rtwdev, u8 kpath)$/;"	f	file:
_write_scbd	coex.c	/^static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state)$/;"	f	file:
a2dp	coex.c	/^	u8 a2dp: 1;$/;"	m	struct:btc_btinfo_lb2	file:
a2dp_active	coex.c	/^	u8 a2dp_active: 1;$/;"	m	struct:btc_btinfo_hb2	file:
a2dp_bitpool	coex.c	/^	u8 a2dp_bitpool: 6;$/;"	m	struct:btc_btinfo_hb3	file:
a2dp_desc	core.h	/^	struct rtw89_btc_bt_a2dp_desc a2dp_desc;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bt_a2dp_desc
a2dp_sink	coex.c	/^	u8 a2dp_sink: 1;$/;"	m	struct:btc_btinfo_hb3	file:
a2dpept	coex.c	/^	u16 a2dpept;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
a2dpept	core.h	/^	__le16 a2dpept; \/* a2dp empty cnt *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
a2dpeptto	coex.c	/^	u16 a2dpeptto;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
a2dpeptto	core.h	/^	__le16 a2dpeptto; \/* a2dp empty timeout cnt*\/$/;"	m	struct:rtw89_btc_fbtc_cysta
a_ctrl_bsr	core.h	/^	bool a_ctrl_bsr;$/;"	m	struct:rtw89_tx_desc_info
ac_mode	rtw8852a.h	/^	u8 ac_mode:1;$/;"	m	struct:rtw8852a_efuse
ac_to_fw_idx	mac80211.c	/^static const u8 ac_to_fw_idx[IEEE80211_NUM_ACS] = {$/;"	v	file:
ac_to_mu_edca_param	mac80211.c	/^static const u32 ac_to_mu_edca_param[IEEE80211_NUM_ACS] = {$/;"	v	file:
acam_num	core.h	/^	u8 acam_num;$/;"	m	struct:rtw89_chip_info
ack	fw.h	/^	u32 ack:1;$/;"	m	struct:rtw89_c2h_phy_cap
ack	fw.h	/^	u8 ack:1;$/;"	m	struct:rtw89_h2creg_sch_tx_en
acl_busy	coex.c	/^	u8 acl_busy: 1;$/;"	m	struct:btc_btinfo_lb2	file:
acl_busy	core.h	/^	u32 acl_busy: 1;$/;"	m	struct:rtw89_btc_bt_smap
active	core.h	/^	u32 active: 1;$/;"	m	struct:rtw89_btc_bt_pan_desc
active	core.h	/^	u32 active: 1;$/;"	m	struct:rtw89_btc_wl_link_info
active	core.h	/^	u8 active: 1;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
active_role	core.h	/^	struct rtw89_btc_wl_active_role active_role[RTW89_MAX_HW_PORT_NUM];$/;"	m	struct:rtw89_btc_wl_role_info	typeref:struct:rtw89_btc_wl_role_info::rtw89_btc_wl_active_role
addck_d	core.h	/^	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];$/;"	m	struct:rtw89_dack_info
addck_timeout	core.h	/^	bool addck_timeout[RTW89_DACK_PATH_NR];$/;"	m	struct:rtw89_dack_info
addr	core.h	/^	u32 addr;$/;"	m	struct:rtw89_reg2_def
addr	core.h	/^	u32 addr;$/;"	m	struct:rtw89_reg3_def
addr	core.h	/^	u32 addr;$/;"	m	struct:rtw89_reg5_def
addr	core.h	/^	u32 addr;$/;"	m	struct:rtw89_reg_def
addr	core.h	/^	u8 addr[ETH_ALEN];$/;"	m	struct:rtw89_efuse
addr	debug.c	/^			u32 addr;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon2	file:
addr	debug.c	/^			u32 addr;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon3	file:
addr	fw.h	/^	const u8 *addr;$/;"	m	struct:rtw89_fw_hdr_section_info
addr	mac.h	/^	u16 addr;$/;"	m	struct:rtw89_pwr_cfg
addr	mac.h	/^	u32 addr;$/;"	m	struct:rtw89_mac_dle_dfi_ctrl
addr1_match	core.h	/^	bool addr1_match;$/;"	m	struct:rtw89_rx_desc_info
addr_bdram	pci.h	/^	u32 addr_bdram;$/;"	m	struct:rtw89_pci_dma_ring
addr_cam	core.h	/^	struct rtw89_addr_cam_entry addr_cam;$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::rtw89_addr_cam_entry
addr_cam_id	core.h	/^	u8 addr_cam_id;$/;"	m	struct:rtw89_rx_desc_info
addr_cam_idx	core.h	/^	u8 addr_cam_idx;$/;"	m	struct:rtw89_addr_cam_entry
addr_cam_init	mac.c	/^static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
addr_cam_valid	core.h	/^	bool addr_cam_valid;$/;"	m	struct:rtw89_rx_desc_info
addr_desa_h	pci.h	/^	u32 addr_desa_h;$/;"	m	struct:rtw89_pci_dma_ring
addr_desa_l	pci.h	/^	u32 addr_desa_l;$/;"	m	struct:rtw89_pci_dma_ring
addr_from	debug.c	/^	u32 addr_from;$/;"	m	struct:txpwr_map	file:
addr_idx	pci.h	/^	u32 addr_idx;$/;"	m	struct:rtw89_pci_dma_ring
addr_mask	core.h	/^	u8 addr_mask	: 6;$/;"	m	struct:rtw89_addr_cam_entry
addr_num	pci.h	/^	u32 addr_num;$/;"	m	struct:rtw89_pci_dma_ring
addr_to	debug.c	/^	u32 addr_to;$/;"	m	struct:txpwr_map	file:
adhoc	core.h	/^	u16 adhoc: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
adhoc_master	core.h	/^	u16 adhoc_master: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
afh_guard_ch	core.h	/^	u8 afh_guard_ch;$/;"	m	struct:rtw89_chip_info
afh_h	core.h	/^	u8 afh_h[4]; \/*bit0:2466, bit1:2467......bit14:2480 *\/$/;"	m	struct:rtw89_btc_fbtc_btafh
afh_info	core.h	/^	struct rtw89_btc_wl_afh_info afh_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_afh_info
afh_l	core.h	/^	u8 afh_l[4]; \/*bit0:2402, bit1: 2403.... bit31:2433 *\/$/;"	m	struct:rtw89_btc_fbtc_btafh
afh_m	core.h	/^	u8 afh_m[4]; \/*bit0:2434, bit1: 2435.... bit31:2465 *\/$/;"	m	struct:rtw89_btc_fbtc_btafh
afh_map	core.h	/^	u8 afh_map[BTC_BT_AFH_GROUP];$/;"	m	struct:rtw89_btc_bt_link_info
afh_update	coex.c	/^	u8 afh_update: 1;$/;"	m	struct:btc_btinfo_hb2	file:
afh_update	core.h	/^	u32 afh_update: 1;$/;"	m	struct:rtw89_btc_bt_link_info
agg_en	core.h	/^	bool agg_en;$/;"	m	struct:rtw89_tx_desc_info
agg_num	core.h	/^	u16 agg_num;$/;"	m	struct:rtw89_ampdu_params
alarm_event	core.h	/^	u8 alarm_event;$/;"	m	struct:rtw89_ser
alpha2	core.h	/^	char alpha2[3];$/;"	m	struct:rtw89_regulatory
always_freerun	core.h	/^	u32 always_freerun: 1;$/;"	m	struct:rtw89_btc_ctrl
ampdu_density	core.h	/^	u8 ampdu_density;$/;"	m	struct:rtw89_tx_desc_info
ampdu_max_time	core.h	/^	u32 ampdu_max_time:4;$/;"	m	struct:rtw89_sta
ampdu_num	core.h	/^	u8 ampdu_num;$/;"	m	struct:rtw89_tx_desc_info
ampdu_params	core.h	/^	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::rtw89_ampdu_params
amsdu	core.h	/^	bool amsdu;$/;"	m	struct:rtw89_ampdu_params
ant	core.h	/^	struct rtw89_btc_ant_info ant;$/;"	m	struct:rtw89_btc_module	typeref:struct:rtw89_btc_module::rtw89_btc_ant_info
ant_iso	rtw8852a.h	/^	u8 ant_iso:1;$/;"	m	struct:rtw8852a_efuse
antenna_rx	core.h	/^	u32 antenna_rx;$/;"	m	struct:rtw89_hal
antenna_tx	core.h	/^	u32 antenna_tx;$/;"	m	struct:rtw89_hal
ap	core.h	/^			struct ieee80211_sta *ap;$/;"	m	struct:rtw89_vif::__anon11::__anon12	typeref:struct:rtw89_vif::__anon11::__anon12::ieee80211_sta
ap	core.h	/^		} ap;$/;"	m	union:rtw89_vif::__anon11	typeref:struct:rtw89_vif::__anon11::__anon13
ap	core.h	/^	u16 ap: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
apply_compensation	core.h	/^	bool apply_compensation;$/;"	m	struct:rtw89_cfo_tracking_info
arp_notify_work	core.h	/^	struct work_struct arp_notify_work;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::work_struct
aval	core.h	/^	u16 aval;$/;"	m	struct:rtw89_hfc_ch_info
avg_rssi	core.h	/^	struct ewma_rssi avg_rssi;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::ewma_rssi
avg_t	core.h	/^	__le32 avg_t[2]; \/* avg_t for 0:null0\/1:null1 *\/$/;"	m	struct:rtw89_btc_fbtc_cynullsta
avg_thermal	core.h	/^	struct ewma_thermal avg_thermal[RF_PATH_MAX];$/;"	m	struct:rtw89_phy_stat	typeref:struct:rtw89_phy_stat::ewma_thermal
b1_hang	core.h	/^	u32 b1_hang: 1;$/;"	m	struct:rtw89_btc_dm_emap
ba_list	core.h	/^	struct list_head ba_list;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::list_head
ba_lock	core.h	/^	spinlock_t ba_lock;$/;"	m	struct:rtw89_dev
ba_work	core.h	/^	struct work_struct ba_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::work_struct
band	core.h	/^	enum rtw89_band band;$/;"	m	struct:rtw89_dpk_bkup_para	typeref:enum:rtw89_dpk_bkup_para::rtw89_band
band	core.h	/^	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];$/;"	m	struct:rtw89_mac_ax_coex_gnt	typeref:struct:rtw89_mac_ax_coex_gnt::rtw89_mac_ax_gnt
band	core.h	/^	u32 band: 2;$/;"	m	struct:rtw89_btc_wl_rfk_info
band	core.h	/^	u8 band: 2;$/;"	m	struct:rtw89_btc_wl_active_role
band	core.h	/^	u8 band;$/;"	m	struct:rtw89_btc_wl_link_info
band	core.h	/^	u8 band[RTW89_PHY_MAX];$/;"	m	struct:rtw89_btc_wl_scan_info
band	fw.h	/^	u8 band:1;$/;"	m	struct:rtw89_h2creg_sch_tx_en
band	mac.h	/^	u8 band;$/;"	m	struct:rtw89_mac_ax_plt
band	phy.h	/^	enum rtw89_band band;$/;"	m	struct:rtw89_txpwr_byrate_cfg	typeref:enum:rtw89_txpwr_byrate_cfg::rtw89_band
band1_enable	mac.c	/^static int band1_enable(struct rtw89_dev *rtwdev)$/;"	f	file:
band_idle_ck_b	mac.c	/^static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
band_num	core.h	/^	u8 band_num;$/;"	m	struct:rtw89_ra_info
bandwidth	core.h	/^	u8 bandwidth;$/;"	m	struct:rtw89_channel_params
base	mac.h	/^	u8 base:4;$/;"	m	struct:rtw89_pwr_cfg
base_thermal	core.h	/^	u32 base_thermal[RF_PATH_MAX];$/;"	m	struct:rtw89_tssi_info
bb	core.h	/^	u32 bb;$/;"	m	struct:rtw89_btc_wl_ver_info
bb_ctrl_btc_preagc	core.h	/^	void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);$/;"	m	struct:rtw89_chip_ops
bb_reset	core.h	/^	void (*bb_reset)(struct rtw89_dev *rtwdev,$/;"	m	struct:rtw89_chip_ops
bb_rpt	core.h	/^	u16 bb_rpt;$/;"	m	struct:rtw89_ple_quota
bb_sel	core.h	/^	bool bb_sel;$/;"	m	struct:rtw89_rx_desc_info
bb_sethw	core.h	/^	void (*bb_sethw)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
bb_table	core.h	/^	const struct rtw89_phy_table *bb_table;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_phy_table
bcam_num	core.h	/^	u8 bcam_num;$/;"	m	struct:rtw89_chip_info
bcn_area	core.h	/^	u32 bcn_area;$/;"	m	struct:rtw89_port_reg
bcn_cnt	coex.c	/^	u32 bcn_cnt[CXBCN_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
bcn_cnt	core.h	/^	__le32 bcn_cnt[CXBCN_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta
bcn_cnt_tmr	core.h	/^	u32 bcn_cnt_tmr;$/;"	m	struct:rtw89_port_reg
bcn_early	core.h	/^	u32 bcn_early;$/;"	m	struct:rtw89_port_reg
bcn_err_cnt	core.h	/^	u32 bcn_err_cnt;$/;"	m	struct:rtw89_port_reg
bcn_err_flag	core.h	/^	u32 bcn_err_flag;$/;"	m	struct:rtw89_port_reg
bcn_forcetx	core.h	/^	u32 bcn_forcetx;$/;"	m	struct:rtw89_port_reg
bcn_hit_cond	core.h	/^	u8 bcn_hit_cond;$/;"	m	struct:rtw89_vif
bcn_period	core.h	/^	u32 bcn_period;$/;"	m	struct:rtw89_btc_wl_link_info
bcn_space	core.h	/^	u32 bcn_space;$/;"	m	struct:rtw89_port_reg
bd_ram_table	pci.c	/^static const struct rtw89_pci_bd_ram bd_ram_table[RTW89_TXCH_NUM] = {$/;"	v	typeref:struct:rtw89_pci_bd_ram	file:
bd_ring	pci.h	/^	struct rtw89_pci_dma_ring bd_ring;$/;"	m	struct:rtw89_pci_rx_ring	typeref:struct:rtw89_pci_rx_ring::rtw89_pci_dma_ring
bd_ring	pci.h	/^	struct rtw89_pci_dma_ring bd_ring;$/;"	m	struct:rtw89_pci_tx_ring	typeref:struct:rtw89_pci_tx_ring::rtw89_pci_dma_ring
beacon_nr	core.h	/^	u16 beacon_nr;$/;"	m	struct:rtw89_pkt_stat
biask_d	core.h	/^	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];$/;"	m	struct:rtw89_dack_info
bit_rate	core.h	/^	u32 bit_rate;$/;"	m	struct:rtw89_ra_report
bitpool	core.h	/^	u8 bitpool;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
bk	core.h	/^	bool bk;$/;"	m	struct:rtw89_tx_desc_info
ble_connect	coex.c	/^	u8 ble_connect: 1;$/;"	m	struct:btc_btinfo_hb1	file:
ble_connect	core.h	/^	u32 ble_connect: 1;$/;"	m	struct:rtw89_btc_bt_smap
ble_scan	coex.c	/^	u8 ble_scan: 1;$/;"	m	struct:btc_btinfo_hb1	file:
ble_scan_en	core.h	/^	u32 ble_scan_en: 1;$/;"	m	struct:rtw89_btc_bt_info
block_idx_to_logical_idx	efuse.c	66;"	d	file:
bp	core.h	/^	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];$/;"	m	struct:rtw89_dpk_info	typeref:struct:rtw89_dpk_info::rtw89_dpk_bkup_para
bp_iqkenable	core.h	/^	u32 bp_iqkenable[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
bp_rxkresult	core.h	/^	u32 bp_rxkresult[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
bp_txkresult	core.h	/^	u32 bp_txkresult[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
bssid	core.c	/^	const u8 *bssid;$/;"	m	struct:rtw89_vif_rx_stats_iter_data	file:
bssid	core.h	/^	u8 bssid[ETH_ALEN];$/;"	m	struct:rtw89_bssid_cam_entry
bssid	core.h	/^	u8 bssid[ETH_ALEN];$/;"	m	struct:rtw89_vif
bssid_cam	core.h	/^	struct rtw89_bssid_cam_entry bssid_cam;$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::rtw89_bssid_cam_entry
bssid_cam_idx	core.h	/^	u8 bssid_cam_idx: 6;$/;"	m	struct:rtw89_addr_cam_entry
bssid_cam_idx	core.h	/^	u8 bssid_cam_idx;$/;"	m	struct:rtw89_bssid_cam_entry
bt	core.h	/^	struct rtw89_btc_bt_info bt;$/;"	m	struct:rtw89_btc_cx	typeref:struct:rtw89_btc_cx::rtw89_btc_bt_info
bt_only	core.h	/^	u32 bt_only: 1;$/;"	m	struct:rtw89_btc_dm
bt_only	core.h	/^	u8 bt_only: 1;$/;"	m	struct:rtw89_btc_init_info
bt_pos	core.h	/^	u8 bt_pos: 1;$/;"	m	struct:rtw89_btc_module
bt_req_en	core.h	/^	bool bt_req_en;$/;"	m	struct:rtw89_btc
bt_req_len	core.h	/^	u32 bt_req_len;$/;"	m	struct:rtw89_btc
bt_rfk_cnt	core.h	/^	u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
bt_rfk_timeout	core.h	/^	u32 bt_rfk_timeout: 1;$/;"	m	struct:rtw89_btc_dm_emap
bt_rssi_thres	core.h	/^	const u8 *bt_rssi_thres;$/;"	m	struct:rtw89_chip_info
bt_rx_gain	core.h	/^	u8 bt_rx_gain;  \/* LNA constrain level *\/$/;"	m	struct:rtw89_btc_rf_trx_para
bt_solo	core.h	/^	u8 bt_solo: 1;$/;"	m	struct:rtw89_btc_module
bt_tx_power	core.h	/^	u8 bt_tx_power; \/* decrease Tx power (dB) *\/$/;"	m	struct:rtw89_btc_rf_trx_para
btc	core.h	/^	struct rtw89_btc btc;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_btc
btc_ant	coex.h	/^enum btc_ant {$/;"	g
btc_ant_phase	coex.c	/^enum btc_ant_phase {$/;"	g	file:
btc_b2w_scoreboard	coex.c	/^enum btc_b2w_scoreboard {$/;"	g	file:
btc_bt_a2dp_type	coex.c	/^enum btc_bt_a2dp_type {$/;"	g	file:
btc_bt_aci_imp	core.h	/^	void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
btc_bt_btg	coex.h	/^enum btc_bt_btg {$/;"	g
btc_bt_hid_type	coex.c	/^enum btc_bt_hid_type {$/;"	g	file:
btc_bt_mailbox_id	coex.h	/^enum btc_bt_mailbox_id {$/;"	g
btc_bt_trs	coex.h	/^enum btc_bt_trs {$/;"	g
btc_btf_set_cx_policy	coex.c	/^enum btc_btf_set_cx_policy {$/;"	g	file:
btc_btf_set_report_en	coex.c	/^enum btc_btf_set_report_en {$/;"	g	file:
btc_btinfo	coex.c	/^union btc_btinfo {$/;"	u	file:
btc_btinfo_hb0	coex.c	/^struct btc_btinfo_hb0 {$/;"	s	file:
btc_btinfo_hb1	coex.c	/^struct btc_btinfo_hb1 {$/;"	s	file:
btc_btinfo_hb2	coex.c	/^struct btc_btinfo_hb2 {$/;"	s	file:
btc_btinfo_hb3	coex.c	/^struct btc_btinfo_hb3 {$/;"	s	file:
btc_btinfo_lb2	coex.c	/^struct btc_btinfo_lb2 {$/;"	s	file:
btc_btinfo_lb3	coex.c	/^struct btc_btinfo_lb3 {$/;"	s	file:
btc_coex_info_map_en	coex.c	/^enum btc_coex_info_map_en {$/;"	g	file:
btc_cx_poicy_main_type	coex.c	/^enum btc_cx_poicy_main_type {$/;"	g	file:
btc_cx_poicy_type	coex.c	/^enum btc_cx_poicy_type {$/;"	g	file:
btc_cx_state_map	coex.c	/^enum btc_cx_state_map {$/;"	g	file:
btc_fbtc_1slot	coex.c	/^struct btc_fbtc_1slot {$/;"	s	file:
btc_fbtc_tdma_rx_flow_ctrl	coex.c	/^enum btc_fbtc_tdma_rx_flow_ctrl {$/;"	g	file:
btc_fbtc_tdma_template	coex.c	/^enum btc_fbtc_tdma_template {$/;"	g	file:
btc_fbtc_tdma_type	coex.c	/^enum btc_fbtc_tdma_type {$/;"	g	file:
btc_fbtc_tdma_wlan_tx_pause	coex.c	/^enum btc_fbtc_tdma_wlan_tx_pause {$/;"	g	file:
btc_fw_event	coex.c	/^void btc_fw_event(struct rtw89_dev *rtwdev, u8 evt_id, void *data, u32 len)$/;"	f	file:
btc_fw_set_monreg	coex.c	/^static void btc_fw_set_monreg(struct rtw89_dev *rtwdev)$/;"	f	file:
btc_get_bt_rssi	core.h	/^	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);$/;"	m	struct:rtw89_chip_ops
btc_gnt_state	coex.c	/^enum btc_gnt_state {$/;"	g	file:
btc_init_cfg	core.h	/^	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
btc_mlme_state	coex.c	/^enum btc_mlme_state {$/;"	g	file:
btc_mode	coex.h	/^enum btc_mode {$/;"	g
btc_phymap	coex.c	/^enum btc_phymap {$/;"	g	file:
btc_pkt_type	coex.h	/^enum btc_pkt_type {$/;"	g
btc_plt	coex.c	/^enum btc_plt {$/;"	g	file:
btc_pri	coex.h	/^enum btc_pri {$/;"	g
btc_reason_and_action	coex.c	/^enum btc_reason_and_action {$/;"	g	file:
btc_reset_module	coex.c	/^enum btc_reset_module {$/;"	g	file:
btc_rfctrl	coex.h	/^enum btc_rfctrl {$/;"	g
btc_role_state	coex.h	/^enum btc_role_state {$/;"	g
btc_rssi_st	coex.h	/^enum btc_rssi_st {$/;"	g
btc_set_rfe	core.h	/^	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
btc_set_wl_pri	core.h	/^	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);$/;"	m	struct:rtw89_chip_ops
btc_set_wl_txpwr_ctrl	core.h	/^	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);$/;"	m	struct:rtw89_chip_ops
btc_slot_type	core.h	/^enum btc_slot_type {$/;"	g
btc_switch	coex.h	/^enum btc_switch {$/;"	g
btc_update_bt_cnt	core.h	/^	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
btc_w2b_scoreboard	coex.c	/^enum btc_w2b_scoreboard {$/;"	g	file:
btc_wl_link_mode	coex.c	/^enum btc_wl_link_mode {$/;"	g	file:
btc_wl_max_tx_retry	coex.c	/^enum btc_wl_max_tx_retry {$/;"	g	file:
btc_wl_max_tx_time	coex.c	/^enum btc_wl_max_tx_time {$/;"	g	file:
btc_wl_mode	coex.c	/^enum btc_wl_mode {$/;"	g	file:
btc_wl_rfk_result	coex.c	/^enum btc_wl_rfk_result {$/;"	g	file:
btc_wl_rfk_state	coex.h	/^enum btc_wl_rfk_state {$/;"	g
btc_wl_rfk_type	coex.h	/^enum btc_wl_rfk_type {$/;"	g
btc_wl_s1_standby	core.h	/^	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);$/;"	m	struct:rtw89_chip_ops
btcx_desired	core.h	/^	u8 btcx_desired;$/;"	m	struct:rtw89_chip_info
btf_fw_event_report	core.h	/^enum btf_fw_event_report {$/;"	g
btg_type	core.h	/^	u32 btg_type: 1;$/;"	m	struct:rtw89_btc_bt_info
buf	coex.c	/^	u8 buf[];$/;"	m	struct:rtw89_btc_btf_set_mon_reg	file:
buf	coex.c	/^	u8 buf[];$/;"	m	struct:rtw89_btc_btf_set_slot_table	file:
buf	core.h	/^	u8 *buf;$/;"	m	struct:rtw89_rx_phy_ppdu
buf	pci.h	/^	struct sk_buff *buf[RTW89_PCI_RXBD_NUM_MAX];$/;"	m	struct:rtw89_pci_rx_ring	typeref:struct:rtw89_pci_rx_ring::sk_buff
buf_size	pci.h	/^	__le16 buf_size;$/;"	m	struct:rtw89_pci_rx_bd_32
buf_sz	pci.h	/^	u32 buf_sz;$/;"	m	struct:rtw89_pci_rx_ring
build_date	core.h	/^	u16 build_date;$/;"	m	struct:rtw89_fw_suit
build_hour	core.h	/^	u16 build_hour;$/;"	m	struct:rtw89_fw_suit
build_min	core.h	/^	u16 build_min;$/;"	m	struct:rtw89_fw_suit
build_mon	core.h	/^	u16 build_mon;$/;"	m	struct:rtw89_fw_suit
build_year	core.h	/^	u16 build_year;$/;"	m	struct:rtw89_fw_suit
busy	core.h	/^	u32 busy: 1;$/;"	m	struct:rtw89_btc_wl_smap
busy	core.h	/^	u8 busy;$/;"	m	struct:rtw89_btc_wl_link_info
busy_all	coex.c	/^	u8 busy_all;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	file:
busy_pages	pci.h	/^	struct list_head busy_pages;$/;"	m	struct:rtw89_pci_tx_ring	typeref:struct:rtw89_pci_tx_ring::list_head
busy_t	core.h	/^	u32 busy_t;$/;"	m	struct:rtw89_btc_wl_link_info
bw	core.h	/^	enum rtw89_bandwidth bw;$/;"	m	struct:rtw89_dpk_bkup_para	typeref:enum:rtw89_dpk_bkup_para::rtw89_bandwidth
bw	core.h	/^	u8 bw: 7;$/;"	m	struct:rtw89_btc_wl_active_role
bw	core.h	/^	u8 bw;$/;"	m	struct:rtw89_btc_wl_afh_info
bw	core.h	/^	u8 bw;$/;"	m	struct:rtw89_btc_wl_link_info
bw	core.h	/^	u8 bw;$/;"	m	struct:rtw89_rx_desc_info
bw	fw.h	/^	u32 bw:8;$/;"	m	struct:rtw89_c2h_phy_cap
bw40_1s_tssi_5g	rtw8852a.h	/^	u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];$/;"	m	struct:rtw8852a_tssi_offset
bw40_tssi	rtw8852a.h	/^	u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];$/;"	m	struct:rtw8852a_tssi_offset
bw_cap	core.h	/^	u8 bw_cap:2;$/;"	m	struct:rtw89_ra_info
bypass_dig	core.h	/^	bool bypass_dig;$/;"	m	struct:rtw89_dig_info
byr	core.h	/^	struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_txpwr_byrate
byr_table	core.h	/^	const struct rtw89_txpwr_table *byr_table;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_txpwr_table
bytes	core.h	/^	__le16 bytes;$/;"	m	struct:rtw89_btc_fbtc_mreg
c0_rx_qta	core.h	/^	u16 c0_rx_qta;$/;"	m	struct:rtw89_dle_info
c1_rx_qta	core.h	/^	u16 c1_rx_qta;$/;"	m	struct:rtw89_dle_info
c2h	core.h	/^	u16 c2h;$/;"	m	struct:rtw89_ple_quota
c2h	phy.c	/^	struct sk_buff *c2h;$/;"	m	struct:rtw89_phy_iter_ra_data	typeref:struct:rtw89_phy_iter_ra_data::sk_buff	file:
c2h_cnt	core.h	/^	u32 c2h_cnt; \/* fw send c2h counter  *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
c2h_queue	core.h	/^	struct sk_buff_head c2h_queue;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::sk_buff_head
c2h_work	core.h	/^	struct work_struct c2h_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::work_struct
c2hreg	fw.h	/^	u32 c2hreg[RTW89_C2HREG_MAX];$/;"	m	struct:rtw89_mac_c2h_info
cam_info	core.h	/^	struct rtw89_cam_info cam_info;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_cam_info
case_DBG_SEL	debug.c	1952;"	d	file:
case_DBG_SEL	debug.c	2004;"	d	file:
case_QUOTA	debug.c	899;"	d	file:
case_QUOTA	debug.c	949;"	d	file:
case_REGD	debug.c	519;"	d	file:
case_REGD	debug.c	549;"	d	file:
case_RXCHADDRS	pci.c	739;"	d	file:
case_RXCHADDRS	pci.c	763;"	d	file:
case_TXCHADDRS	pci.c	700;"	d	file:
case_TXCHADDRS	pci.c	737;"	d	file:
cb_data	debug.c	/^		u32 cb_data;$/;"	m	union:rtw89_debugfs_priv::__anon1	file:
cb_read	debug.c	/^	int (*cb_read)(struct seq_file *m, void *v);$/;"	m	struct:rtw89_debugfs_priv	file:
cb_write	debug.c	/^	ssize_t (*cb_write)(struct file *filp, const char __user *buffer,$/;"	m	struct:rtw89_debugfs_priv	file:
cca_ctrl_init	mac.c	/^static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
cch_by_bw	core.h	/^	u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1];$/;"	m	struct:rtw89_channel_params
cch_by_bw	core.h	/^	u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1];$/;"	m	struct:rtw89_hal
cck	core.h	/^	s8 cck[RTW89_RATE_CCK_MAX];$/;"	m	struct:rtw89_txpwr_byrate
cck_20m	core.h	/^	s8 cck_20m[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
cck_40m	core.h	/^	s8 cck_40m[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
cck_tssi	rtw8852a.h	/^	u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];$/;"	m	struct:rtw8852a_tssi_offset
cctl_tx_retry_limit	core.h	/^	bool cctl_tx_retry_limit;$/;"	m	struct:rtw89_sta
cctl_tx_time	core.h	/^	bool cctl_tx_time;$/;"	m	struct:rtw89_sta
ccx_edcca_opt_bw_idx	core.h	/^	enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;$/;"	m	struct:rtw89_env_monitor_info	typeref:enum:rtw89_env_monitor_info::rtw89_ccx_edcca_opt_bw_idx
ccx_manual_ctrl	core.h	/^	bool ccx_manual_ctrl;$/;"	m	struct:rtw89_env_monitor_info
ccx_ongoing	core.h	/^	bool ccx_ongoing;$/;"	m	struct:rtw89_env_monitor_info
ccx_period	core.h	/^	u16 ccx_period;$/;"	m	struct:rtw89_env_monitor_info
ccx_pre_rssi	core.h	/^	u8 ccx_pre_rssi;$/;"	m	struct:rtw89_env_monitor_info
ccx_rac_lv	core.h	/^	u8 ccx_rac_lv;$/;"	m	struct:rtw89_env_monitor_info
ccx_rpt_stamp	core.h	/^	u8 ccx_rpt_stamp;$/;"	m	struct:rtw89_env_monitor_info
ccx_trigger_time	core.h	/^	u32 ccx_trigger_time;$/;"	m	struct:rtw89_env_monitor_info
ccx_unit_idx	core.h	/^	u8 ccx_unit_idx;$/;"	m	struct:rtw89_env_monitor_info
ccx_watchdog_result	core.h	/^	u8 ccx_watchdog_result;$/;"	m	struct:rtw89_env_monitor_info
center_chan	core.h	/^	u8 center_chan;$/;"	m	struct:rtw89_channel_params
cfg	core.h	/^	s32 cfg[RTW89_SUBBAND_NR];$/;"	m	struct:rtw89_sar_cfg_common
cfg_common	core.h	/^		struct rtw89_sar_cfg_common cfg_common;$/;"	m	union:rtw89_sar_info::__anon14	typeref:struct:rtw89_sar_info::__anon14::rtw89_sar_cfg_common
cfg_lna_a	phy.h	/^	const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;$/;"	m	struct:rtw89_phy_dig_gain_table	typeref:struct:rtw89_phy_dig_gain_table::rtw89_phy_dig_gain_cfg
cfg_lna_g	phy.h	/^	const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;$/;"	m	struct:rtw89_phy_dig_gain_table	typeref:struct:rtw89_phy_dig_gain_table::rtw89_phy_dig_gain_cfg
cfg_tia_a	phy.h	/^	const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;$/;"	m	struct:rtw89_phy_dig_gain_table	typeref:struct:rtw89_phy_dig_gain_table::rtw89_phy_dig_gain_cfg
cfg_tia_g	phy.h	/^	const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;$/;"	m	struct:rtw89_phy_dig_gain_table	typeref:struct:rtw89_phy_dig_gain_table::rtw89_phy_dig_gain_cfg
cfo_avg	core.h	/^	s32 cfo_avg[CFO_TRACK_MAX_USER];$/;"	m	struct:rtw89_cfo_tracking_info
cfo_avg_pre	core.h	/^	s32 cfo_avg_pre;$/;"	m	struct:rtw89_cfo_tracking_info
cfo_cnt	core.h	/^	u16 cfo_cnt[CFO_TRACK_MAX_USER];$/;"	m	struct:rtw89_cfo_tracking_info
cfo_tail	core.h	/^	s32 cfo_tail[CFO_TRACK_MAX_USER];$/;"	m	struct:rtw89_cfo_tracking_info
cfo_timer_ms	core.h	/^	u16 cfo_timer_ms;$/;"	m	struct:rtw89_cfo_tracking_info
cfo_track_work	core.h	/^	struct delayed_work cfo_track_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
cfo_tracking	core.h	/^	struct rtw89_cfo_tracking_info cfo_tracking;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_cfo_tracking_info
cfo_trig_by_timer_en	core.h	/^	bool cfo_trig_by_timer_en;$/;"	m	struct:rtw89_cfo_tracking_info
ch	core.h	/^	u8 ch;$/;"	m	struct:rtw89_btc_wl_active_role
ch	core.h	/^	u8 ch;$/;"	m	struct:rtw89_btc_wl_afh_info
ch	core.h	/^	u8 ch;$/;"	m	struct:rtw89_btc_wl_link_info
ch	core.h	/^	u8 ch;$/;"	m	struct:rtw89_dpk_bkup_para
ch011_full_cond	core.h	/^	u8 ch011_full_cond;$/;"	m	struct:rtw89_hfc_prec_cfg
ch011_prec	core.h	/^	u16 ch011_prec;$/;"	m	struct:rtw89_hfc_prec_cfg
ch_cfg	core.h	/^	const struct rtw89_hfc_ch_cfg *ch_cfg;$/;"	m	struct:rtw89_hfc_param	typeref:struct:rtw89_hfc_param::rtw89_hfc_ch_cfg
ch_cfg	core.h	/^	const struct rtw89_hfc_ch_cfg *ch_cfg;$/;"	m	struct:rtw89_hfc_param_ini	typeref:struct:rtw89_hfc_param_ini::rtw89_hfc_ch_cfg
ch_dma	core.h	/^	u8 ch_dma;$/;"	m	struct:rtw89_tx_desc_info
ch_info	core.h	/^	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];$/;"	m	struct:rtw89_hfc_param	typeref:struct:rtw89_hfc_param::rtw89_hfc_ch_info
ch_info	core.h	/^	struct rtw89_phy_ch_info ch_info;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_phy_ch_info
ch_info	phy.c	/^	struct rtw89_phy_ch_info *ch_info;$/;"	m	struct:rtw89_phy_iter_rssi_data	typeref:struct:rtw89_phy_iter_rssi_data::rtw89_phy_ch_info	file:
channel_plan	rtw8852a.h	/^	u8 channel_plan;$/;"	m	struct:rtw8852a_efuse
check_and_reclaim_tx_resource	core.h	/^	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);$/;"	m	struct:rtw89_hci_ops
chip	core.h	/^	const struct rtw89_chip_info *chip;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_chip_info
chip_func_en	mac.c	/^static int chip_func_en(struct rtw89_dev *rtwdev)$/;"	f	file:
chip_id	core.h	/^	enum rtw89_core_chip_id chip_id;$/;"	m	struct:rtw89_chip_info	typeref:enum:rtw89_chip_info::rtw89_core_chip_id
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_report_ctrl_state	typeref:struct:rtw89_btc_report_ctrl_state::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btafh	typeref:struct:rtw89_btc_rpt_fbtc_btafh::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btdev	typeref:struct:rtw89_btc_rpt_fbtc_btdev::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btscan	typeref:struct:rtw89_btc_rpt_fbtc_btscan::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btver	typeref:struct:rtw89_btc_rpt_fbtc_btver::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_cysta	typeref:struct:rtw89_btc_rpt_fbtc_cysta::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_gpio_dbg	typeref:struct:rtw89_btc_rpt_fbtc_gpio_dbg::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_mreg	typeref:struct:rtw89_btc_rpt_fbtc_mreg::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_nullsta	typeref:struct:rtw89_btc_rpt_fbtc_nullsta::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_slots	typeref:struct:rtw89_btc_rpt_fbtc_slots::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_step	typeref:struct:rtw89_btc_rpt_fbtc_step::rtw89_btc_rpt_cmn_info
cinfo	core.h	/^	struct rtw89_btc_rpt_cmn_info cinfo; \/* common info, by driver *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_tdma	typeref:struct:rtw89_btc_rpt_fbtc_tdma::rtw89_btc_rpt_cmn_info
client_cnt	core.h	/^	u32 client_cnt;$/;"	m	struct:rtw89_btc_wl_link_info
client_ps	core.h	/^	u32 client_ps: 1;$/;"	m	struct:rtw89_btc_wl_link_info
client_ps	core.h	/^	u8 client_ps: 1;$/;"	m	struct:rtw89_btc_wl_active_role
clm_mntr_time	core.h	/^	u16 clm_mntr_time;$/;"	m	struct:rtw89_env_monitor_info
clm_ratio	core.h	/^	u8 clm_ratio;$/;"	m	struct:rtw89_env_monitor_info
clm_result	core.h	/^	u16 clm_result;$/;"	m	struct:rtw89_env_monitor_info
cma0_dma	core.h	/^	u16 cma0_dma;$/;"	m	struct:rtw89_ple_quota
cma0_tx	core.h	/^	u16 cma0_tx;$/;"	m	struct:rtw89_ple_quota
cma1_dma	core.h	/^	u16 cma1_dma;$/;"	m	struct:rtw89_ple_quota
cma1_tx	core.h	/^	u16 cma1_tx;$/;"	m	struct:rtw89_ple_quota
cmac_com_init	mac.c	/^static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
cmac_dbg	debug.c	/^			u8 cmac_dbg:1;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon4	file:
cmac_func_en	mac.c	/^static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)$/;"	f	file:
cmac_init	mac.c	/^static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
cmd	mac.h	/^	u8 cmd:4;$/;"	m	struct:rtw89_pwr_cfg
cmd_type	mac.h	/^	u8 cmd_type;$/;"	m	struct:rtw89_cpuio_ctrl
cmd_ver	core.h	/^	u8 cmd_ver;$/;"	m	struct:rtw89_fw_suit
cnt	core.h	/^	__le16 cnt;$/;"	m	struct:rtw89_btc_fbtc_steps
cnt_bt	core.h	/^	u32 cnt_bt[BTC_BCNT_NUM];$/;"	m	struct:rtw89_btc_cx
cnt_c2h	core.h	/^	u32 cnt_c2h;$/;"	m	struct:rtw89_btc_btf_fwinfo
cnt_dm	core.h	/^	u32 cnt_dm[BTC_DCNT_NUM];$/;"	m	struct:rtw89_btc_dm
cnt_h2c	core.h	/^	u32 cnt_h2c;$/;"	m	struct:rtw89_btc_btf_fwinfo
cnt_h2c_fail	core.h	/^	u32 cnt_h2c_fail;$/;"	m	struct:rtw89_btc_btf_fwinfo
cnt_notify	core.h	/^	u32 cnt_notify[BTC_NCNT_NUM];$/;"	m	struct:rtw89_btc_dm
cnt_wl	core.h	/^	u32 cnt_wl[BTC_WCNT_NUM];$/;"	m	struct:rtw89_btc_cx
coex_act1_work	core.h	/^	struct delayed_work coex_act1_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
coex_bt_devinfo_work	core.h	/^	struct delayed_work coex_bt_devinfo_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
coex_info_map	core.h	/^	u32 coex_info_map: 8;$/;"	m	struct:rtw89_btc_dm
coex_rfk_chk_work	core.h	/^	struct delayed_work coex_rfk_chk_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
coex_type	rtw8852a.h	/^	u8 coex_type:3;$/;"	m	struct:rtw8852a_efuse
coex_ver	core.h	/^	__le32 coex_ver; \/*bit[15:8]->shared, bit[7:0]->non-shared *\/$/;"	m	struct:rtw89_btc_fbtc_btver
collision_cnt	coex.c	/^	u32 collision_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
collision_cnt	core.h	/^	__le32 collision_cnt; \/* counter for event\/timer occur at same time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
completion	core.h	/^	struct completion completion;$/;"	m	struct:rtw89_fw_info	typeref:struct:rtw89_fw_info::completion
connect	coex.c	/^	u8 connect: 1;$/;"	m	struct:btc_btinfo_lb2	file:
connect	core.h	/^	u32 connect: 1;$/;"	m	struct:rtw89_btc_bt_smap
connect_cnt	core.h	/^	u8 connect_cnt;$/;"	m	struct:rtw89_btc_wl_role_info
connected	core.h	/^	u32 connected: 2;$/;"	m	struct:rtw89_btc_wl_link_info
connected	core.h	/^	u8 connected: 1;$/;"	m	struct:rtw89_btc_wl_active_role
connecting	core.h	/^	u32 connecting: 1;$/;"	m	struct:rtw89_btc_wl_smap
content	coex.c	/^	u8 content[];$/;"	m	struct:rtw89_btc_prpt	file:
content_len	fw.h	/^	u8 content_len;$/;"	m	struct:rtw89_mac_c2h_info
content_len	fw.h	/^	u8 content_len;$/;"	m	struct:rtw89_mac_h2c_info
corr_idx	core.h	/^	u8 corr_idx[RTW89_DPK_RF_PATH];$/;"	m	struct:rtw89_dpk_info
corr_val	core.h	/^	u8 corr_val[RTW89_DPK_RF_PATH];$/;"	m	struct:rtw89_dpk_info
count	mac.c	/^	int count;$/;"	m	struct:rtw89_mac_bf_monitor_iter_data	file:
country_code	core.h	/^	char country_code[2];$/;"	m	struct:rtw89_efuse
country_code	rtw8852a.h	/^	u8 country_code[2];$/;"	m	struct:rtw8852a_efuse
cpu_io	core.h	/^	u16 cpu_io;$/;"	m	struct:rtw89_ple_quota
cpu_io	core.h	/^	u16 cpu_io;$/;"	m	struct:rtw89_wde_quota
cpwm_addr	core.h	/^	u32 cpwm_addr;$/;"	m	struct:rtw89_hci_info
cpwm_seq_num	core.h	/^	u8 cpwm_seq_num;$/;"	m	struct:rtw89_mac_info
cqddr	coex.c	/^	u8 cqddr: 1;$/;"	m	struct:btc_btinfo_lb3	file:
cqddr	core.h	/^	u32 cqddr: 1;$/;"	m	struct:rtw89_btc_bt_link_info
cr_tbl_sel	core.h	/^	u8 cr_tbl_sel:1;$/;"	m	struct:rtw89_ra_info
crc32_err	core.h	/^	bool crc32_err;$/;"	m	struct:rtw89_rx_desc_info
crystal_cap	core.h	/^	u8 crystal_cap;$/;"	m	struct:rtw89_cfo_tracking_info
crystal_cap_default	core.h	/^	u8 crystal_cap_default;$/;"	m	struct:rtw89_cfo_tracking_info
csi_bw	core.h	/^	u8 csi_bw:3;$/;"	m	struct:rtw89_ra_info
csi_gi_ltf	core.h	/^	u8 csi_gi_ltf:3;$/;"	m	struct:rtw89_ra_info
csi_mcs_ss_idx	core.h	/^	u8 csi_mcs_ss_idx;$/;"	m	struct:rtw89_ra_info
csi_mode	core.h	/^	u8 csi_mode:2;$/;"	m	struct:rtw89_ra_info
ctrl	core.h	/^	struct rtw89_btc_ctrl ctrl;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_ctrl
ctrl_btg	core.h	/^	void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);$/;"	m	struct:rtw89_chip_ops
cur_gaincode	core.h	/^	struct rtw89_agc_gaincode_set cur_gaincode;$/;"	m	struct:rtw89_dig_info	typeref:struct:rtw89_dig_info::rtw89_agc_gaincode_set
cur_idx	core.h	/^	u8 cur_idx[RTW89_DPK_RF_PATH];$/;"	m	struct:rtw89_dpk_info
cur_pkt_stat	core.h	/^	struct rtw89_pkt_stat cur_pkt_stat;$/;"	m	struct:rtw89_phy_stat	typeref:struct:rtw89_phy_stat::rtw89_pkt_stat
curr_idx	fw.h	/^	u16 curr_idx;$/;"	m	struct:rtw89_fw_h2c_rf_reg_info
curr_num	pci.h	/^	u32 curr_num;$/;"	m	struct:rtw89_pci_tx_wd_ring
curr_rx_ppdu_cnt	core.h	/^	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];$/;"	m	struct:rtw89_ppdu_sts_info
current_band_type	core.h	/^	u8 current_band_type;$/;"	m	struct:rtw89_hal
current_band_width	core.h	/^	u8 current_band_width;$/;"	m	struct:rtw89_hal
current_channel	core.h	/^	u8 current_channel;$/;"	m	struct:rtw89_hal
current_primary_channel	core.h	/^	u8 current_primary_channel;$/;"	m	struct:rtw89_hal
current_subband	core.h	/^	enum rtw89_subband current_subband;$/;"	m	struct:rtw89_hal	typeref:enum:rtw89_hal::rtw89_subband
customer_id	rtw8852a.h	/^	u8 customer_id;$/;"	m	struct:rtw8852a_efuse
cv	core.h	/^	u8 cv;$/;"	m	struct:rtw89_btc_module
cv	core.h	/^	u8 cv;$/;"	m	struct:rtw89_hal
cv	fw.h	/^	u8 cv;$/;"	m	struct:rtw89_mfw_info
cv_msk	mac.h	/^	u8 cv_msk;$/;"	m	struct:rtw89_pwr_cfg
cx	core.h	/^	struct rtw89_btc_cx cx;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_cx
cx_other	core.h	/^	u8 cx_other: 1;$/;"	m	struct:rtw89_btc_init_info
cxtbl	coex.c	/^static const u32 cxtbl[] = {$/;"	v	file:
cxtbl	core.h	/^	__le32 cxtbl;$/;"	m	struct:rtw89_btc_fbtc_slot
cxtype	core.h	/^	__le16 cxtype;$/;"	m	struct:rtw89_btc_fbtc_slot
cycle_hang	core.h	/^	u32 cycle_hang: 1;$/;"	m	struct:rtw89_btc_dm_emap
cycles	coex.c	/^	u16 cycles;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
cycles	core.h	/^	__le16 cycles; \/* total cycle number *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
cycles_a2dp	coex.c	/^	u16 cycles_a2dp[CXT_FLCTRL_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
cycles_a2dp	core.h	/^	__le16 cycles_a2dp[CXT_FLCTRL_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta
dack	core.h	/^	struct rtw89_dack_info dack;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_dack_info
dack_cnt	core.h	/^	u32 dack_cnt;$/;"	m	struct:rtw89_dack_info
dack_done	core.h	/^	bool dack_done;$/;"	m	struct:rtw89_dack_info
dadck_d	core.h	/^	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];$/;"	m	struct:rtw89_dack_info
dadck_timeout	core.h	/^	bool dadck_timeout[RTW89_DACK_PATH_NR];$/;"	m	struct:rtw89_dack_info
data	core.h	/^	const u8 *data;$/;"	m	struct:rtw89_fw_suit
data	core.h	/^	const void *data;$/;"	m	struct:rtw89_txpwr_table
data	core.h	/^	u32 data;$/;"	m	struct:rtw89_reg2_def
data	core.h	/^	u32 data;$/;"	m	struct:rtw89_reg3_def
data	core.h	/^	u32 data;$/;"	m	struct:rtw89_reg5_def
data	phy.h	/^	u32 data;$/;"	m	struct:rtw89_txpwr_byrate_cfg
data_rate	core.h	/^	u16 data_rate;$/;"	m	struct:rtw89_rx_desc_info
data_rate	core.h	/^	u16 data_rate;$/;"	m	struct:rtw89_tx_desc_info
data_retry_lowest_rate	core.h	/^	u16 data_retry_lowest_rate;$/;"	m	struct:rtw89_tx_desc_info
data_tx_cnt_lmt	core.h	/^	u32 data_tx_cnt_lmt:6;$/;"	m	struct:rtw89_sta
dbcc_en	core.h	/^	bool dbcc_en;$/;"	m	struct:rtw89_dev
dbcc_en	core.h	/^	u8 dbcc_en: 1;$/;"	m	struct:rtw89_btc_init_info
dbcc_info	core.h	/^	struct rtw89_btc_wl_dbcc_info dbcc_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_dbcc_info
dbg	core.h	/^	struct rtw89_btc_dbg dbg;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_dbg
dbg_port	debug.c	/^			u8 dbg_port:1;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon4	file:
dbg_port_pcie_cvt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_cxpl	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_io	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_misc	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_misc2	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_rxdma	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pcie_txdma	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_pktinfo	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_bufmgn_freepg	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_bufmgn_pagellt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_bufmgn_pktinfo	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_bufmgn_quota	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_quemgn_nxtpkt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_quemgn_prepkt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_quemgn_qempty	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ple_quemgn_qlnktbl	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ptcl_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_ptcl_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmac_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmac_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmac_plcp_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmac_plcp_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmacst_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_rmacst_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_sch_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_sch_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tmac_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tmac_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_trxptcl_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_trxptcl_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tx_infoh_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tx_infoh_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tx_infol_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_tx_infol_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_txtf_infoh_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_txtf_infoh_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_txtf_infol_c0	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_txtf_infol_c1	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_bufmgn_freepg	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_bufmgn_pagellt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_bufmgn_pktinfo	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_bufmgn_quota	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_quemgn_nxtpkt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_quemgn_prepkt	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_quemgn_qempty	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbg_port_wde_quemgn_qlnktbl	debug.c	/^static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {$/;"	v	typeref:struct:rtw89_mac_dbg_port_info	file:
dbgpkg_en	debug.c	/^		} dbgpkg_en;$/;"	m	union:rtw89_debugfs_priv::__anon1	typeref:struct:rtw89_debugfs_priv::__anon1::__anon4	file:
dc_i	core.h	/^	u16 dc_i[RTW89_DPK_RF_PATH];$/;"	m	struct:rtw89_dpk_info
dc_q	core.h	/^	u16 dc_q[RTW89_DPK_RF_PATH];$/;"	m	struct:rtw89_dpk_info
dcm_cap	core.h	/^	u8 dcm_cap:1;$/;"	m	struct:rtw89_ra_info
def_x_cap	core.h	/^	u8 def_x_cap;$/;"	m	struct:rtw89_cfo_tracking_info
default_txagc_offset	core.h	/^	u8 default_txagc_offset[RF_PATH_MAX];$/;"	m	struct:rtw89_tssi_info
defs	rtw8852a_rfk_table.h	/^	const struct rtw89_reg5_def *defs;$/;"	m	struct:rtw89_rfk_tbl	typeref:struct:rtw89_rfk_tbl::rtw89_reg5_def
deinit	core.h	/^	int (*deinit)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
delta_swingidx_2g_cck_a_n	phy.h	/^	const u8 *delta_swingidx_2g_cck_a_n;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2g_cck_a_p	phy.h	/^	const u8 *delta_swingidx_2g_cck_a_p;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2g_cck_b_n	phy.h	/^	const u8 *delta_swingidx_2g_cck_b_n;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2g_cck_b_p	phy.h	/^	const u8 *delta_swingidx_2g_cck_b_p;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2ga_n	phy.h	/^	const u8 *delta_swingidx_2ga_n;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2ga_p	phy.h	/^	const u8 *delta_swingidx_2ga_p;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2gb_n	phy.h	/^	const u8 *delta_swingidx_2gb_n;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_2gb_p	phy.h	/^	const u8 *delta_swingidx_2gb_p;$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_5ga_n	phy.h	/^	const u8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE];$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_5ga_p	phy.h	/^	const u8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE];$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_5gb_n	phy.h	/^	const u8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE];$/;"	m	struct:rtw89_txpwr_track_cfg
delta_swingidx_5gb_p	phy.h	/^	const u8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE];$/;"	m	struct:rtw89_txpwr_track_cfg
desc_info	core.c	/^	struct rtw89_rx_desc_info *desc_info;$/;"	m	struct:rtw89_core_iter_rx_status	typeref:struct:rtw89_core_iter_rx_status::rtw89_rx_desc_info	file:
desc_info	core.c	/^	struct rtw89_rx_desc_info *desc_info;$/;"	m	struct:rtw89_vif_rx_stats_iter_data	typeref:struct:rtw89_vif_rx_stats_iter_data::rtw89_rx_desc_info	file:
desc_info	core.h	/^	struct rtw89_tx_desc_info desc_info;$/;"	m	struct:rtw89_core_tx_request	typeref:struct:rtw89_core_tx_request::rtw89_tx_desc_info
desc_size	pci.h	/^	u8 desc_size;$/;"	m	struct:rtw89_pci_dma_ring
descr_sar_source	sar.h	/^	const char *descr_sar_source;$/;"	m	struct:rtw89_sar_handler
dev	core.h	/^	struct device *dev;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::device
dev_name	core.h	/^	__le32 dev_name; \/* only 24 bits valid *\/$/;"	m	struct:rtw89_btc_fbtc_btdevinfo
device_name	core.h	/^	u32 device_name;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
dhcp_notify_work	core.h	/^	struct work_struct dhcp_notify_work;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::work_struct
difft	core.h	/^	__le16 difft;$/;"	m	struct:rtw89_btc_fbtc_step
dig	core.h	/^	struct rtw89_dig_info dig;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_dig_info
dig_table	core.h	/^	const struct rtw89_phy_dig_gain_table *dig_table;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_phy_dig_gain_table
diliver_desc	pci.h	/^	struct rtw89_rx_desc_info diliver_desc;$/;"	m	struct:rtw89_pci_rx_ring	typeref:struct:rtw89_pci_rx_ring::rtw89_rx_desc_info
diliver_skb	pci.h	/^	struct sk_buff *diliver_skb;$/;"	m	struct:rtw89_pci_rx_ring	typeref:struct:rtw89_pci_rx_ring::sk_buff
dir	core.h	/^	enum rtw89_tfc_dir dir;$/;"	m	struct:rtw89_btc_wl_link_info	typeref:enum:rtw89_btc_wl_link_info::rtw89_tfc_dir
dir_all	coex.c	/^	u8 dir_all;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	file:
direction	mac.h	/^	u8 direction;$/;"	m	struct:rtw89_mac_ax_coex
dis_2g_40m_ul_ofdma	core.h	/^	bool dis_2g_40m_ul_ofdma;$/;"	m	struct:rtw89_chip_info
dis_data_fb	core.h	/^	bool dis_data_fb;$/;"	m	struct:rtw89_tx_desc_info
disassoc	core.h	/^	bool disassoc;$/;"	m	struct:rtw89_sta
diversity	core.h	/^	u8 diversity: 1;$/;"	m	struct:rtw89_btc_ant_info
dladdr	fw.h	/^	u32 dladdr;$/;"	m	struct:rtw89_fw_hdr_section_info
dle_clk_en	mac.c	/^static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
dle_dbg	debug.c	/^			u8 dle_dbg:1;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon4	file:
dle_dfi_ctrl	mac.c	/^int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)$/;"	f	file:
dle_dfi_qempty	mac.c	/^static int dle_dfi_qempty(struct rtw89_dev *rtwdev,$/;"	f	file:
dle_dfi_quota	mac.c	/^static int dle_dfi_quota(struct rtw89_dev *rtwdev,$/;"	f	file:
dle_func_en	mac.c	/^static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
dle_info	core.h	/^	struct rtw89_dle_info dle_info;$/;"	m	struct:rtw89_mac_info	typeref:struct:rtw89_mac_info::rtw89_dle_info
dle_init	mac.c	/^static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,$/;"	f	file:
dle_is_txq_empty	mac.c	/^static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)$/;"	f	file:
dle_mem	core.h	/^	const struct rtw89_dle_mem *dle_mem;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_dle_mem
dle_mix_cfg	mac.c	/^static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)$/;"	f	file:
dle_quota_cfg	mac.c	/^static void dle_quota_cfg(struct rtw89_dev *rtwdev,$/;"	f	file:
dle_quota_change	mac.c	/^static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)$/;"	f	file:
dle_type	mac.h	/^	enum rtw89_mac_dle_ctrl_type dle_type;$/;"	m	struct:rtw89_mac_dle_dfi_qempty	typeref:enum:rtw89_mac_dle_dfi_qempty::rtw89_mac_dle_ctrl_type
dle_type	mac.h	/^	enum rtw89_mac_dle_ctrl_type dle_type;$/;"	m	struct:rtw89_mac_dle_dfi_quota	typeref:enum:rtw89_mac_dle_dfi_quota::rtw89_mac_dle_ctrl_type
dle_used_size	mac.c	/^static inline u32 dle_used_size(const struct rtw89_dle_size *wde,$/;"	f	file:
dm	core.h	/^	struct rtw89_btc_dm dm;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_dm
dm_step	core.h	/^	struct rtw89_btc_dm_step dm_step;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_dm_step
dma	pci.h	/^	__le32 dma;$/;"	m	struct:rtw89_pci_rx_bd_32
dma	pci.h	/^	__le32 dma;$/;"	m	struct:rtw89_pci_tx_addr_info_32
dma	pci.h	/^	__le32 dma;$/;"	m	struct:rtw89_pci_tx_bd_32
dma	pci.h	/^	dma_addr_t dma;$/;"	m	struct:rtw89_pci_dma_ring
dma	pci.h	/^	dma_addr_t dma;$/;"	m	struct:rtw89_pci_rx_info
dma	pci.h	/^	dma_addr_t dma;$/;"	m	struct:rtw89_pci_tx_data
dma	pci.h	/^	dma_addr_t dma;$/;"	m	struct:rtw89_pci_tx_wd_ring
dma_enabled	pci.h	/^	bool dma_enabled;$/;"	m	struct:rtw89_pci_tx_ring
dmac_dbg	debug.c	/^			u8 dmac_dbg:1;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon4	file:
dmac_func_en	mac.c	/^static int dmac_func_en(struct rtw89_dev *rtwdev)$/;"	f	file:
dmac_init	mac.c	/^static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
down_sta	mac.c	/^	struct ieee80211_sta *down_sta;$/;"	m	struct:rtw89_mac_bf_monitor_iter_data	typeref:struct:rtw89_mac_bf_monitor_iter_data::ieee80211_sta	file:
dpk	core.h	/^	struct rtw89_dpk_info dpk;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_dpk_info
dpk_agc_step	rtw8852a_rfk.c	/^enum dpk_agc_step {$/;"	g	file:
drv_info_size	core.h	/^	u8 drv_info_size;$/;"	m	struct:rtw89_rx_desc_info
drv_resume_rx	ser.c	/^static void drv_resume_rx(struct rtw89_ser *ser)$/;"	f	file:
drv_resume_tx	ser.c	/^static void drv_resume_tx(struct rtw89_ser *ser)$/;"	f	file:
drv_stop_rx	ser.c	/^static void drv_stop_rx(struct rtw89_ser *ser)$/;"	f	file:
drv_stop_tx	ser.c	/^static void drv_stop_tx(struct rtw89_ser *ser)$/;"	f	file:
drv_trx_reset	ser.c	/^static void drv_trx_reset(struct rtw89_ser *ser)$/;"	f	file:
dst_pid	mac.h	/^	u8 dst_pid;$/;"	m	struct:rtw89_cpuio_ctrl
dst_qid	mac.h	/^	u8 dst_qid;$/;"	m	struct:rtw89_cpuio_ctrl
dtim_ctrl	core.h	/^	u32 dtim_ctrl;$/;"	m	struct:rtw89_port_reg
dtim_period	core.h	/^	u8 dtim_period;$/;"	m	struct:rtw89_btc_wl_link_info
dump_err_status	core.h	/^	void (*dump_err_status)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
dump_err_status_dispatcher	mac.c	/^static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)$/;"	f	file:
dur	core.h	/^	__le16 dur;$/;"	m	struct:rtw89_btc_fbtc_slot
duty_cycle	rtw8852a.h	/^	u8 duty_cycle;$/;"	m	struct:rtw8852a_bb_pmac_info
dword	pci.h	/^	__le32 dword;$/;"	m	struct:rtw89_pci_rpp_fmt
dword	pci.h	/^	__le32 dword;$/;"	m	struct:rtw89_pci_rxbd_info
dword0	core.h	/^	__le32 dword0;$/;"	m	struct:rtw89_rxdesc_long
dword0	core.h	/^	__le32 dword0;$/;"	m	struct:rtw89_rxdesc_short
dword0	core.h	/^	__le32 dword0;$/;"	m	struct:rtw89_txwd_body
dword0	core.h	/^	__le32 dword0;$/;"	m	struct:rtw89_txwd_info
dword1	core.h	/^	__le32 dword1;$/;"	m	struct:rtw89_rxdesc_long
dword1	core.h	/^	__le32 dword1;$/;"	m	struct:rtw89_rxdesc_short
dword1	core.h	/^	__le32 dword1;$/;"	m	struct:rtw89_txwd_body
dword1	core.h	/^	__le32 dword1;$/;"	m	struct:rtw89_txwd_info
dword2	core.h	/^	__le32 dword2;$/;"	m	struct:rtw89_rxdesc_long
dword2	core.h	/^	__le32 dword2;$/;"	m	struct:rtw89_rxdesc_short
dword2	core.h	/^	__le32 dword2;$/;"	m	struct:rtw89_txwd_body
dword2	core.h	/^	__le32 dword2;$/;"	m	struct:rtw89_txwd_info
dword3	core.h	/^	__le32 dword3;$/;"	m	struct:rtw89_rxdesc_long
dword3	core.h	/^	__le32 dword3;$/;"	m	struct:rtw89_rxdesc_short
dword3	core.h	/^	__le32 dword3;$/;"	m	struct:rtw89_txwd_body
dword3	core.h	/^	__le32 dword3;$/;"	m	struct:rtw89_txwd_info
dword4	core.h	/^	__le32 dword4;$/;"	m	struct:rtw89_rxdesc_long
dword4	core.h	/^	__le32 dword4;$/;"	m	struct:rtw89_txwd_body
dword4	core.h	/^	__le32 dword4;$/;"	m	struct:rtw89_txwd_info
dword5	core.h	/^	__le32 dword5;$/;"	m	struct:rtw89_rxdesc_long
dword5	core.h	/^	__le32 dword5;$/;"	m	struct:rtw89_txwd_body
dword5	core.h	/^	__le32 dword5;$/;"	m	struct:rtw89_txwd_info
dword6	core.h	/^	__le32 dword6;$/;"	m	struct:rtw89_rxdesc_long
dword7	core.h	/^	__le32 dword7;$/;"	m	struct:rtw89_rxdesc_long
dyn_igi_max	core.h	/^	u8 dyn_igi_max;$/;"	m	struct:rtw89_dig_info
dyn_igi_min	core.h	/^	u8 dyn_igi_min;$/;"	m	struct:rtw89_dig_info
dyn_pd_th_en	core.h	/^	bool dyn_pd_th_en;$/;"	m	struct:rtw89_dig_info
dyn_pd_th_max	core.h	/^	u8 dyn_pd_th_max;$/;"	m	struct:rtw89_dig_info
dynamic_igi_min	phy.c	/^static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20;$/;"	v	file:
dynamic_pd_threshold_max	phy.c	/^static const u8 dynamic_pd_threshold_max;$/;"	v	file:
e	rtw8852a.h	/^		struct rtw8852ae_efuse e;$/;"	m	union:rtw8852a_efuse::__anon6	typeref:struct:rtw8852a_efuse::__anon6::rtw8852ae_efuse
eapol_notify_work	core.h	/^	struct work_struct eapol_notify_work;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::work_struct
early_h2c_list	core.h	/^	struct list_head early_h2c_list;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::list_head
edcca_clm_mntr_time	core.h	/^	u16 edcca_clm_mntr_time;$/;"	m	struct:rtw89_env_monitor_info
edcca_clm_ratio	core.h	/^	u8 edcca_clm_ratio;$/;"	m	struct:rtw89_env_monitor_info
edcca_clm_result	core.h	/^	u16 edcca_clm_result;$/;"	m	struct:rtw89_env_monitor_info
eeprom_version	rtw8852a.h	/^	u8 eeprom_version;$/;"	m	struct:rtw8852a_efuse
efuse	core.h	/^	struct rtw89_efuse efuse;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_efuse
elna_2g	core.h	/^	bool elna_2g;$/;"	m	struct:rtw89_fem_info
elna_5g	core.h	/^	bool elna_5g;$/;"	m	struct:rtw89_fem_info
en	core.h	/^	bool en;$/;"	m	struct:rtw89_hfc_param
en	core.h	/^	u8 en;$/;"	m	struct:rtw89_btc_wl_afh_info
en_map	core.h	/^	u32 en_map; \/* which debug signal (see btc_wl_gpio_debug) is enable *\/$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
en_pmac_tx	rtw8852a.h	/^	u8 en_pmac_tx:1;$/;"	m	struct:rtw8852a_bb_pmac_info
en_sgi	core.h	/^	u8 en_sgi:1;$/;"	m	struct:rtw89_ra_info
en_wd_info	core.h	/^	bool en_wd_info;$/;"	m	struct:rtw89_tx_desc_info
enable	coex.c	/^	__le32 enable;$/;"	m	struct:rtw89_btc_btf_set_report	file:
enable	coex.c	/^	u16 enable;$/;"	m	struct:rtw89_txtime_data	file:
enable	core.h	/^	bool enable;$/;"	m	struct:rtw89_phy_rate_pattern
enable	core.h	/^	struct rtw89_btc_bool_sta_chg enable;$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_bool_sta_chg
enable	core.h	/^	u16 enable;$/;"	m	struct:rtw89_btc_wl_tx_limit_para
enable	core.h	/^	u32 enable: 1;$/;"	m	struct:rtw89_btc_bt_scan_info
end	mac.h	/^	u32 end;$/;"	m	struct:rtw89_mac_dbg_port_info
end_pktid	mac.h	/^	u16 end_pktid;$/;"	m	struct:rtw89_cpuio_ctrl
ent	debug.c	/^	const struct txpwr_ent *ent;$/;"	m	struct:txpwr_map	typeref:struct:txpwr_map::txpwr_ent	file:
env_monitor	core.h	/^	struct rtw89_env_monitor_info env_monitor;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_env_monitor_info
epa_2g	core.h	/^	bool epa_2g;$/;"	m	struct:rtw89_fem_info
epa_5g	core.h	/^	bool epa_5g;$/;"	m	struct:rtw89_fem_info
er_cap	core.h	/^	u8 er_cap:1;$/;"	m	struct:rtw89_ra_info
err	core.h	/^	u32 err[BTFRE_MAX];$/;"	m	struct:rtw89_btc_btf_fwinfo
error	core.h	/^	union rtw89_btc_dm_error_map error;$/;"	m	struct:rtw89_btc_dm	typeref:union:rtw89_btc_dm::rtw89_btc_dm_error_map
ev_tbl	core.h	/^	struct event_ent *ev_tbl;$/;"	m	struct:rtw89_ser	typeref:struct:rtw89_ser::event_ent
event	core.h	/^	u32 event[BTF_EVNT_MAX];$/;"	m	struct:rtw89_btc_btf_fwinfo
event	ser.c	/^	u8 event;$/;"	m	struct:event_ent	file:
event	ser.c	/^	u8 event;$/;"	m	struct:ser_msg	file:
event_ent	ser.c	/^struct event_ent {$/;"	s	file:
except_cnt	coex.c	/^	u32 except_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
except_cnt	core.h	/^	__le32 except_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta
exception	coex.c	/^	u32 exception;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
exception	core.h	/^	__le32 exception;$/;"	m	struct:rtw89_btc_fbtc_cysta
exist	core.h	/^	u32 exist: 1;$/;"	m	struct:rtw89_btc_bt_hfp_desc
exist	core.h	/^	u32 exist: 1;$/;"	m	struct:rtw89_btc_bt_hid_desc
exist	core.h	/^	u32 exist: 1;$/;"	m	struct:rtw89_btc_bt_pan_desc
exist	core.h	/^	u8 exist: 1;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
exist_last	core.h	/^	u8 exist_last: 1;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
ext_ctrl	core.h	/^	u8 ext_ctrl;$/;"	m	struct:rtw89_btc_fbtc_tdma
ext_key	core.h	/^	u8 ext_key : 1;$/;"	m	struct:rtw89_sec_cam_entry
extra_ofst	core.h	/^	s8 extra_ofst[RF_PATH_MAX];$/;"	m	struct:rtw89_tssi_info
fa_rssi_ofst	core.h	/^	u8 fa_rssi_ofst;$/;"	m	struct:rtw89_dig_info
fa_th	core.h	/^	u16 fa_th[FA_TH_NUM];$/;"	m	struct:rtw89_dig_info
fa_th_2g	phy.c	/^static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};$/;"	v	file:
fa_th_5g	phy.c	/^static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};$/;"	v	file:
fa_th_nolink	phy.c	/^static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};$/;"	v	file:
fahm_denom_opt	core.h	/^	u8 fahm_denom_opt;$/;"	m	struct:rtw89_ccx_para_info
fahm_denom_opt	core.h	/^	u8 fahm_denom_opt;$/;"	m	struct:rtw89_env_monitor_info
fahm_denom_ratio	core.h	/^	u8 fahm_denom_ratio;$/;"	m	struct:rtw89_env_monitor_info
fahm_denom_result	core.h	/^	u16 fahm_denom_result;$/;"	m	struct:rtw89_env_monitor_info
fahm_manual_th0	core.h	/^	u8 fahm_manual_th0;$/;"	m	struct:rtw89_ccx_para_info
fahm_manual_th_ofst	core.h	/^	u8 fahm_manual_th_ofst;$/;"	m	struct:rtw89_ccx_para_info
fahm_mntr_time	core.h	/^	u16 fahm_mntr_time;$/;"	m	struct:rtw89_env_monitor_info
fahm_numer_opt	core.h	/^	u8 fahm_numer_opt;$/;"	m	struct:rtw89_ccx_para_info
fahm_numer_opt	core.h	/^	u8 fahm_numer_opt;$/;"	m	struct:rtw89_env_monitor_info
fahm_pwr	core.h	/^	u8 fahm_pwr;$/;"	m	struct:rtw89_env_monitor_info
fahm_ratio	core.h	/^	u8 fahm_ratio;$/;"	m	struct:rtw89_env_monitor_info
fahm_result	core.h	/^	u16 fahm_result[RTW89_FAHM_RPT_NUM];$/;"	m	struct:rtw89_env_monitor_info
fahm_result_sum	core.h	/^	u16 fahm_result_sum;$/;"	m	struct:rtw89_env_monitor_info
fahm_rpt	core.h	/^	u8 fahm_rpt[RTW89_FAHM_RPT_NUM];$/;"	m	struct:rtw89_env_monitor_info
fahm_th	core.h	/^	u8 fahm_th[RTW89_FAHM_TH_NUM];$/;"	m	struct:rtw89_env_monitor_info
feature	core.h	/^	__le32 feature;$/;"	m	struct:rtw89_btc_fbtc_btver
feature	core.h	/^	u32 feature;$/;"	m	struct:rtw89_btc_bt_info
fem	core.h	/^	struct rtw89_fem_info fem;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_fem_info
fem_setup	core.h	/^	void (*fem_setup)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
fifo_size	core.h	/^	u32 fifo_size;$/;"	m	struct:rtw89_chip_info
file_ops_common_rw	debug.c	/^static const struct file_operations file_ops_common_rw = {$/;"	v	typeref:struct:file_operations	file:
file_ops_single_r	debug.c	/^static const struct file_operations file_ops_single_r = {$/;"	v	typeref:struct:file_operations	file:
file_ops_single_w	debug.c	/^static const struct file_operations file_ops_single_w = {$/;"	v	typeref:struct:file_operations	file:
finfo	core.h	/^	struct rtw89_btc_fbtc_btafh finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btafh	typeref:struct:rtw89_btc_rpt_fbtc_btafh::rtw89_btc_fbtc_btafh
finfo	core.h	/^	struct rtw89_btc_fbtc_btdevinfo finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btdev	typeref:struct:rtw89_btc_rpt_fbtc_btdev::rtw89_btc_fbtc_btdevinfo
finfo	core.h	/^	struct rtw89_btc_fbtc_btscan finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btscan	typeref:struct:rtw89_btc_rpt_fbtc_btscan::rtw89_btc_fbtc_btscan
finfo	core.h	/^	struct rtw89_btc_fbtc_btver finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_btver	typeref:struct:rtw89_btc_rpt_fbtc_btver::rtw89_btc_fbtc_btver
finfo	core.h	/^	struct rtw89_btc_fbtc_cynullsta finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_nullsta	typeref:struct:rtw89_btc_rpt_fbtc_nullsta::rtw89_btc_fbtc_cynullsta
finfo	core.h	/^	struct rtw89_btc_fbtc_cysta finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_cysta	typeref:struct:rtw89_btc_rpt_fbtc_cysta::rtw89_btc_fbtc_cysta
finfo	core.h	/^	struct rtw89_btc_fbtc_gpio_dbg finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_gpio_dbg	typeref:struct:rtw89_btc_rpt_fbtc_gpio_dbg::rtw89_btc_fbtc_gpio_dbg
finfo	core.h	/^	struct rtw89_btc_fbtc_mreg_val finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_mreg	typeref:struct:rtw89_btc_rpt_fbtc_mreg::rtw89_btc_fbtc_mreg_val
finfo	core.h	/^	struct rtw89_btc_fbtc_rpt_ctrl finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_report_ctrl_state	typeref:struct:rtw89_btc_report_ctrl_state::rtw89_btc_fbtc_rpt_ctrl
finfo	core.h	/^	struct rtw89_btc_fbtc_slots finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_slots	typeref:struct:rtw89_btc_rpt_fbtc_slots::rtw89_btc_fbtc_slots
finfo	core.h	/^	struct rtw89_btc_fbtc_steps finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_step	typeref:struct:rtw89_btc_rpt_fbtc_step::rtw89_btc_fbtc_steps
finfo	core.h	/^	struct rtw89_btc_fbtc_tdma finfo; \/* info from fw *\/$/;"	m	struct:rtw89_btc_rpt_fbtc_tdma	typeref:struct:rtw89_btc_rpt_fbtc_tdma::rtw89_btc_fbtc_tdma
firmware	core.h	/^	const struct firmware *firmware;$/;"	m	struct:rtw89_fw_info	typeref:struct:rtw89_fw_info::firmware
first_rate	debug.c	/^	enum rtw89_hw_rate first_rate;$/;"	m	struct:rtw89_rx_rate_cnt_info	typeref:enum:rtw89_rx_rate_cnt_info::rtw89_hw_rate	file:
fixed_csi_rate_en	core.h	/^	u8 fixed_csi_rate_en:1;$/;"	m	struct:rtw89_ra_info
flag	core.h	/^	u8 flag; \/* recognized by parsers *\/$/;"	m	struct:rtw89_reg5_def
flags	core.h	/^	unsigned long flags;$/;"	m	struct:rtw89_txq
flush_queues	core.h	/^	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);$/;"	m	struct:rtw89_hci_ops
flush_time	core.h	/^	__le32 flush_time;$/;"	m	struct:rtw89_btc_fbtc_btdevinfo
flush_time	core.h	/^	u32 flush_time;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
force_gaincode	core.h	/^	struct rtw89_agc_gaincode_set force_gaincode;$/;"	m	struct:rtw89_dig_info	typeref:struct:rtw89_dig_info::rtw89_agc_gaincode_set
force_gaincode_idx_en	core.h	/^	bool force_gaincode_idx_en;$/;"	m	struct:rtw89_dig_info
frag	core.h	/^	u8 frag;$/;"	m	struct:rtw89_rx_desc_info
frame_type	core.h	/^	u8 frame_type;$/;"	m	struct:rtw89_rx_desc_info
free_pages	pci.h	/^	struct list_head free_pages;$/;"	m	struct:rtw89_pci_tx_wd_ring	typeref:struct:rtw89_pci_tx_wd_ring::list_head
free_run_cnt	core.h	/^	u32 free_run_cnt;$/;"	m	struct:rtw89_rx_desc_info
freerun	core.h	/^	u32 freerun: 1;$/;"	m	struct:rtw89_btc_dm
frm_tgt_ind	core.h	/^	u8 frm_tgt_ind;$/;"	m	struct:rtw89_vif
fs	pci.h	/^	u32 fs:1, ls:1, tag:11, len:14;$/;"	m	struct:rtw89_pci_rx_info
func	fw.h	/^	u32 func:7;$/;"	m	struct:rtw89_c2h_phy_cap
func	fw.h	/^	u8 func:7;$/;"	m	struct:rtw89_h2creg_sch_tx_en
fver	coex.c	/^	u8 fver;$/;"	m	struct:btc_fbtc_1slot	file:
fver	coex.c	/^	u8 fver;$/;"	m	struct:rtw89_btc_btf_set_mon_reg	file:
fver	coex.c	/^	u8 fver;$/;"	m	struct:rtw89_btc_btf_set_report	file:
fver	coex.c	/^	u8 fver;$/;"	m	struct:rtw89_btc_btf_set_slot_table	file:
fver	coex.c	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
fver	core.h	/^	u16 fver;$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_btafh
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_btdevinfo
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_btscan
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_btver
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_cynullsta
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_cysta
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_mreg_val
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_slots
fver	core.h	/^	u8 fver;$/;"	m	struct:rtw89_btc_fbtc_steps
fver_mismch	core.h	/^	u32 fver_mismch;$/;"	m	struct:rtw89_btc_btf_fwinfo
fw	core.h	/^	struct rtw89_fw_info fw;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_fw_info
fw	core.h	/^	u32 fw;$/;"	m	struct:rtw89_btc_bt_ver_info
fw	core.h	/^	u32 fw;$/;"	m	struct:rtw89_btc_wl_ver_info
fw_coex	core.h	/^	u32 fw_coex; \/* match with which coex_ver *\/$/;"	m	struct:rtw89_btc_bt_ver_info
fw_coex	core.h	/^	u32 fw_coex; \/* match with which coex_ver *\/$/;"	m	struct:rtw89_btc_wl_ver_info
fw_dl	core.h	/^	bool fw_dl;$/;"	m	struct:rtw89_tx_desc_info
fw_log_enable	core.h	/^	bool fw_log_enable;$/;"	m	struct:rtw89_fw_info
fw_name	core.h	/^	const char *fw_name;$/;"	m	struct:rtw89_chip_info
fw_nr	fw.h	/^	u8 fw_nr;$/;"	m	struct:rtw89_mfw_hdr
fw_ver	core.h	/^	__le32 fw_ver;$/;"	m	struct:rtw89_btc_fbtc_btver
fwcmd_hdr	fw.h	/^struct fwcmd_hdr {$/;"	s
fwinfo	core.h	/^	struct rtw89_btc_btf_fwinfo fwinfo;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_btf_fwinfo
g0_aval	core.h	/^	u16 g0_aval;$/;"	m	struct:rtw89_hfc_pub_info
g0_used	core.h	/^	u16 g0_used;$/;"	m	struct:rtw89_hfc_pub_info
g1_aval	core.h	/^	u16 g1_aval;$/;"	m	struct:rtw89_hfc_pub_info
g1_used	core.h	/^	u16 g1_used;$/;"	m	struct:rtw89_hfc_pub_info
get_dle_mem_cfg	mac.c	/^static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,$/;"	f	file:
get_efuse_blk_idx	efuse.c	64;"	d	file:
get_hdr_bssid	core.h	/^static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)$/;"	f
get_he_ra_mask	phy.c	/^static u64 get_he_ra_mask(struct ieee80211_sta *sta)$/;"	f	file:
get_max_amsdu_len	phy.c	/^static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,$/;"	f	file:
get_mcs_ra_mask	phy.c	/^static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)$/;"	f	file:
get_phy_compare	phy.h	15;"	d
get_phy_cond	phy.h	18;"	d
get_phy_cond_cv	phy.h	21;"	d
get_phy_cond_pkg	phy.h	20;"	d
get_phy_cond_rfe	phy.h	19;"	d
get_phy_headline	phy.h	12;"	d
get_phy_target	phy.h	14;"	d
get_thermal	core.h	/^	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);$/;"	m	struct:rtw89_chip_ops
gi_ltf	core.h	/^	u8 gi_ltf;$/;"	m	struct:rtw89_rx_desc_info
giltf	core.h	/^	u8 giltf:3;$/;"	m	struct:rtw89_ra_info
gnt	core.h	/^	struct rtw89_mac_ax_coex_gnt gnt;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_mac_ax_coex_gnt
gnt_bt	core.h	/^	u8 gnt_bt;$/;"	m	struct:rtw89_mac_ax_gnt
gnt_bt_sw_en	core.h	/^	u8 gnt_bt_sw_en;$/;"	m	struct:rtw89_mac_ax_gnt
gnt_wl	core.h	/^	u8 gnt_wl;$/;"	m	struct:rtw89_mac_ax_gnt
gnt_wl_sw_en	core.h	/^	u8 gnt_wl_sw_en;$/;"	m	struct:rtw89_mac_ax_gnt
golden_rx_shift	core.h	/^	u8 golden_rx_shift[BTC_PROFILE_MAX];$/;"	m	struct:rtw89_btc_bt_link_info
gpio_map	core.h	/^	u8 gpio_map[BTC_DBG_MAX1]; \/*the debug signals to GPIO-Position *\/$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
grp	core.h	/^	u8 grp;$/;"	m	struct:rtw89_hfc_ch_cfg
grp0	core.h	/^	u16 grp0;$/;"	m	struct:rtw89_hfc_pub_cfg
grp1	core.h	/^	u16 grp1;$/;"	m	struct:rtw89_hfc_pub_cfg
grp_0	core.h	2061;"	d
grp_1	core.h	2062;"	d
grp_num	core.h	2063;"	d
grpsel	mac.h	/^	u32 grpsel;$/;"	m	struct:rtw89_mac_dle_dfi_qempty
gs	core.h	/^	u8 gs;$/;"	m	struct:rtw89_dpk_bkup_para
h2c	core.h	/^	u16 h2c;$/;"	m	struct:rtw89_ple_quota
h2c	core.h	/^	u8 *h2c;$/;"	m	struct:rtw89_early_h2c
h2c_cnt	core.h	/^	u32 h2c_cnt; \/* fw recv h2c counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
h2c_en	core.h	/^	bool h2c_en;$/;"	m	struct:rtw89_hfc_param
h2c_full_cond	core.h	/^	u8 h2c_full_cond;$/;"	m	struct:rtw89_hfc_prec_cfg
h2c_len	core.h	/^	u16 h2c_len;$/;"	m	struct:rtw89_early_h2c
h2c_prec	core.h	/^	u16 h2c_prec;$/;"	m	struct:rtw89_hfc_prec_cfg
h2c_queue	pci.h	/^	struct sk_buff_head h2c_queue;$/;"	m	struct:rtw89_pci	typeref:struct:rtw89_pci::sk_buff_head
h2c_release_queue	pci.h	/^	struct sk_buff_head h2c_release_queue;$/;"	m	struct:rtw89_pci	typeref:struct:rtw89_pci::sk_buff_head
h2c_seq	core.h	/^	u8 h2c_seq;$/;"	m	struct:rtw89_fw_info
h2creg	fw.h	/^	u32 h2creg[RTW89_H2CREG_MAX];$/;"	m	struct:rtw89_mac_h2c_info
hal	core.h	/^	struct rtw89_hal hal;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_hal
hal_enable_dma	ser.c	/^static int hal_enable_dma(struct rtw89_ser *ser)$/;"	f	file:
hal_send_m2_event	ser.c	/^static void hal_send_m2_event(struct rtw89_ser *ser)$/;"	f	file:
hal_send_m4_event	ser.c	/^static void hal_send_m4_event(struct rtw89_ser *ser)$/;"	f	file:
hal_stop_dma	ser.c	/^static int hal_stop_dma(struct rtw89_ser *ser)$/;"	f	file:
halt_c2h_intrs	pci.h	/^	u32 halt_c2h_intrs;$/;"	m	struct:rtw89_pci
halt_c2h_isrs	pci.h	/^	u32 halt_c2h_isrs;$/;"	m	struct:rtw89_pci_isrs
hb0	coex.c	/^	struct btc_btinfo_hb0 hb0;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_hb0	file:
hb1	coex.c	/^	struct btc_btinfo_hb1 hb1;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_hb1	file:
hb2	coex.c	/^	struct btc_btinfo_hb2 hb2;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_hb2	file:
hb3	coex.c	/^	struct btc_btinfo_hb3 hb3;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_hb3	file:
hci	core.h	/^	struct rtw89_hci_info hci;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_hci_info
hdr0	fw.h	/^	__le32 hdr0;$/;"	m	struct:fwcmd_hdr
hdr1	fw.h	/^	__le32 hdr1;$/;"	m	struct:fwcmd_hdr
hdr_len	fw.h	/^	u32 hdr_len;$/;"	m	struct:rtw89_fw_bin_info
hdr_llc_len	core.h	/^	u8 hdr_llc_len;$/;"	m	struct:rtw89_tx_desc_info
head	pci.h	/^	void *head;$/;"	m	struct:rtw89_pci_dma_ring
head	pci.h	/^	void *head;$/;"	m	struct:rtw89_pci_tx_wd_ring
hedcm	core.h	/^	s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];$/;"	m	struct:rtw89_txpwr_byrate
hfc_ch_cfg_chk	mac.c	/^static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
hfc_ch_ctrl	mac.c	/^static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
hfc_func_en	mac.c	/^static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)$/;"	f	file:
hfc_h2c_cfg	mac.c	/^static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_init	mac.c	/^static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)$/;"	f	file:
hfc_mix_cfg	mac.c	/^static void hfc_mix_cfg(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_param	core.h	/^	struct rtw89_hfc_param hfc_param;$/;"	m	struct:rtw89_mac_info	typeref:struct:rtw89_mac_info::rtw89_hfc_param
hfc_param_ini	core.h	/^	const struct rtw89_hfc_param_ini *hfc_param_ini;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_hfc_param_ini
hfc_pub_cfg_chk	mac.c	/^static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_pub_ctrl	mac.c	/^static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_pub_info_chk	mac.c	/^static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_reset_param	mac.c	/^static int hfc_reset_param(struct rtw89_dev *rtwdev)$/;"	f	file:
hfc_upd_ch_info	mac.c	/^static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)$/;"	f	file:
hfc_upd_mix_info	mac.c	/^static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)$/;"	f	file:
hfp	coex.c	/^	u8 hfp: 1;$/;"	m	struct:btc_btinfo_lb2	file:
hfp_desc	core.h	/^	struct rtw89_btc_bt_hfp_desc hfp_desc;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bt_hfp_desc
hi_lna_rx	core.h	/^	u32 hi_lna_rx: 1;$/;"	m	struct:rtw89_btc_bt_info
hid	coex.c	/^	u8 hid: 1;$/;"	m	struct:btc_btinfo_lb2	file:
hid_cnt	coex.c	/^	u8 hid_cnt: 2;$/;"	m	struct:btc_btinfo_hb2	file:
hid_desc	core.h	/^	struct rtw89_btc_bt_hid_desc hid_desc;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bt_hid_desc
hid_slot	coex.c	/^	u8 hid_slot: 2;$/;"	m	struct:btc_btinfo_hb2	file:
hif	core.h	/^	u16 hif;$/;"	m	struct:rtw89_wde_quota
hit_rule	core.h	/^	u8 hit_rule;$/;"	m	struct:rtw89_vif
htc_om_channel_width	core.h	/^enum htc_om_channel_width {$/;"	g
htc_template	core.h	/^	__le32 htc_template;$/;"	m	struct:rtw89_sta
hw	core.h	/^	struct ieee80211_hw *hw;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::ieee80211_hw
hw_coex	core.h	/^	u8 hw_coex;$/;"	m	struct:rtw89_btc_3rdcx_info
hw_dec	core.h	/^	bool hw_dec;$/;"	m	struct:rtw89_rx_desc_info
hw_rate	core.h	/^	u16 hw_rate;$/;"	m	struct:rtw89_ra_report
hw_type	fw.h	/^	u32 hw_type:8;$/;"	m	struct:rtw89_c2h_phy_cap
ib_pbk	core.h	/^	u8 ib_pbk;$/;"	m	struct:rtw89_dig_info
ib_pkpwr	core.h	/^	s8 ib_pkpwr;$/;"	m	struct:rtw89_dig_info
icmp_notify_work	core.h	/^	struct work_struct icmp_notify_work;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::work_struct
icv_err	core.h	/^	bool icv_err;$/;"	m	struct:rtw89_rx_desc_info
id	fw.h	/^	u8 id;$/;"	m	struct:rtw89_mac_c2h_info
id	fw.h	/^	u8 id;$/;"	m	struct:rtw89_mac_h2c_info
idx	core.h	/^	u8 idx;$/;"	m	struct:rtw89_rate_desc
ifs_clm_app	core.h	/^	enum rtw89_ifs_clm_application ifs_clm_app;$/;"	m	struct:rtw89_ccx_para_info	typeref:enum:rtw89_ccx_para_info::rtw89_ifs_clm_application
ifs_clm_app	core.h	/^	enum rtw89_ifs_clm_application ifs_clm_app;$/;"	m	struct:rtw89_env_monitor_info	typeref:enum:rtw89_env_monitor_info::rtw89_ifs_clm_application
ifs_clm_avg	core.h	/^	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cca	core.h	/^	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cca_avg	core.h	/^	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cck_cca_excl_fa_ratio	core.h	/^	u8 ifs_clm_cck_cca_excl_fa_ratio;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cck_fa_permil	core.h	/^	u16 ifs_clm_cck_fa_permil;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cck_fa_ratio	core.h	/^	u8 ifs_clm_cck_fa_ratio;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cckcca_excl_fa	core.h	/^	u16 ifs_clm_cckcca_excl_fa;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_cckfa	core.h	/^	u16 ifs_clm_cckfa;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_edcca_excl_cca	core.h	/^	u16 ifs_clm_edcca_excl_cca;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_edcca_excl_cca_ratio	core.h	/^	u8 ifs_clm_edcca_excl_cca_ratio;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_his	core.h	/^	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ifs_avg	core.h	/^	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_manual_th0	core.h	/^	u32 ifs_clm_manual_th0;$/;"	m	struct:rtw89_ccx_para_info
ifs_clm_manual_th_times	core.h	/^	u32 ifs_clm_manual_th_times;$/;"	m	struct:rtw89_ccx_para_info
ifs_clm_mntr_time	core.h	/^	u16 ifs_clm_mntr_time;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ofdm_cca_excl_fa_ratio	core.h	/^	u8 ifs_clm_ofdm_cca_excl_fa_ratio;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ofdm_fa_permil	core.h	/^	u16 ifs_clm_ofdm_fa_permil;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ofdm_fa_ratio	core.h	/^	u8 ifs_clm_ofdm_fa_ratio;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ofdmcca_excl_fa	core.h	/^	u16 ifs_clm_ofdmcca_excl_fa;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_ofdmfa	core.h	/^	u16 ifs_clm_ofdmfa;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_th_h	core.h	/^	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_th_l	core.h	/^	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_total_ifs	core.h	/^	u16 ifs_clm_total_ifs;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_tx	core.h	/^	u16 ifs_clm_tx;$/;"	m	struct:rtw89_env_monitor_info
ifs_clm_tx_ratio	core.h	/^	u8 ifs_clm_tx_ratio;$/;"	m	struct:rtw89_env_monitor_info
igi_fa_rssi	core.h	/^	u8 igi_fa_rssi;$/;"	m	struct:rtw89_dig_info
igi_max_performance_mode	phy.c	/^static const u8 igi_max_performance_mode = 0x5a;$/;"	v	file:
igi_rssi	core.h	/^	u8 igi_rssi;$/;"	m	struct:rtw89_dig_info
igi_rssi_th	core.h	/^	u8 igi_rssi_th[IGI_RSSI_TH_NUM];$/;"	m	struct:rtw89_dig_info
igi_rssi_th	phy.c	/^static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};$/;"	v	file:
igno_bt	core.h	/^	u32 igno_bt: 1;$/;"	m	struct:rtw89_btc_ctrl
igno_wl	coex.c	/^	u8 igno_wl: 1;$/;"	m	struct:btc_btinfo_hb1	file:
igno_wl	core.h	/^	u32 igno_wl: 1;$/;"	m	struct:rtw89_btc_bt_info
info	fw.h	/^	struct rtw89_mfw_info info[];$/;"	m	struct:rtw89_mfw_hdr	typeref:struct:rtw89_mfw_hdr::rtw89_mfw_info
init	core.h	/^	u32 init: 1;$/;"	m	struct:rtw89_btc_dm_emap
init_info	core.h	/^	struct rtw89_btc_init_info init_info; \/* pass to wl_fw if offload *\/$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_init_info
init_ok	core.h	/^	u32 init_ok: 1;$/;"	m	struct:rtw89_btc_wl_smap
init_rate_lv	core.h	/^	u8 init_rate_lv:2;$/;"	m	struct:rtw89_ra_info
init_txpwr_unit	core.h	/^	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);$/;"	m	struct:rtw89_chip_ops
inq	coex.c	/^	u8 inq: 1;$/;"	m	struct:btc_btinfo_lb3	file:
inq	core.h	/^	u32 inq: 1;$/;"	m	struct:rtw89_btc_bt_info
inq_pag	coex.c	/^	u8 inq_pag: 1;$/;"	m	struct:btc_btinfo_lb2	file:
inq_pag	core.h	/^	struct rtw89_btc_bool_sta_chg inq_pag;$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_bool_sta_chg
inq_pag	core.h	/^	u32 inq_pag: 1;$/;"	m	struct:rtw89_btc_bt_smap
interlace	core.h	/^	u32 interlace: 1;$/;"	m	struct:rtw89_btc_bt_scan_info
intf_msk	mac.h	/^	u8 intf_msk;$/;"	m	struct:rtw89_pwr_cfg
intrs	pci.h	/^	u32 intrs[2];$/;"	m	struct:rtw89_pci
intvl	core.h	/^	u16 intvl;$/;"	m	struct:rtw89_btc_bt_scan_info
invalid_efuse_content	efuse.c	62;"	d	file:
invalid_efuse_header	efuse.c	60;"	d	file:
ips	core.h	/^	u32 ips: 1;$/;"	m	struct:rtw89_btc_wl_smap
iqk	core.h	/^	struct rtw89_iqk_info iqk;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_iqk_info
iqk_band	core.h	/^	u8 iqk_band[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_bw	core.h	/^	u8 iqk_bw[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_cfir_en	core.h	/^	bool iqk_cfir_en;$/;"	m	struct:rtw89_iqk_info
iqk_ch	core.h	/^	u8 iqk_ch[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_channel	core.h	/^	u32 iqk_channel[RTW89_IQK_CHS_NR];$/;"	m	struct:rtw89_iqk_info
iqk_fail_cnt	core.h	/^	u32 iqk_fail_cnt;$/;"	m	struct:rtw89_iqk_info
iqk_fft_en	core.h	/^	bool iqk_fft_en;$/;"	m	struct:rtw89_iqk_info
iqk_lck	rtw8852a.h	/^	u8 iqk_lck;$/;"	m	struct:rtw8852a_efuse
iqk_mcc_ch	core.h	/^	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_rx_fail	core.h	/^	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_sram_en	core.h	/^	bool iqk_sram_en;$/;"	m	struct:rtw89_iqk_info
iqk_table_idx	core.h	/^	u8 iqk_table_idx[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_times	core.h	/^	u8 iqk_times;$/;"	m	struct:rtw89_iqk_info
iqk_tx_fail	core.h	/^	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
iqk_xym_en	core.h	/^	bool iqk_xym_en;$/;"	m	struct:rtw89_iqk_info
irq_lock	pci.h	/^	spinlock_t irq_lock;$/;"	m	struct:rtw89_pci
is_adjust	core.h	/^	bool is_adjust;$/;"	m	struct:rtw89_cfo_tracking_info
is_bmc	core.h	/^	bool is_bmc;$/;"	m	struct:rtw89_tx_desc_info
is_bt_iqk_timeout	core.h	/^	bool is_bt_iqk_timeout;$/;"	m	struct:rtw89_dev
is_cck	rtw8852a.h	/^	u8 is_cck:1;$/;"	m	struct:rtw8852a_bb_pmac_info
is_dbg_port_valid	debug.c	/^static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)$/;"	f	file:
is_dis_ra	core.h	/^	u8 is_dis_ra:1;$/;"	m	struct:rtw89_ra_info
is_dpk_enable	core.h	/^	bool is_dpk_enable;$/;"	m	struct:rtw89_dpk_info
is_dpk_reload_en	core.h	/^	bool is_dpk_reload_en;$/;"	m	struct:rtw89_dpk_info
is_hesta	core.h	/^	bool is_hesta;$/;"	m	struct:rtw89_vif
is_iqk_init	core.h	/^	bool is_iqk_init;$/;"	m	struct:rtw89_iqk_info
is_linked_pre	core.h	/^	bool is_linked_pre;$/;"	m	struct:rtw89_dig_info
is_nbiqk	core.h	/^	bool is_nbiqk;$/;"	m	struct:rtw89_iqk_info
is_noisy	core.h	/^	u8 is_noisy;$/;"	m	struct:rtw89_phy_ch_info
is_qta_dbcc	mac.c	/^static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)$/;"	f	file:
is_sta_change	coex.c	/^	bool is_sta_change;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	file:
is_traffic_change	coex.c	/^	bool is_traffic_change;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	file:
is_tssi_mode	core.h	/^	bool is_tssi_mode[RF_PATH_MAX];$/;"	m	struct:rtw89_dev
is_wb_rxiqk	core.h	/^	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
is_wb_txiqk	core.h	/^	bool is_wb_txiqk[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
isolation	core.h	/^	u8 isolation;$/;"	m	struct:rtw89_btc_ant_info
isrs	pci.h	/^	u32 isrs[2];$/;"	m	struct:rtw89_pci_isrs
kcount	core.h	/^	u8 kcount;$/;"	m	struct:rtw89_iqk_info
key	core.h	/^	u8 key[32];$/;"	m	struct:rtw89_sec_cam_entry
last	core.h	/^	u32 last: 1;$/;"	m	struct:rtw89_btc_bool_sta_chg
last	core.h	/^	u8 last;$/;"	m	struct:rtw89_btc_u8_sta_chg
last_a_ctrl	core.h	/^	bool last_a_ctrl;$/;"	m	struct:rtw89_vif
last_pkt_stat	core.h	/^	struct rtw89_pkt_stat last_pkt_stat;$/;"	m	struct:rtw89_phy_stat	typeref:struct:rtw89_phy_stat::rtw89_pkt_stat
lastrpwm	core.h	/^	u8 lastrpwm; \/* enum rtw89_last_rpwm_mode *\/$/;"	m	struct:rtw89_lps_parm
lb2	coex.c	/^	struct btc_btinfo_lb2 lb2;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_lb2	file:
lb3	coex.c	/^	struct btc_btinfo_lb3 lb3;$/;"	m	union:btc_btinfo	typeref:struct:btc_btinfo::btc_btinfo_lb3	file:
ldpc_cap	core.h	/^	u8 ldpc_cap:1;$/;"	m	struct:rtw89_ra_info
leak_ap	core.h	/^	u32 leak_ap: 1;$/;"	m	struct:rtw89_btc_dm
leak_n	core.h	/^	u8 leak_n;$/;"	m	struct:rtw89_btc_fbtc_tdma
leakrx_cnt	coex.c	/^	u32 leakrx_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
leakrx_cnt	core.h	/^	__le32 leakrx_cnt; \/* the rximr occur at leak slot  *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
len	coex.c	/^	__le16 len;$/;"	m	struct:rtw89_btc_prpt	file:
len	coex.c	/^	u8 len;$/;"	m	struct:rtw89_btc_btf_tlv	file:
len	core.h	/^	u32 len;$/;"	m	struct:rtw89_rx_phy_ppdu
len	core.h	/^	u8 len;$/;"	m	struct:rtw89_addr_cam_entry
len	core.h	/^	u8 len;$/;"	m	struct:rtw89_bssid_cam_entry
len	core.h	/^	u8 len;$/;"	m	struct:rtw89_sec_cam_entry
len	debug.c	/^			u32 len;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon5	file:
len	debug.c	/^			u8 len;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon2	file:
len	debug.c	/^	int len;$/;"	m	struct:rtw89_rx_rate_cnt_info	file:
len	debug.c	/^	u8 len;$/;"	m	struct:txpwr_ent	file:
len	fw.h	/^	u32 len:4;$/;"	m	struct:rtw89_c2h_phy_cap
len	fw.h	/^	u32 len;$/;"	m	struct:rtw89_fw_hdr_section_info
len	pci.h	/^	u32 fs:1, ls:1, tag:11, len:14;$/;"	m	struct:rtw89_pci_rx_info
len	pci.h	/^	u32 len;$/;"	m	struct:rtw89_pci_dma_ring
len	pci.h	/^	u32 len;$/;"	m	struct:rtw89_pci_tx_wd
len	phy.h	/^	u8 len;$/;"	m	struct:rtw89_txpwr_byrate_cfg
len_mismch	core.h	/^	u32 len_mismch;$/;"	m	struct:rtw89_btc_btf_fwinfo
length	pci.h	/^	__le16 length;$/;"	m	struct:rtw89_pci_tx_addr_info_32
length	pci.h	/^	__le16 length;$/;"	m	struct:rtw89_pci_tx_bd_32
limit_efuse_size	core.h	/^	u32 limit_efuse_size;$/;"	m	struct:rtw89_chip_info
link_info	core.h	/^	struct rtw89_btc_bt_link_info link_info;$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_bt_link_info
link_info	core.h	/^	struct rtw89_btc_wl_link_info link_info[RTW89_MAX_HW_PORT_NUM];$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_link_info
link_mode	core.h	/^	u8 link_mode;$/;"	m	struct:rtw89_btc_wl_role_info
list	core.h	/^	struct list_head list;$/;"	m	struct:rtw89_early_h2c	typeref:struct:rtw89_early_h2c::list_head
list	core.h	/^	struct list_head list;$/;"	m	struct:rtw89_txq	typeref:struct:rtw89_txq::list_head
list	core.h	/^	struct list_head list;$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::list_head
list	pci.h	/^	struct list_head list;$/;"	m	struct:rtw89_pci_tx_wd	typeref:struct:rtw89_pci_tx_wd::list_head
list	ser.c	/^	struct list_head list;$/;"	m	struct:ser_msg	typeref:struct:ser_msg::list_head	file:
lna_gain	core.h	/^	s8 *lna_gain;$/;"	m	struct:rtw89_dig_info
lna_gain_a	core.h	/^	s8 lna_gain_a[LNA_GAIN_NUM];$/;"	m	struct:rtw89_dig_info
lna_gain_g	core.h	/^	s8 lna_gain_g[LNA_GAIN_NUM];$/;"	m	struct:rtw89_dig_info
lna_idx	core.h	/^	u8 lna_idx;$/;"	m	struct:rtw89_agc_gaincode_set
lnk_pge_num	core.h	/^	u16 lnk_pge_num;$/;"	m	struct:rtw89_dle_size
load	core.h	/^	void (*load)(struct rtw89_dev *rtwdev,$/;"	m	struct:rtw89_txpwr_table
logical_efuse_size	core.h	/^	u32 logical_efuse_size;$/;"	m	struct:rtw89_chip_info
lok_cor_fail	core.h	/^	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
lok_fin_fail	core.h	/^	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
long_rxdesc	core.h	/^	bool long_rxdesc;$/;"	m	struct:rtw89_rx_desc_info
lps	core.h	/^	bool lps;$/;"	m	struct:rtw89_btc
lps	core.h	/^	u32 lps: 1;$/;"	m	struct:rtw89_btc_wl_smap
lps_enabled	core.h	/^	bool lps_enabled;$/;"	m	struct:rtw89_dev
lps_pre	core.h	/^	u32 lps_pre: 1;$/;"	m	struct:rtw89_btc_wl_smap
ls	pci.h	/^	u32 fs:1, ls:1, tag:11, len:14;$/;"	m	struct:rtw89_pci_rx_info
lsig_txop	core.h	/^	bool lsig_txop;$/;"	m	struct:rtw89_vif
mac	core.h	/^	struct rtw89_mac_info mac;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_mac_info
mac	core.h	/^	u32 mac;$/;"	m	struct:rtw89_btc_wl_ver_info
mac_addr	core.h	/^	u8 mac_addr[ETH_ALEN];$/;"	m	struct:rtw89_btc_wl_link_info
mac_addr	core.h	/^	u8 mac_addr[ETH_ALEN];$/;"	m	struct:rtw89_vif
mac_addr	rtw8852a.h	/^	u8 mac_addr[ETH_ALEN];$/;"	m	struct:rtw8852ae_efuse
mac_addr	rtw8852a.h	/^	u8 mac_addr[ETH_ALEN];$/;"	m	struct:rtw8852au_efuse
mac_ax_err_info	mac.h	/^enum mac_ax_err_info {$/;"	g
mac_ax_func_sw	pci.h	/^enum mac_ax_func_sw {$/;"	g
mac_id	core.c	/^	u8 mac_id;$/;"	m	struct:rtw89_core_iter_rx_status	file:
mac_id	core.h	/^	u8 mac_id;$/;"	m	struct:rtw89_btc_wl_link_info
mac_id	core.h	/^	u8 mac_id;$/;"	m	struct:rtw89_rx_desc_info
mac_id	core.h	/^	u8 mac_id;$/;"	m	struct:rtw89_rx_phy_ppdu
mac_id	core.h	/^	u8 mac_id;$/;"	m	struct:rtw89_sta
mac_id	core.h	/^	u8 mac_id;$/;"	m	struct:rtw89_vif
mac_idx	core.h	/^	u8 mac_idx;$/;"	m	struct:rtw89_vif
mac_info_valid	core.h	/^	bool mac_info_valid;$/;"	m	struct:rtw89_rx_desc_info
mac_lv1_rcvy	core.h	/^	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);$/;"	m	struct:rtw89_hci_ops
mac_mem	debug.c	/^		} mac_mem;$/;"	m	union:rtw89_debugfs_priv::__anon1	typeref:struct:rtw89_debugfs_priv::__anon1::__anon5	file:
mac_mem_base_addr_table	debug.c	/^static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = {$/;"	v	file:
mac_post_init	core.h	/^	int (*mac_post_init)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
mac_pre_init	core.h	/^	int (*mac_pre_init)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
macid	core.h	/^	u8 macid;$/;"	m	struct:rtw89_lps_parm
macid	core.h	/^	u8 macid;$/;"	m	struct:rtw89_ra_info
macid	mac.h	/^	u8 macid;$/;"	m	struct:rtw89_cpuio_ctrl
mailbox	core.h	/^	u8 mailbox;$/;"	m	struct:rtw89_chip_info
major_ver	core.h	/^	u8 major_ver;$/;"	m	struct:rtw89_fw_suit
manual	core.h	/^	u32 manual: 1;$/;"	m	struct:rtw89_btc_ctrl
map	core.h	/^	struct rtw89_btc_bt_rfk_info map;$/;"	m	union:rtw89_btc_bt_rfk_info_map	typeref:struct:rtw89_btc_bt_rfk_info_map::rtw89_btc_bt_rfk_info
map	core.h	/^	struct rtw89_btc_bt_smap map;$/;"	m	union:rtw89_btc_bt_state_map	typeref:struct:rtw89_btc_bt_state_map::rtw89_btc_bt_smap
map	core.h	/^	struct rtw89_btc_dm_emap map;$/;"	m	union:rtw89_btc_dm_error_map	typeref:struct:rtw89_btc_dm_error_map::rtw89_btc_dm_emap
map	core.h	/^	struct rtw89_btc_wl_smap map;$/;"	m	union:rtw89_btc_wl_state_map	typeref:struct:rtw89_btc_wl_state_map::rtw89_btc_wl_smap
mask	core.h	/^	struct cfg80211_bitrate_mask mask;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::cfg80211_bitrate_mask
mask	core.h	/^	u32 mask;$/;"	m	struct:rtw89_reg3_def
mask	core.h	/^	u32 mask;$/;"	m	struct:rtw89_reg5_def
mask	core.h	/^	u32 mask;$/;"	m	struct:rtw89_reg_def
mask	debug.c	/^			u32 mask;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon3	file:
mask	fw.h	/^	u16 mask:16;$/;"	m	struct:rtw89_h2creg_sch_tx_en
mask	mac80211.c	/^	const struct cfg80211_bitrate_mask *mask;$/;"	m	struct:rtw89_iter_bitrate_mask_data	typeref:struct:rtw89_iter_bitrate_mask_data::cfg80211_bitrate_mask	file:
mask_grp	fw.h	/^	__le32 mask_grp[4];$/;"	m	struct:rtw89_fw_macid_pause_grp
mask_sel	core.h	/^	u8 mask_sel	: 2;$/;"	m	struct:rtw89_addr_cam_entry
max	core.h	/^	u16 max;$/;"	m	struct:rtw89_hfc_ch_cfg
max_agg_wait	core.h	/^	int max_agg_wait;$/;"	m	struct:rtw89_sta
max_amsdu_limit	core.h	/^	u16 max_amsdu_limit;$/;"	m	struct:rtw89_chip_info
max_num	pci.h	/^	u8 max_num;$/;"	m	struct:rtw89_pci_bd_ram
max_t	core.h	/^	__le32 max_t[2]; \/* max_t for 0:null0\/1:null1 *\/$/;"	m	struct:rtw89_btc_fbtc_cynullsta
mb_a2dp_empty_cnt	core.h	/^	u32 mb_a2dp_empty_cnt; \/* a2dp empty count *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mb_a2dp_flct_cnt	core.h	/^	u32 mb_a2dp_flct_cnt; \/* a2dp empty flow control counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mb_a2dp_full_cnt	core.h	/^	u32 mb_a2dp_full_cnt; \/* a2dp empty full counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mb_recv_cnt	core.h	/^	u32 mb_recv_cnt; \/* fw recv mailbox counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mb_send_fail_cnt	core.h	/^	u32 mb_send_fail_cnt; \/* fw send mailbox fail counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mb_send_ok_cnt	core.h	/^	u32 mb_send_ok_cnt; \/* fw send mailbox ok counter *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
mbx_avl	core.h	/^	u32 mbx_avl: 1;$/;"	m	struct:rtw89_btc_bt_info
mcs	core.h	/^	s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];$/;"	m	struct:rtw89_txpwr_byrate
mcs_160m	core.h	/^	s8 mcs_160m[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mcs_20m	core.h	/^	s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mcs_40m	core.h	/^	s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mcs_40m_0p5	core.h	/^	s8 mcs_40m_0p5[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mcs_40m_2p5	core.h	/^	s8 mcs_40m_2p5[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mcs_80m	core.h	/^	s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
mdinfo	core.h	/^	struct rtw89_btc_module mdinfo;$/;"	m	struct:rtw89_btc	typeref:struct:rtw89_btc::rtw89_btc_module
mesh	core.h	/^	u16 mesh: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
mesh_busy	coex.c	/^	u8 mesh_busy: 1;$/;"	m	struct:btc_btinfo_lb3	file:
mesh_busy	core.h	/^	u32 mesh_busy: 1;$/;"	m	struct:rtw89_btc_bt_smap
mgd	core.h	/^		} mgd;$/;"	m	union:rtw89_vif::__anon11	typeref:struct:rtw89_vif::__anon11::__anon12
min	core.h	/^	u16 min;$/;"	m	struct:rtw89_hfc_ch_cfg
min_num	pci.h	/^	u8 min_num;$/;"	m	struct:rtw89_pci_bd_ram
minor_ver	core.h	/^	u8 minor_ver;$/;"	m	struct:rtw89_fw_suit
mmap	pci.h	/^	void __iomem *mmap;$/;"	m	struct:rtw89_pci
mntr_time	core.h	/^	u16 mntr_time;$/;"	m	struct:rtw89_ccx_para_info
mode	core.h	/^	enum rtw89_qta_mode mode;$/;"	m	struct:rtw89_dle_mem	typeref:enum:rtw89_dle_mem::rtw89_qta_mode
mode	core.h	/^	u8 mode;$/;"	m	struct:rtw89_btc_wl_link_info
mode	core.h	/^	u8 mode;$/;"	m	struct:rtw89_hfc_param
mode	core.h	/^	u8 mode;$/;"	m	struct:rtw89_hfc_param_ini
mode	rtw8852a.h	/^	u8 mode:3;$/;"	m	struct:rtw8852a_bb_pmac_info
mode_ctrl	core.h	/^	u8 mode_ctrl:5;$/;"	m	struct:rtw89_ra_info
module	core.h	/^	struct rtw89_btc_module module;$/;"	m	struct:rtw89_btc_init_info	typeref:struct:rtw89_btc_init_info::rtw89_btc_module
module_type	rtw8852a.h	/^	u8 module_type:2;$/;"	m	struct:rtw8852a_efuse
mon_reg	core.h	/^	const struct rtw89_btc_fbtc_mreg *mon_reg;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_btc_fbtc_mreg
mon_reg_num	core.h	/^	u8 mon_reg_num;$/;"	m	struct:rtw89_chip_info
moniter	core.h	/^	u16 moniter: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
mp	fw.h	/^	u8 mp;$/;"	m	struct:rtw89_mfw_info
mpdu_proc	core.h	/^	u16 mpdu_proc;$/;"	m	struct:rtw89_ple_quota
mpdu_proc_init	mac.c	/^static int mpdu_proc_init(struct rtw89_dev *rtwdev)$/;"	f	file:
mreg_val	core.h	/^	__le32 mreg_val[CXMREG_MAX];$/;"	m	struct:rtw89_btc_fbtc_mreg_val
msbk_d	core.h	/^	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];$/;"	m	struct:rtw89_dack_info
msbk_timeout	core.h	/^	bool msbk_timeout[RTW89_DACK_PATH_NR];$/;"	m	struct:rtw89_dack_info
msg_q	core.h	/^	struct list_head msg_q;$/;"	m	struct:rtw89_ser	typeref:struct:rtw89_ser::list_head
msg_q_lock	core.h	/^	spinlock_t msg_q_lock; \/* lock when read\/write ser msg *\/$/;"	m	struct:rtw89_ser
msk	mac.h	/^	u8 msk;$/;"	m	struct:rtw89_pwr_cfg
multi_link	coex.c	/^	u8 multi_link: 1;$/;"	m	struct:btc_btinfo_hb1	file:
multi_link	core.h	/^	struct rtw89_btc_bool_sta_chg multi_link;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bool_sta_chg
mutex	core.h	/^	struct mutex mutex;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::mutex
n_regs	core.h	/^	u32 n_regs;$/;"	m	struct:rtw89_phy_table
name	ser.c	/^	char *name;$/;"	m	struct:event_ent	file:
name	ser.c	/^	char *name;$/;"	m	struct:state_ent	file:
nan	core.h	/^	u16 nan: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
napi	core.h	/^	struct napi_struct napi;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::napi_struct
napi_budget_countdown	core.h	/^	int napi_budget_countdown;$/;"	m	struct:rtw89_dev
napi_poll	core.h	/^	int (*napi_poll)(struct napi_struct *napi, int budget);$/;"	m	struct:rtw89_hci_ops
nb_rxcfir	core.h	/^	u32 nb_rxcfir[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
nb_txcfir	core.h	/^	u32 nb_txcfir[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
nctl_table	core.h	/^	const struct rtw89_phy_table *nctl_table;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_phy_table
net_type	core.h	/^	u8 net_type;$/;"	m	struct:rtw89_vif
netdev	core.h	/^	struct net_device netdev;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::net_device
nhm_cca_cnt	core.h	/^	u16 nhm_cca_cnt;$/;"	m	struct:rtw89_env_monitor_info
nhm_cca_ratio	core.h	/^	u8 nhm_cca_ratio;$/;"	m	struct:rtw89_env_monitor_info
nhm_idle_cnt	core.h	/^	u16 nhm_idle_cnt;$/;"	m	struct:rtw89_env_monitor_info
nhm_idle_ratio	core.h	/^	u8 nhm_idle_ratio;$/;"	m	struct:rtw89_env_monitor_info
nhm_manual_th0	core.h	/^	u8 nhm_manual_th0;$/;"	m	struct:rtw89_ccx_para_info
nhm_manual_th_ofst	core.h	/^	u8 nhm_manual_th_ofst;$/;"	m	struct:rtw89_ccx_para_info
nhm_mntr_time	core.h	/^	u16 nhm_mntr_time;$/;"	m	struct:rtw89_env_monitor_info
nhm_pwr	core.h	/^	u8 nhm_pwr;$/;"	m	struct:rtw89_env_monitor_info
nhm_ratio	core.h	/^	u8 nhm_ratio;$/;"	m	struct:rtw89_env_monitor_info
nhm_result	core.h	/^	u16 nhm_result[RTW89_NHM_RPT_NUM];$/;"	m	struct:rtw89_env_monitor_info
nhm_result_sum	core.h	/^	u16 nhm_result_sum;$/;"	m	struct:rtw89_env_monitor_info
nhm_rpt	core.h	/^	u8 nhm_rpt[RTW89_NHM_RPT_NUM];$/;"	m	struct:rtw89_env_monitor_info
nhm_th	core.h	/^	u8 nhm_th[RTW89_NHM_TH_NUM];$/;"	m	struct:rtw89_env_monitor_info
nhm_tx_cnt	core.h	/^	u16 nhm_tx_cnt;$/;"	m	struct:rtw89_env_monitor_info
nhm_tx_ratio	core.h	/^	u8 nhm_tx_ratio;$/;"	m	struct:rtw89_env_monitor_info
nhm_wgt	core.h	/^	u8 nhm_wgt[RTW89_NHM_RPT_NUM];$/;"	m	struct:rtw89_env_monitor_info
nic	fw.h	/^	u32 nic:8;$/;"	m	struct:rtw89_c2h_phy_cap
noa	core.h	/^	u32 noa: 1;$/;"	m	struct:rtw89_btc_wl_link_info
noa	core.h	/^	u8 noa: 1;$/;"	m	struct:rtw89_btc_wl_active_role
noisy_level	core.h	/^	u32 noisy_level: 3;$/;"	m	struct:rtw89_btc_dm
none	core.h	/^	u16 none: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
normal	core.h	/^	struct rtw89_fw_suit normal;$/;"	m	struct:rtw89_fw_info	typeref:struct:rtw89_fw_info::rtw89_fw_suit
now	core.h	/^	u32 now: 1;$/;"	m	struct:rtw89_btc_bool_sta_chg
now	core.h	/^	u8 now;$/;"	m	struct:rtw89_btc_u8_sta_chg
nss	core.h	/^	enum rtw89_nss nss;$/;"	m	struct:rtw89_rate_desc	typeref:enum:rtw89_rate_desc::rtw89_nss
nss	phy.h	/^	enum rtw89_nss nss;$/;"	m	struct:rtw89_txpwr_byrate_cfg	typeref:enum:rtw89_txpwr_byrate_cfg::rtw89_nss
num	core.h	/^	u8 num;$/;"	m	struct:rtw89_bssid_cam_entry
num	core.h	/^	u8 num;$/;"	m	struct:rtw89_btc_ant_info
ofdm	core.h	/^	s8 ofdm[RTW89_BF_NUM];$/;"	m	struct:rtw89_txpwr_limit
ofdm	core.h	/^	s8 ofdm[RTW89_RATE_OFDM_MAX];$/;"	m	struct:rtw89_txpwr_byrate
offload_mismatch	core.h	/^	u32 offload_mismatch: 1;$/;"	m	struct:rtw89_btc_dm_emap
offset	core.h	/^	__le32 offset;$/;"	m	struct:rtw89_btc_fbtc_mreg
offset	core.h	/^	s8 offset[RTW89_RATE_OFFSET_MAX];$/;"	m	struct:rtw89_txpwr_byrate
offset	core.h	/^	u16 offset;$/;"	m	struct:rtw89_rx_desc_info
offset	core.h	/^	u8 offset;$/;"	m	struct:rtw89_addr_cam_entry
offset	core.h	/^	u8 offset;$/;"	m	struct:rtw89_bssid_cam_entry
offset	core.h	/^	u8 offset;$/;"	m	struct:rtw89_sec_cam_entry
old_ht_ra_format	core.h	/^	bool old_ht_ra_format;$/;"	m	struct:rtw89_fw_info
op_band	core.h	/^	u8 op_band[RTW89_PHY_MAX]; \/* op band in each phy *\/$/;"	m	struct:rtw89_btc_wl_dbcc_info
ops	core.h	/^	const struct rtw89_chip_ops *ops;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_chip_ops
ops	core.h	/^	const struct rtw89_hci_ops *ops;$/;"	m	struct:rtw89_hci_info	typeref:struct:rtw89_hci_info::rtw89_hci_ops
option	pci.h	/^	__le16 option;$/;"	m	struct:rtw89_pci_tx_addr_info_32
option	pci.h	/^	__le16 option;$/;"	m	struct:rtw89_pci_tx_bd_32
other	core.h	/^	struct rtw89_btc_3rdcx_info other;$/;"	m	struct:rtw89_btc_cx	typeref:struct:rtw89_btc_cx::rtw89_btc_3rdcx_info
out_data	mac.h	/^	u32 out_data;$/;"	m	struct:rtw89_mac_dle_dfi_ctrl
p2p_device	core.h	/^	u16 p2p_device: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
p2p_gc	core.h	/^	u16 p2p_gc: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
p2p_go	core.h	/^	u16 p2p_go: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
pa_bias_trim	core.h	/^	u8 pa_bias_trim[RF_PATH_MAX];$/;"	m	struct:rtw89_power_trim_info
packet_count	core.h	/^	u32 packet_count;$/;"	m	struct:rtw89_cfo_tracking_info
packet_count_pre	core.h	/^	u32 packet_count_pre;$/;"	m	struct:rtw89_cfo_tracking_info
paddr	pci.h	/^	dma_addr_t paddr;$/;"	m	struct:rtw89_pci_tx_wd
pag	coex.c	/^	u8 pag: 1;$/;"	m	struct:btc_btinfo_lb3	file:
pag	core.h	/^	u32 pag: 1;$/;"	m	struct:rtw89_btc_bt_info
page_num	pci.h	/^	u32 page_num;$/;"	m	struct:rtw89_pci_tx_wd_ring
page_size	pci.h	/^	u32 page_size;$/;"	m	struct:rtw89_pci_tx_wd_ring
pages	pci.h	/^	struct rtw89_pci_tx_wd pages[RTW89_PCI_TXWD_NUM_MAX];$/;"	m	struct:rtw89_pci_tx_wd_ring	typeref:struct:rtw89_pci_tx_wd_ring::rtw89_pci_tx_wd
pair_cnt	core.h	/^	u32 pair_cnt: 2;$/;"	m	struct:rtw89_btc_bt_hid_desc
pan	coex.c	/^	u8 pan: 1;$/;"	m	struct:btc_btinfo_lb2	file:
pan_active	coex.c	/^	u8 pan_active: 1;$/;"	m	struct:btc_btinfo_hb2	file:
pan_desc	core.h	/^	struct rtw89_btc_bt_pan_desc pan_desc;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bt_pan_desc
para	coex.c	/^	__le32 para;$/;"	m	struct:rtw89_btc_btf_set_report	file:
para_ver	core.h	/^	u32 para_ver;$/;"	m	struct:rtw89_chip_info
path	core.h	/^	u8 path;$/;"	m	struct:rtw89_reg5_def
path	debug.c	/^			u8 path;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon3	file:
path_a_bw20_1tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_bw20_1tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_bw20_2tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_bw20_2tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_bw40_1tx_pwr_idx	rtw8852a.h	/^	u8 path_a_bw40_1tx_pwr_idx[5];$/;"	m	struct:rtw8852a_efuse
path_a_bw40_2tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_bw40_2tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_cck_2tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_cck_2tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_cck_pwr_idx	rtw8852a.h	/^	u8 path_a_cck_pwr_idx[6];$/;"	m	struct:rtw8852a_efuse
path_a_ofdm_1tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_ofdm_1tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_ofdm_2tx_pwr_idx_diff	rtw8852a.h	/^	u8 path_a_ofdm_2tx_pwr_idx_diff:4;$/;"	m	struct:rtw8852a_efuse
path_a_therm	rtw8852a.h	/^	u8 path_a_therm;$/;"	m	struct:rtw8852a_efuse
path_a_tssi	rtw8852a.h	/^	struct rtw8852a_tssi_offset path_a_tssi;$/;"	m	struct:rtw8852a_efuse	typeref:struct:rtw8852a_efuse::rtw8852a_tssi_offset
path_b_therm	rtw8852a.h	/^	u8 path_b_therm;$/;"	m	struct:rtw8852a_efuse
path_b_tssi	rtw8852a.h	/^	struct rtw8852a_tssi_offset path_b_tssi;$/;"	m	struct:rtw8852a_efuse	typeref:struct:rtw8852a_efuse::rtw8852a_tssi_offset
path_map	core.h	/^	u32 path_map: 4;$/;"	m	struct:rtw89_btc_wl_rfk_info
path_ok	core.h	/^	bool path_ok;$/;"	m	struct:rtw89_dpk_bkup_para
pause_grp	fw.h	/^	__le32 pause_grp[4];$/;"	m	struct:rtw89_fw_macid_pause_grp
pd_low_th_offset	phy.c	/^static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20;$/;"	v	file:
pd_low_th_ofst	core.h	/^	u8 pd_low_th_ofst;$/;"	m	struct:rtw89_dig_info
pdev	pci.h	/^	struct pci_dev *pdev;$/;"	m	struct:rtw89_pci	typeref:struct:rtw89_pci::pci_dev
period	rtw8852a.h	/^	u16 period;$/;"	m	struct:rtw8852a_bb_pmac_info
pg_pa_bias_trim	core.h	/^	bool pg_pa_bias_trim;$/;"	m	struct:rtw89_power_trim_info
pg_thermal_trim	core.h	/^	bool pg_thermal_trim;$/;"	m	struct:rtw89_power_trim_info
pge_size	core.h	/^	u16 pge_size;$/;"	m	struct:rtw89_dle_size
phy	core.h	/^	u8 phy: 1;$/;"	m	struct:rtw89_btc_wl_active_role
phy	core.h	/^	u8 phy;$/;"	m	struct:rtw89_btc_wl_link_info
phy_cfo_status	core.h	/^	enum rtw89_phy_cfo_status phy_cfo_status;$/;"	m	struct:rtw89_cfo_tracking_info	typeref:enum:rtw89_cfo_tracking_info::rtw89_phy_cfo_status
phy_cfo_trk_cnt	core.h	/^	u8 phy_cfo_trk_cnt;$/;"	m	struct:rtw89_cfo_tracking_info
phy_cfotrk_cnt	core.h	/^	u8 phy_cfotrk_cnt;$/;"	m	struct:rtw89_cfo_tracking_info
phy_cfotrk_state	core.h	/^	u8 phy_cfotrk_state;$/;"	m	struct:rtw89_cfo_tracking_info
phy_div	phy.h	22;"	d
phy_idx	core.h	/^	u8 phy_idx;$/;"	m	struct:rtw89_bssid_cam_entry
phy_idx	core.h	/^	u8 phy_idx;$/;"	m	struct:rtw89_vif
phy_map	core.h	/^	u32 phy_map: 2;$/;"	m	struct:rtw89_btc_wl_rfk_info
phy_map	core.h	/^	u8 phy_map;$/;"	m	struct:rtw89_btc_wl_scan_info
phy_ppdu	core.c	/^	struct rtw89_rx_phy_ppdu *phy_ppdu;$/;"	m	struct:rtw89_vif_rx_stats_iter_data	typeref:struct:rtw89_vif_rx_stats_iter_data::rtw89_rx_phy_ppdu	file:
phycap_addr	core.h	/^	u32 phycap_addr;$/;"	m	struct:rtw89_chip_info
phycap_size	core.h	/^	u32 phycap_size;$/;"	m	struct:rtw89_chip_info
physical_efuse_size	core.h	/^	u32 physical_efuse_size;$/;"	m	struct:rtw89_chip_info
phystat	core.h	/^	struct rtw89_phy_stat phystat;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_phy_stat
pid	core.h	/^	u8 pid: 3;$/;"	m	struct:rtw89_btc_wl_active_role
pid	core.h	/^	u8 pid;$/;"	m	struct:rtw89_btc_wl_link_info
pkt_in	core.h	/^	u16 pkt_in;$/;"	m	struct:rtw89_wde_quota
pkt_num	mac.h	/^	u16 pkt_num;$/;"	m	struct:rtw89_cpuio_ctrl
pkt_size	core.h	/^	u16 pkt_size;$/;"	m	struct:rtw89_rx_desc_info
pkt_size	core.h	/^	u16 pkt_size;$/;"	m	struct:rtw89_tx_desc_info
pkt_type	core.h	/^	u8 pkt_type;$/;"	m	struct:rtw89_rx_desc_info
pktid	mac.h	/^	u16 pktid;$/;"	m	struct:rtw89_cpuio_ctrl
play_latency	core.h	/^	u8 play_latency: 1;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
ple_max_qt	core.h	/^	const struct rtw89_ple_quota *ple_max_qt;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_ple_quota
ple_min_qt	core.h	/^	const struct rtw89_ple_quota *ple_min_qt;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_ple_quota
ple_pg_size	core.h	/^	u16 ple_pg_size;$/;"	m	struct:rtw89_dle_info
ple_qt13	mac.c	/^const struct rtw89_ple_quota ple_qt13 = {$/;"	v	typeref:struct:rtw89_ple_quota
ple_qt4	mac.c	/^const struct rtw89_ple_quota ple_qt4 = {$/;"	v	typeref:struct:rtw89_ple_quota
ple_qt5	mac.c	/^const struct rtw89_ple_quota ple_qt5 = {$/;"	v	typeref:struct:rtw89_ple_quota
ple_quota_cfg	mac.c	/^static void ple_quota_cfg(struct rtw89_dev *rtwdev,$/;"	f	file:
ple_size	core.h	/^	const struct rtw89_dle_size *ple_size;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_dle_size
ple_size0	mac.c	/^const struct rtw89_dle_size ple_size0 = {$/;"	v	typeref:struct:rtw89_dle_size
ple_size4	mac.c	/^const struct rtw89_dle_size ple_size4 = {$/;"	v	typeref:struct:rtw89_dle_size
policy	core.h	/^	u8 policy[RTW89_BTC_POLICY_MAXLEN];$/;"	m	struct:rtw89_btc
policy_len	core.h	/^	u16 policy_len;$/;"	m	struct:rtw89_btc
policy_type	core.h	/^	u16 policy_type;$/;"	m	struct:rtw89_btc
port	core.h	/^	u8 port;$/;"	m	struct:rtw89_vif
port_cfg	core.h	/^	u32 port_cfg;$/;"	m	struct:rtw89_port_reg
port_id	core.h	/^	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];$/;"	m	struct:rtw89_btc_wl_info
pos_new	core.h	/^	__le16 pos_new;$/;"	m	struct:rtw89_btc_fbtc_steps
pos_old	core.h	/^	__le16 pos_old;$/;"	m	struct:rtw89_btc_fbtc_steps
power_trim	core.h	/^	void (*power_trim)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
ppdu_cnt	core.h	/^	u8 ppdu_cnt;$/;"	m	struct:rtw89_rx_desc_info
ppdu_sts	core.h	/^	struct rtw89_ppdu_sts_info ppdu_sts;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_ppdu_sts_info
ppdu_type	core.h	/^	u8 ppdu_type;$/;"	m	struct:rtw89_rx_desc_info
pre_cfo_avg	core.h	/^	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];$/;"	m	struct:rtw89_cfo_tracking_info
pre_rssi_min	core.h	/^	u8 pre_rssi_min;$/;"	m	struct:rtw89_phy_ch_info
pre_state	core.h	/^	u32 pre_state; \/* the debug signal is 1 or 0  *\/$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
prec_cfg	core.h	/^	const struct rtw89_hfc_prec_cfg *prec_cfg;$/;"	m	struct:rtw89_hfc_param_ini	typeref:struct:rtw89_hfc_param_ini::rtw89_hfc_prec_cfg
prec_cfg	core.h	/^	struct rtw89_hfc_prec_cfg prec_cfg;$/;"	m	struct:rtw89_hfc_param	typeref:struct:rtw89_hfc_param::rtw89_hfc_prec_cfg
prev_rssi	core.h	/^	u8 prev_rssi;$/;"	m	struct:rtw89_sta
pri_ch_idx	core.h	/^	u8 pri_ch_idx;$/;"	m	struct:rtw89_channel_params
primary_chan	core.h	/^	u8 primary_chan;$/;"	m	struct:rtw89_channel_params
profile_cnt	core.h	/^	struct rtw89_btc_u8_sta_chg profile_cnt;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_u8_sta_chg
prot	fw.h	/^	u32 prot:8;$/;"	m	struct:rtw89_c2h_phy_cap
ps_mode	core.h	/^	enum rtw89_ps_mode ps_mode;$/;"	m	struct:rtw89_dev	typeref:enum:rtw89_dev::rtw89_ps_mode
ps_mode_supported	core.h	/^	u8 ps_mode_supported;$/;"	m	struct:rtw89_chip_info
psmode	core.h	/^	u8 psmode; \/* enum rtw89_mac_ax_ps_mode *\/$/;"	m	struct:rtw89_lps_parm
pta_mode	mac.h	/^	u8 pta_mode;$/;"	m	struct:rtw89_mac_ax_coex
pta_owner	core.h	/^	u32 pta_owner: 1;$/;"	m	struct:rtw89_btc_dm_emap
ptcl_init	mac.c	/^static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
pub_aval	core.h	/^	u16 pub_aval;$/;"	m	struct:rtw89_hfc_pub_info
pub_cfg	core.h	/^	const struct rtw89_hfc_pub_cfg *pub_cfg;$/;"	m	struct:rtw89_hfc_param_ini	typeref:struct:rtw89_hfc_param_ini::rtw89_hfc_pub_cfg
pub_cfg	core.h	/^	struct rtw89_hfc_pub_cfg pub_cfg;$/;"	m	struct:rtw89_hfc_param	typeref:struct:rtw89_hfc_param::rtw89_hfc_pub_cfg
pub_info	core.h	/^	struct rtw89_hfc_pub_info pub_info;$/;"	m	struct:rtw89_hfc_param	typeref:struct:rtw89_hfc_param::rtw89_hfc_pub_info
pub_max	core.h	/^	u16 pub_max;$/;"	m	struct:rtw89_hfc_pub_cfg
pwr_cmd_poll	mac.c	/^static int pwr_cmd_poll(struct rtw89_dev *rtwdev,$/;"	f	file:
pwr_off_seq	core.h	/^	const struct rtw89_pwr_cfg * const *pwr_off_seq;$/;"	m	struct:rtw89_chip_info
pwr_off_seq_8852a	rtw8852a.c	/^static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = {$/;"	v	file:
pwr_on_seq	core.h	/^	const struct rtw89_pwr_cfg * const *pwr_on_seq;$/;"	m	struct:rtw89_chip_info
pwr_on_seq_8852a	rtw8852a.c	/^static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = {$/;"	v	file:
pwr_trim	core.h	/^	struct rtw89_power_trim_info pwr_trim;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_power_trim_info
pwsf	core.h	/^	u16 pwsf;$/;"	m	struct:rtw89_dpk_bkup_para
qempty	mac.h	/^	u32 qempty;$/;"	m	struct:rtw89_mac_dle_dfi_qempty
qsel	core.h	/^	u8 qsel;$/;"	m	struct:rtw89_tx_desc_info
qta_mode	core.h	/^	enum rtw89_qta_mode qta_mode;$/;"	m	struct:rtw89_dle_info	typeref:enum:rtw89_dle_info::rtw89_qta_mode
qta_mode	core.h	/^	enum rtw89_qta_mode qta_mode;$/;"	m	struct:rtw89_mac_info	typeref:enum:rtw89_mac_info::rtw89_qta_mode
qtaid	mac.h	/^	u32 qtaid;$/;"	m	struct:rtw89_mac_dle_dfi_quota
query_ppdu	core.h	/^	void (*query_ppdu)(struct rtw89_dev *rtwdev,$/;"	m	struct:rtw89_chip_ops
query_sar_config	sar.h	/^	int (*query_sar_config)(struct rtw89_dev *rtwdev, s32 *cfg);$/;"	m	struct:rtw89_sar_handler
queue	pci.h	/^	struct sk_buff_head queue;$/;"	m	struct:rtw89_pci_tx_wd	typeref:struct:rtw89_pci_tx_wd::sk_buff_head
ra	core.h	/^	struct rtw89_ra_info ra;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::rtw89_ra_info
ra_csi_rate_en	core.h	/^	u8 ra_csi_rate_en:1;$/;"	m	struct:rtw89_ra_info
ra_mask	core.h	/^	u64 ra_mask; \/* 63 bits ra_mask + 1 bit CSI ctrl *\/$/;"	m	struct:rtw89_ra_info
ra_mask	core.h	/^	u64 ra_mask;$/;"	m	struct:rtw89_phy_rate_pattern
ra_mode	core.h	/^	u8 ra_mode;$/;"	m	struct:rtw89_phy_rate_pattern
ra_report	core.h	/^	struct rtw89_ra_report ra_report;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::rtw89_ra_report
rac_lv	core.h	/^	enum rtw89_env_racing_lv rac_lv;$/;"	m	struct:rtw89_ccx_para_info	typeref:enum:rtw89_ccx_para_info::rtw89_env_racing_lv
radio_on_off	rtw8852a.h	/^	u8 radio_on_off:1;$/;"	m	struct:rtw8852a_efuse
rate	core.h	/^	u16 rate;$/;"	m	struct:rtw89_phy_rate_pattern
rate_mode	debug.c	/^	const char *rate_mode;$/;"	m	struct:rtw89_rx_rate_cnt_info	file:
rate_pattern	core.h	/^	struct rtw89_phy_rate_pattern rate_pattern;$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::rtw89_phy_rate_pattern
raw_info	core.h	/^	u8 raw_info[BTC_BTINFO_MAX]; \/* raw bt info from mailbox *\/$/;"	m	struct:rtw89_btc_bt_info
rb_done	core.h	/^	bool rb_done;$/;"	m	struct:rtw89_btc_dbg
rb_val	core.h	/^	u32 rb_val;$/;"	m	struct:rtw89_btc_dbg
rd_addr	mac.h	/^	u32 rd_addr;$/;"	m	struct:rtw89_mac_dbg_port_info
rd_byte	mac.h	/^	u8 rd_byte;$/;"	m	struct:rtw89_mac_dbg_port_info
rd_msk	mac.h	/^	u32 rd_msk;$/;"	m	struct:rtw89_mac_dbg_port_info
read16	core.h	/^	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);$/;"	m	struct:rtw89_hci_ops
read32	core.h	/^	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);$/;"	m	struct:rtw89_hci_ops
read8	core.h	/^	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);$/;"	m	struct:rtw89_hci_ops
read_efuse	core.h	/^	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);$/;"	m	struct:rtw89_chip_ops
read_phycap	core.h	/^	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);$/;"	m	struct:rtw89_chip_ops
read_reg	debug.c	/^		} read_reg;$/;"	m	union:rtw89_debugfs_priv::__anon1	typeref:struct:rtw89_debugfs_priv::__anon1::__anon2	file:
read_rf	core.h	/^	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	m	struct:rtw89_chip_ops
read_rf	debug.c	/^		} read_rf;$/;"	m	union:rtw89_debugfs_priv::__anon1	typeref:struct:rtw89_debugfs_priv::__anon1::__anon3	file:
ready	core.h	/^	bool ready;$/;"	m	struct:rtw89_rx_desc_info
real_band	core.h	/^	u8 real_band[RTW89_PHY_MAX];$/;"	m	struct:rtw89_btc_wl_dbcc_info
rec_seq	core.h	/^	u8 rec_seq;$/;"	m	struct:rtw89_fw_info
recalc_int_mit	core.h	/^	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
redl	fw.h	/^	u8 redl;$/;"	m	struct:rtw89_fw_hdr_section_info
reenable	coex.c	/^	bool reenable;$/;"	m	struct:rtw89_txtime_data	file:
reg3	phy.h	/^	const struct rtw89_reg3_def *reg3;$/;"	m	struct:rtw89_phy_reg3_tbl	typeref:struct:rtw89_phy_reg3_tbl::rtw89_reg3_def
reg_num	coex.c	/^	u8 reg_num;$/;"	m	struct:rtw89_btc_btf_set_mon_reg	file:
reg_num	core.h	/^	u8 reg_num;$/;"	m	struct:rtw89_btc_fbtc_mreg_val
reg_setting	rtw8852a.h	/^	u8 reg_setting:2;$/;"	m	struct:rtw8852a_efuse
regd	core.h	/^	const struct rtw89_regulatory *regd;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_regulatory
regs	core.h	/^	const struct rtw89_reg2_def *regs;$/;"	m	struct:rtw89_phy_table	typeref:struct:rtw89_phy_table::rtw89_reg2_def
reinit	coex.c	/^	u8 reinit: 1;$/;"	m	struct:btc_btinfo_hb1	file:
reinit	core.h	/^	u32 reinit: 1;$/;"	m	struct:rtw89_btc_bt_info
relink	coex.c	/^	u8 relink: 1;$/;"	m	struct:btc_btinfo_hb1	file:
relink	core.h	/^	struct rtw89_btc_bool_sta_chg relink;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:struct:rtw89_btc_bt_link_info::rtw89_btc_bool_sta_chg
remain	core.h	/^	u32 remain: 1;$/;"	m	struct:rtw89_btc_bool_sta_chg
remain	core.h	/^	u8 remain;$/;"	m	struct:rtw89_btc_u8_sta_chg
req	core.h	/^	u32 req: 1;$/;"	m	struct:rtw89_btc_bt_rfk_info
req_fver	core.h	/^	u8 req_fver; \/* expected rsp fver *\/$/;"	m	struct:rtw89_btc_rpt_cmn_info
req_len	core.h	/^	u32 req_len; \/* expected rsp len *\/$/;"	m	struct:rtw89_btc_rpt_cmn_info
reset	core.h	/^	void (*reset)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
residual_cfo_acc	core.h	/^	s32 residual_cfo_acc;$/;"	m	struct:rtw89_cfo_tracking_info
result	core.h	/^	__le32 result[2][4]; \/* 0:fail, 1:ok, 2:on_time, 3:retry *\/$/;"	m	struct:rtw89_btc_fbtc_cynullsta
retry	coex.c	/^	u8 retry: 4;$/;"	m	struct:btc_btinfo_lb3	file:
rf	core.h	/^	u32 rf;$/;"	m	struct:rtw89_btc_wl_ver_info
rf_base_addr	core.h	/^	u32 rf_base_addr[2];$/;"	m	struct:rtw89_chip_info
rf_mutex	core.h	/^	struct mutex rf_mutex;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::mutex
rf_off	core.h	/^	u32 rf_off: 1;$/;"	m	struct:rtw89_btc_wl_smap
rf_off_pre	core.h	/^	u32 rf_off_pre: 1;$/;"	m	struct:rtw89_btc_wl_smap
rf_para	core.h	/^	struct rtw89_btc_rf_para rf_para;$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_rf_para
rf_para	core.h	/^	struct rtw89_btc_rf_para rf_para;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_rf_para
rf_para_dlink	core.h	/^	const struct rtw89_btc_rf_trx_para *rf_para_dlink;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_btc_rf_trx_para
rf_para_dlink_num	core.h	/^	u8 rf_para_dlink_num;$/;"	m	struct:rtw89_chip_info
rf_para_ulink	core.h	/^	const struct rtw89_btc_rf_trx_para *rf_para_ulink;$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_btc_rf_trx_para
rf_para_ulink_num	core.h	/^	u8 rf_para_ulink_num;$/;"	m	struct:rtw89_chip_info
rf_path	core.h	/^	enum rtw89_rf_path rf_path;$/;"	m	struct:rtw89_phy_table	typeref:enum:rtw89_phy_table::rtw89_rf_path
rf_path	fw.h	/^	enum rtw89_rf_path rf_path;$/;"	m	struct:rtw89_fw_h2c_rf_reg_info	typeref:enum:rtw89_fw_h2c_rf_reg_info::rtw89_rf_path
rf_path_num	core.h	/^	u8 rf_path_num;$/;"	m	struct:rtw89_chip_info
rf_table	core.h	/^	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];$/;"	m	struct:rtw89_chip_info	typeref:struct:rtw89_chip_info::rtw89_phy_table
rf_trx_para	core.h	/^	struct rtw89_btc_rf_trx_para rf_trx_para;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_rf_trx_para
rfe_type	core.h	/^	u8 rfe_type;$/;"	m	struct:rtw89_btc_module
rfe_type	core.h	/^	u8 rfe_type;$/;"	m	struct:rtw89_efuse
rfe_type	rtw8852a.h	/^	u8 rfe_type;$/;"	m	struct:rtw8852a_efuse
rfk_band_changed	core.h	/^	void (*rfk_band_changed)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
rfk_channel	core.h	/^	void (*rfk_channel)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
rfk_info	core.h	/^	struct rtw89_btc_wl_rfk_info rfk_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_rfk_info
rfk_info	core.h	/^	union rtw89_btc_bt_rfk_info_map rfk_info;$/;"	m	struct:rtw89_btc_bt_info	typeref:union:rtw89_btc_bt_info::rtw89_btc_bt_rfk_info_map
rfk_init	core.h	/^	void (*rfk_init)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
rfk_scan	core.h	/^	void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);$/;"	m	struct:rtw89_chip_ops
rfk_track	core.h	/^	void (*rfk_track)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
rmac_init	mac.c	/^static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
roaming	core.h	/^	u32 roaming: 1;$/;"	m	struct:rtw89_btc_wl_smap
role	core.h	/^	struct rtw89_btc_wl_role_info_bpos role;$/;"	m	union:rtw89_btc_wl_role_info_map	typeref:struct:rtw89_btc_wl_role_info_map::rtw89_btc_wl_role_info_bpos
role	core.h	/^	u8 role;$/;"	m	struct:rtw89_btc_wl_active_role
role	core.h	/^	u8 role;$/;"	m	struct:rtw89_btc_wl_link_info
role	core.h	/^	u8 role[RTW89_PHY_MAX]; \/* role in each phy *\/$/;"	m	struct:rtw89_btc_wl_dbcc_info
role_info	core.h	/^	struct rtw89_btc_wl_role_info role_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_role_info
role_map	core.h	/^	union rtw89_btc_wl_role_info_map role_map;$/;"	m	struct:rtw89_btc_wl_role_info	typeref:union:rtw89_btc_wl_role_info::rtw89_btc_wl_role_info_map
role_sw	coex.c	/^	u8 role_sw: 1;$/;"	m	struct:btc_btinfo_hb1	file:
role_sw	core.h	/^	u32 role_sw: 1;$/;"	m	struct:rtw89_btc_bt_link_info
rp	pci.h	/^	u32 rp; \/* hw idx *\/$/;"	m	struct:rtw89_pci_dma_ring
rpt_cnt	core.h	/^	u16 rpt_cnt; \/* tmr counters *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
rpt_ctrl	core.h	/^	struct rtw89_btc_report_ctrl_state rpt_ctrl;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_report_ctrl_state
rpt_en_map	core.h	/^	u32 rpt_en_map;$/;"	m	struct:rtw89_btc_btf_fwinfo
rpt_enable	core.h	/^	u32 rpt_enable;$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
rpt_fbtc_btafh	core.h	/^	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_btafh
rpt_fbtc_btdev	core.h	/^	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_btdev
rpt_fbtc_btscan	core.h	/^	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_btscan
rpt_fbtc_btver	core.h	/^	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_btver
rpt_fbtc_cysta	core.h	/^	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_cysta
rpt_fbtc_gpio_dbg	core.h	/^	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_gpio_dbg
rpt_fbtc_mregval	core.h	/^	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_mreg
rpt_fbtc_nullsta	core.h	/^	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_nullsta
rpt_fbtc_slots	core.h	/^	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_slots
rpt_fbtc_step	core.h	/^	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_step
rpt_fbtc_tdma	core.h	/^	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;$/;"	m	struct:rtw89_btc_btf_fwinfo	typeref:struct:rtw89_btc_btf_fwinfo::rtw89_btc_rpt_fbtc_tdma
rpt_para	core.h	/^	u32 rpt_para; \/* ms *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
rpwm_addr	core.h	/^	u32 rpwm_addr;$/;"	m	struct:rtw89_hci_info
rpwm_seq_num	core.h	/^	u8 rpwm_seq_num;$/;"	m	struct:rtw89_mac_info
rs	core.h	/^	enum rtw89_rate_section rs;$/;"	m	struct:rtw89_rate_desc	typeref:enum:rtw89_rate_desc::rtw89_rate_section
rs	phy.h	/^	enum rtw89_rate_section rs;$/;"	m	struct:rtw89_txpwr_byrate_cfg	typeref:enum:rtw89_txpwr_byrate_cfg::rtw89_rate_section
rsp_fver	core.h	/^	u8 rsp_fver; \/* fver from fw *\/$/;"	m	struct:rtw89_btc_rpt_cmn_info
rssi	coex.c	/^	s8 rssi;$/;"	m	struct:btc_btinfo_hb0	file:
rssi	core.h	/^	s8 rssi[RF_PATH_MAX];$/;"	m	struct:rtw89_rx_phy_ppdu
rssi	core.h	/^	u32 rssi: 8;$/;"	m	struct:rtw89_btc_bt_link_info
rssi	core.h	/^	u8 rssi; \/* 0%~110% (dBm = rssi -110) *\/$/;"	m	struct:rtw89_btc_statistic
rssi_avg	core.h	/^	u8 rssi_avg;$/;"	m	struct:rtw89_rx_phy_ppdu
rssi_changed	phy.c	/^	bool rssi_changed;$/;"	m	struct:rtw89_phy_iter_rssi_data	file:
rssi_level	core.h	/^	u8 rssi_level;$/;"	m	struct:rtw89_btc_wl_info
rssi_map_all	coex.c	/^	u8 rssi_map_all;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	file:
rssi_max	core.h	/^	u8 rssi_max;$/;"	m	struct:rtw89_phy_ch_info
rssi_max_macid	core.h	/^	u16 rssi_max_macid;$/;"	m	struct:rtw89_phy_ch_info
rssi_min	core.h	/^	u8 rssi_min;$/;"	m	struct:rtw89_phy_ch_info
rssi_min_macid	core.h	/^	u16 rssi_min_macid;$/;"	m	struct:rtw89_phy_ch_info
rssi_nolink	phy.c	/^static const u8 rssi_nolink = 22;$/;"	v	file:
rssi_state	core.h	/^	u8 rssi_state[BTC_BT_RSSI_THMAX];$/;"	m	struct:rtw89_btc_bt_link_info
rssi_state	core.h	/^	u8 rssi_state[BTC_WL_RSSI_THMAX];$/;"	m	struct:rtw89_btc_wl_link_info
rssi_tol	core.h	/^	u8 rssi_tol;$/;"	m	struct:rtw89_chip_info
rsv_pgnum	mac.h	/^	u16 rsv_pgnum;$/;"	m	struct:rtw89_mac_dle_dfi_quota
rsvd	coex.c	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
rsvd	core.h	/^	__le16 rsvd;$/;"	m	struct:rtw89_btc_fbtc_mreg_val
rsvd	core.h	/^	__le16 rsvd;$/;"	m	struct:rtw89_btc_fbtc_slots
rsvd	core.h	/^	u16 rsvd;$/;"	m	struct:rtw89_btc_3rdcx_info
rsvd	core.h	/^	u16 rsvd;$/;"	m	struct:rtw89_btc_init_info
rsvd	core.h	/^	u32 rsvd: 12;$/;"	m	struct:rtw89_btc_ctrl
rsvd	core.h	/^	u32 rsvd: 14;$/;"	m	struct:rtw89_btc_wl_rfk_info
rsvd	core.h	/^	u32 rsvd: 19;$/;"	m	struct:rtw89_btc_bt_hid_desc
rsvd	core.h	/^	u32 rsvd: 19;$/;"	m	struct:rtw89_btc_bt_link_info
rsvd	core.h	/^	u32 rsvd: 22;$/;"	m	struct:rtw89_btc_bt_info
rsvd	core.h	/^	u32 rsvd: 29;$/;"	m	struct:rtw89_btc_bt_hfp_desc
rsvd	core.h	/^	u32 rsvd: 29;$/;"	m	struct:rtw89_btc_bt_pan_desc
rsvd	core.h	/^	u32 rsvd: 29;$/;"	m	struct:rtw89_btc_bt_rfk_info
rsvd	core.h	/^	u32 rsvd: 30;$/;"	m	struct:rtw89_btc_bt_scan_info
rsvd	core.h	/^	u32 rsvd: 3;$/;"	m	struct:rtw89_btc_dm
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_btafh
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_btdevinfo
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_btscan
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_btver
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_cynullsta
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_cysta
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_fbtc_steps
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_module
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_u8_sta_chg
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_wl_afh_info
rsvd	core.h	/^	u8 rsvd;$/;"	m	struct:rtw89_btc_wl_scan_info
rsvd	fw.h	/^	u16 rsvd:15;$/;"	m	struct:rtw89_h2creg_sch_tx_en
rsvd	fw.h	/^	u8 rsvd;$/;"	m	struct:rtw89_mfw_info
rsvd	fw.h	/^	u8 rsvd[14];$/;"	m	struct:rtw89_mfw_hdr
rsvd	pci.h	/^	__le16 rsvd;$/;"	m	struct:rtw89_pci_rx_bd_32
rsvd	rtw8852a.h	/^	u8 rsvd:3;$/;"	m	struct:rtw8852a_bb_pmac_info
rsvd	rtw8852a.h	/^	u8 rsvd[0x210];$/;"	m	struct:rtw8852a_efuse
rsvd	rtw8852a.h	/^	u8 rsvd[0x38];$/;"	m	struct:rtw8852au_efuse
rsvd	rtw8852a.h	/^	u8 rsvd[7];$/;"	m	struct:rtw8852a_tssi_offset
rsvd0	core.h	/^	u8 rsvd0;$/;"	m	struct:rtw89_btc_fbtc_tdma
rsvd1	core.h	/^	u8 rsvd1;$/;"	m	struct:rtw89_btc_fbtc_tdma
rsvd1	rtw8852a.h	/^	u8 rsvd1[10];$/;"	m	struct:rtw8852a_efuse
rsvd2	core.h	/^	__le16 rsvd2;$/;"	m	struct:rtw89_btc_fbtc_btafh
rsvd2	core.h	/^	__le16 rsvd2;$/;"	m	struct:rtw89_btc_fbtc_btscan
rsvd2	core.h	/^	__le16 rsvd2;$/;"	m	struct:rtw89_btc_fbtc_btver
rsvd2	core.h	/^	__le16 rsvd2;$/;"	m	struct:rtw89_btc_fbtc_cynullsta
rsvd2	core.h	/^	u16 rsvd2;$/;"	m	struct:rtw89_btc_fbtc_gpio_dbg
rsvd2	core.h	/^	u8 rsvd2:5;$/;"	m	struct:rtw89_ra_info
rsvd2	fw.h	/^	u8 rsvd2[4];$/;"	m	struct:rtw89_mfw_info
rsvd2	rtw8852a.h	/^	u8 rsvd2[94];$/;"	m	struct:rtw8852a_efuse
rsvd3	rtw8852a.h	/^	u8 rsvd3;$/;"	m	struct:rtw8852a_efuse
rsvd4	rtw8852a.h	/^	u8 rsvd4[5];$/;"	m	struct:rtw8852a_efuse
rsvd5	rtw8852a.h	/^	u8 rsvd5;$/;"	m	struct:rtw8852a_efuse
rsvd6	rtw8852a.h	/^	u8 rsvd6:2;$/;"	m	struct:rtw8852a_efuse
rsvd7	rtw8852a.h	/^	u8 rsvd7[3];$/;"	m	struct:rtw8852a_efuse
rsvd8	rtw8852a.h	/^	u8 rsvd8[46];$/;"	m	struct:rtw8852a_efuse
rsvd9	rtw8852a.h	/^	u8 rsvd9[0xf2];$/;"	m	struct:rtw8852a_efuse
rtw8852a_adc_en	rtw8852a.c	/^static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en)$/;"	f	file:
rtw8852a_backup_bb_regs	rtw8852a_rfk.c	/^static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};$/;"	v	file:
rtw8852a_backup_rf_regs	rtw8852a_rfk.c	/^static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};$/;"	v	file:
rtw8852a_bb_cal_txpwr_ref	rtw8852a.c	/^static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_bb_cfg_tx_path	rtw8852a.c	/^void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)$/;"	f
rtw8852a_bb_ctrl_btc_preagc	rtw8852a.c	/^static void rtw8852a_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)$/;"	f	file:
rtw8852a_bb_macid_ctrl_init	rtw8852a.c	/^static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_bb_pmac_info	rtw8852a.h	/^struct rtw8852a_bb_pmac_info {$/;"	s
rtw8852a_bb_reset	rtw8852a.c	/^static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_bb_reset_all	rtw8852a.c	/^static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_bb_reset_en	rtw8852a.c	/^static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_bb_set_plcp_tx	rtw8852a.c	/^void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_bb_set_pmac_pkt_tx	rtw8852a.c	/^void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,$/;"	f
rtw8852a_bb_set_pmac_tx	rtw8852a.c	/^void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev,$/;"	f
rtw8852a_bb_set_power	rtw8852a.c	/^void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,$/;"	f
rtw8852a_bb_sethw	rtw8852a.c	/^static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_bb_tx_mode_switch	rtw8852a.c	/^void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev,$/;"	f
rtw8852a_bbrst_for_rfk	rtw8852a.c	/^static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_btc_bt_aci_imp	rtw8852a.c	/^void rtw8852a_btc_bt_aci_imp(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_btc_get_bt_rssi	rtw8852a.c	/^s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)$/;"	f	file:
rtw8852a_btc_init_cfg	rtw8852a.c	/^static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_btc_preagc_dis_defs	rtw8852a.c	/^static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = {$/;"	v	typeref:struct:rtw89_reg3_def	file:
rtw8852a_btc_preagc_en_defs	rtw8852a.c	/^static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = {$/;"	v	typeref:struct:rtw89_reg3_def	file:
rtw8852a_btc_set_rfe	rtw8852a.c	/^static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_btc_set_wl_pri	rtw8852a.c	/^void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)$/;"	f	file:
rtw8852a_btc_set_wl_txpwr_ctrl	rtw8852a.c	/^rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)$/;"	f	file:
rtw8852a_btc_update_bt_cnt	rtw8852a.c	/^void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_btc_wl_s1_standby	rtw8852a.c	/^void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)$/;"	f	file:
rtw8852a_bw_setting	rtw8852a.c	/^static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)$/;"	f	file:
rtw8852a_ch_setting	rtw8852a.c	/^static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch,$/;"	f	file:
rtw8852a_chip_info	rtw8852a.c	/^EXPORT_SYMBOL(rtw8852a_chip_info);$/;"	v
rtw8852a_chip_info	rtw8852a.c	/^const struct rtw89_chip_info rtw8852a_chip_info = {$/;"	v	typeref:struct:rtw89_chip_info
rtw8852a_chip_ops	rtw8852a.c	/^static const struct rtw89_chip_ops rtw8852a_chip_ops = {$/;"	v	typeref:struct:rtw89_chip_ops	file:
rtw8852a_ctrl_btg	rtw8852a.c	/^static void rtw8852a_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)$/;"	f	file:
rtw8852a_ctrl_bw	rtw8852a.c	/^rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,$/;"	f	file:
rtw8852a_ctrl_ch	rtw8852a.c	/^static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch,$/;"	f	file:
rtw8852a_ctrl_sco_cck	rtw8852a.c	/^static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,$/;"	f	file:
rtw8852a_dack	rtw8852a_rfk.c	/^void rtw8852a_dack(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_dfs_en	rtw8852a.c	/^static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en)$/;"	f	file:
rtw8852a_dle_mem_pcie	rtw8852a.c	/^static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = {$/;"	v	typeref:struct:rtw89_dle_mem	file:
rtw8852a_dpk	rtw8852a_rfk.c	/^void rtw8852a_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)$/;"	f
rtw8852a_dpk_id	rtw8852a_rfk.c	/^enum rtw8852a_dpk_id {$/;"	g	file:
rtw8852a_dpk_track	rtw8852a_rfk.c	/^void rtw8852a_dpk_track(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_efuse	rtw8852a.h	/^struct rtw8852a_efuse {$/;"	s
rtw8852a_efuse_parsing_tssi	rtw8852a.c	/^static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_fem_setup	rtw8852a.c	/^static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_get_thermal	rtw8852a.c	/^static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)$/;"	f	file:
rtw8852a_hfc_chcfg_pcie	rtw8852a.c	/^static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = {$/;"	v	typeref:struct:rtw89_hfc_ch_cfg	file:
rtw8852a_hfc_param_ini_pcie	rtw8852a.c	/^static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = {$/;"	v	typeref:struct:rtw89_hfc_param_ini	file:
rtw8852a_hfc_pubcfg_pcie	rtw8852a.c	/^static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = {$/;"	v	typeref:struct:rtw89_hfc_pub_cfg	file:
rtw8852a_init_txpwr_unit	rtw8852a.c	/^rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)$/;"	f	file:
rtw8852a_iqk	rtw8852a_rfk.c	/^void rtw8852a_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)$/;"	f
rtw8852a_iqk_track	rtw8852a_rfk.c	/^void rtw8852a_iqk_track(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_iqk_type	rtw8852a_rfk.c	/^enum rtw8852a_iqk_type {$/;"	g	file:
rtw8852a_pa_bias_trim	rtw8852a.c	/^static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_phycap_parsing_pa_bias_trim	rtw8852a.c	/^static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_phycap_parsing_thermal_trim	rtw8852a.c	/^static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_phycap_parsing_tssi	rtw8852a.c	/^static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)$/;"	f	file:
rtw8852a_pmac_ht20_mcs7_tbl	rtw8852a.c	/^static const struct rtw89_reg2_def  rtw8852a_pmac_ht20_mcs7_tbl[] = {$/;"	v	typeref:struct:rtw89_reg2_def	file:
rtw8852a_pmac_mode	rtw8852a.h	/^enum rtw8852a_pmac_mode {$/;"	g
rtw8852a_power_trim	rtw8852a.c	/^static void rtw8852a_power_trim(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_pwroff	rtw8852a.c	/^static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = {$/;"	v	typeref:struct:rtw89_pwr_cfg	file:
rtw8852a_pwron	rtw8852a.c	/^static const struct rtw89_pwr_cfg rtw8852a_pwron[] = {$/;"	v	typeref:struct:rtw89_pwr_cfg	file:
rtw8852a_query_ppdu	rtw8852a.c	/^static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_rck	rtw8852a_rfk.c	/^void rtw8852a_rck(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_read_efuse	rtw8852a.c	/^static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)$/;"	f	file:
rtw8852a_read_phycap	rtw8852a.c	/^static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)$/;"	f	file:
rtw8852a_rfk_addck_reset_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_a);$/;"	v
rtw8852a_rfk_addck_reset_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_addck_reset_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_reset_defs_b);$/;"	v
rtw8852a_rfk_addck_reset_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_reset_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_addck_restore_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_a);$/;"	v
rtw8852a_rfk_addck_restore_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_addck_restore_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_restore_defs_b);$/;"	v
rtw8852a_rfk_addck_restore_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_restore_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_addck_trigger_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_a);$/;"	v
rtw8852a_rfk_addck_trigger_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_addck_trigger_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_addck_trigger_defs_b);$/;"	v
rtw8852a_rfk_addck_trigger_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_addck_trigger_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_afe_init_defs	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_afe_init_defs);$/;"	v
rtw8852a_rfk_afe_init_defs	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_afe_init_defs[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_band_changed	rtw8852a.c	/^static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_rfk_channel	rtw8852a.c	/^static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_rfk_check_addc_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_a);$/;"	v
rtw8852a_rfk_check_addc_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_check_addc_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_addc_defs_b);$/;"	v
rtw8852a_rfk_check_addc_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_addc_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_check_dadc_defs_f_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_a);$/;"	v
rtw8852a_rfk_check_dadc_defs_f_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_check_dadc_defs_f_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_f_b);$/;"	v
rtw8852a_rfk_check_dadc_defs_f_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_f_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_check_dadc_defs_r_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_a);$/;"	v
rtw8852a_rfk_check_dadc_defs_r_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_check_dadc_defs_r_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_check_dadc_defs_r_b);$/;"	v
rtw8852a_rfk_check_dadc_defs_r_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_check_dadc_defs_r_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_f_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_a);$/;"	v
rtw8852a_rfk_dack_defs_f_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_f_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_f_b);$/;"	v
rtw8852a_rfk_dack_defs_f_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_f_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_m_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_a);$/;"	v
rtw8852a_rfk_dack_defs_m_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_m_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_m_b);$/;"	v
rtw8852a_rfk_dack_defs_m_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_m_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_r_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_a);$/;"	v
rtw8852a_rfk_dack_defs_r_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_defs_r_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_defs_r_b);$/;"	v
rtw8852a_rfk_dack_defs_r_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_defs_r_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_reload_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_a);$/;"	v
rtw8852a_rfk_dack_reload_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dack_reload_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dack_reload_defs_b);$/;"	v
rtw8852a_rfk_dack_reload_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dack_reload_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_r_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_a);$/;"	v
rtw8852a_rfk_dpk_bb_afe_r_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_r_defs_ab	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_ab);$/;"	v
rtw8852a_rfk_dpk_bb_afe_r_defs_ab	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_ab[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_r_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_r_defs_b);$/;"	v
rtw8852a_rfk_dpk_bb_afe_r_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_r_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_s_defs_ab	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_s_defs_ab);$/;"	v
rtw8852a_rfk_dpk_bb_afe_s_defs_ab	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_s_defs_ab[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_sf_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_a);$/;"	v
rtw8852a_rfk_dpk_bb_afe_sf_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_sf_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sf_defs_b);$/;"	v
rtw8852a_rfk_dpk_bb_afe_sf_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sf_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_sr_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_a);$/;"	v
rtw8852a_rfk_dpk_bb_afe_sr_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_bb_afe_sr_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_bb_afe_sr_defs_b);$/;"	v
rtw8852a_rfk_dpk_bb_afe_sr_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_bb_afe_sr_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_lbk_rxiqk_defs_f	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_f);$/;"	v
rtw8852a_rfk_dpk_lbk_rxiqk_defs_f	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_f[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_lbk_rxiqk_defs_r	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_lbk_rxiqk_defs_r);$/;"	v
rtw8852a_rfk_dpk_lbk_rxiqk_defs_r	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_lbk_rxiqk_defs_r[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_dpk_pas_read_defs	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_dpk_pas_read_defs);$/;"	v
rtw8852a_rfk_dpk_pas_read_defs	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_dpk_pas_read_defs[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_init	rtw8852a.c	/^static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_rfk_iqk_restore_defs_dbcc_path0	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path0);$/;"	v
rtw8852a_rfk_iqk_restore_defs_dbcc_path0	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path0[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_iqk_restore_defs_dbcc_path1	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_dbcc_path1);$/;"	v
rtw8852a_rfk_iqk_restore_defs_dbcc_path1	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_dbcc_path1[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_iqk_restore_defs_nondbcc_path01	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_restore_defs_nondbcc_path01);$/;"	v
rtw8852a_rfk_iqk_restore_defs_nondbcc_path01	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_restore_defs_nondbcc_path01[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_iqk_set_defs_dbcc_path0	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path0);$/;"	v
rtw8852a_rfk_iqk_set_defs_dbcc_path0	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path0[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_iqk_set_defs_dbcc_path1	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_dbcc_path1);$/;"	v
rtw8852a_rfk_iqk_set_defs_dbcc_path1	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_dbcc_path1[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_iqk_set_defs_nondbcc_path01	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_rfk_iqk_set_defs_nondbcc_path01);$/;"	v
rtw8852a_rfk_iqk_set_defs_nondbcc_path01	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_rfk_iqk_set_defs_nondbcc_path01[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_rfk_scan	rtw8852a.c	/^static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start)$/;"	f	file:
rtw8852a_rfk_track	rtw8852a.c	/^static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_rx_dck	rtw8852a_rfk.c	/^void rtw8852a_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx,$/;"	f
rtw8852a_sco_barker_threshold	rtw8852a.c	/^static const u32 rtw8852a_sco_barker_threshold[14] = {$/;"	v	file:
rtw8852a_sco_cck_threshold	rtw8852a.c	/^static const u32 rtw8852a_sco_cck_threshold[14] = {$/;"	v	file:
rtw8852a_sco_mapping	rtw8852a.c	/^static u8 rtw8852a_sco_mapping(u8 central_ch)$/;"	f	file:
rtw8852a_set_channel	rtw8852a.c	/^static void rtw8852a_set_channel(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_channel_bb	rtw8852a.c	/^static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_channel_help	rtw8852a.c	/^static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter,$/;"	f	file:
rtw8852a_set_channel_mac	rtw8852a.c	/^static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_trx_mask	rtw8852a.c	/^void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)$/;"	f	file:
rtw8852a_set_txpwr	rtw8852a.c	/^static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_set_txpwr_byrate	rtw8852a.c	/^static void rtw8852a_set_txpwr_byrate(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_txpwr_ctrl	rtw8852a.c	/^static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_set_txpwr_limit	rtw8852a.c	/^static void rtw8852a_set_txpwr_limit(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_txpwr_limit_ru	rtw8852a.c	/^static void rtw8852a_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_txpwr_offset	rtw8852a.c	/^static void rtw8852a_set_txpwr_offset(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_txpwr_ref	rtw8852a.c	/^static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_set_txpwr_ul_tb_offset	rtw8852a.c	/^void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_spur_elimination	rtw8852a.c	/^static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch)$/;"	f	file:
rtw8852a_start_pmac_tx	rtw8852a.c	/^static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_stop_pmac_tx	rtw8852a.c	/^static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_thermal_trim	rtw8852a.c	/^static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw8852a_tssi	rtw8852a_rfk.c	/^void rtw8852a_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f
rtw8852a_tssi_cont_en	rtw8852a.c	/^static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,$/;"	f	file:
rtw8852a_tssi_cont_en_phyidx	rtw8852a.c	/^static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,$/;"	f	file:
rtw8852a_tssi_dac_gain_tbl_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_a);$/;"	v
rtw8852a_tssi_dac_gain_tbl_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_dac_gain_tbl_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_dac_gain_tbl_defs_b);$/;"	v
rtw8852a_tssi_dac_gain_tbl_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_dac_gain_tbl_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_dck_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_a);$/;"	v
rtw8852a_tssi_dck_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_dck_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_dck_defs_b);$/;"	v
rtw8852a_tssi_dck_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_dck_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_default_txagc	rtw8852a_rfk.c	/^static void rtw8852a_tssi_default_txagc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_tssi_disable_defs	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_disable_defs);$/;"	v
rtw8852a_tssi_disable_defs	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_disable_defs[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_enable_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_a);$/;"	v
rtw8852a_tssi_enable_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_enable_defs_ab	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_ab);$/;"	v
rtw8852a_tssi_enable_defs_ab	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_ab[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_enable_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_enable_defs_b);$/;"	v
rtw8852a_tssi_enable_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_enable_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_offset	rtw8852a.h	/^struct rtw8852a_tssi_offset {$/;"	s
rtw8852a_tssi_pak_defs_a_2g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_2g);$/;"	v
rtw8852a_tssi_pak_defs_a_2g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_2g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_a_5g_1	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_1);$/;"	v
rtw8852a_tssi_pak_defs_a_5g_1	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_1[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_a_5g_3	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_3);$/;"	v
rtw8852a_tssi_pak_defs_a_5g_3	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_3[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_a_5g_4	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_a_5g_4);$/;"	v
rtw8852a_tssi_pak_defs_a_5g_4	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_a_5g_4[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_b_2g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_2g);$/;"	v
rtw8852a_tssi_pak_defs_b_2g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_2g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_b_5g_1	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_1);$/;"	v
rtw8852a_tssi_pak_defs_b_5g_1	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_1[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_b_5g_3	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_3);$/;"	v
rtw8852a_tssi_pak_defs_b_5g_3	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_3[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_pak_defs_b_5g_4	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_pak_defs_b_5g_4);$/;"	v
rtw8852a_tssi_pak_defs_b_5g_4	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_pak_defs_b_5g_4[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_rf_gap_tbl_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_a);$/;"	v
rtw8852a_tssi_rf_gap_tbl_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_rf_gap_tbl_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_rf_gap_tbl_defs_b);$/;"	v
rtw8852a_tssi_rf_gap_tbl_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_rf_gap_tbl_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_scan	rtw8852a_rfk.c	/^void rtw8852a_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy)$/;"	f
rtw8852a_tssi_set_avg	rtw8852a_rfk.c	/^static void rtw8852a_tssi_set_avg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw8852a_tssi_slope_cal_org_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_a);$/;"	v
rtw8852a_tssi_slope_cal_org_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_slope_cal_org_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_slope_cal_org_defs_b);$/;"	v
rtw8852a_tssi_slope_cal_org_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_slope_cal_org_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_slope_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_a);$/;"	v
rtw8852a_tssi_slope_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_slope_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_slope_defs_b);$/;"	v
rtw8852a_tssi_slope_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_slope_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_sys_defs	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs);$/;"	v
rtw8852a_tssi_sys_defs	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_sys_defs_2g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_2g);$/;"	v
rtw8852a_tssi_sys_defs_2g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_2g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_sys_defs_5g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_sys_defs_5g);$/;"	v
rtw8852a_tssi_sys_defs_5g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_sys_defs_5g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_track	rtw8852a_rfk.c	/^void rtw8852a_tssi_track(struct rtw89_dev *rtwdev)$/;"	f
rtw8852a_tssi_track_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_a);$/;"	v
rtw8852a_tssi_track_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_track_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_track_defs_b);$/;"	v
rtw8852a_tssi_track_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_track_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_tracking_defs	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_tracking_defs);$/;"	v
rtw8852a_tssi_tracking_defs	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_tracking_defs[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txagc_ofst_mv_avg_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_a);$/;"	v
rtw8852a_tssi_txagc_ofst_mv_avg_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txagc_ofst_mv_avg_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txagc_ofst_mv_avg_defs_b);$/;"	v
rtw8852a_tssi_txagc_ofst_mv_avg_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txagc_ofst_mv_avg_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_defs_2g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_2g);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_defs_2g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_2g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_defs_5g	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_5g);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_defs_5g	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_5g[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_a);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_defs_b);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_a[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b	rtw8852a_rfk_table.c	/^DECLARE_RFK_TBL(rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b);$/;"	v
rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b	rtw8852a_rfk_table.c	/^static const struct rtw89_reg5_def rtw8852a_tssi_txpwr_ctrl_bb_he_tb_defs_b[] = {$/;"	v	typeref:struct:rtw89_reg5_def	file:
rtw8852a_wifi_scan_notify	rtw8852a_rfk.c	/^void rtw8852a_wifi_scan_notify(struct rtw89_dev *rtwdev,$/;"	f
rtw8852ae_efuse	rtw8852a.h	/^struct rtw8852ae_efuse {$/;"	s
rtw8852ae_efuse_parsing	rtw8852a.c	/^static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse,$/;"	f	file:
rtw8852au_efuse	rtw8852a.h	/^struct rtw8852au_efuse {$/;"	s
rtw89_8852a_byr_table	rtw8852a_table.c	/^const struct rtw89_txpwr_table rtw89_8852a_byr_table = {$/;"	v	typeref:struct:rtw89_txpwr_table
rtw89_8852a_lna_gain_a	rtw8852a_table.c	/^DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_a);$/;"	v
rtw89_8852a_lna_gain_a	rtw8852a_table.c	/^static const struct rtw89_reg_def rtw89_8852a_lna_gain_a[] = {$/;"	v	typeref:struct:rtw89_reg_def	file:
rtw89_8852a_lna_gain_g	rtw8852a_table.c	/^DECLARE_DIG_TABLE(rtw89_8852a_lna_gain_g);$/;"	v
rtw89_8852a_lna_gain_g	rtw8852a_table.c	/^static const struct rtw89_reg_def rtw89_8852a_lna_gain_g[] = {$/;"	v	typeref:struct:rtw89_reg_def	file:
rtw89_8852a_phy_bb_regs	rtw8852a_table.c	/^static const struct rtw89_reg2_def rtw89_8852a_phy_bb_regs[] = {$/;"	v	typeref:struct:rtw89_reg2_def	file:
rtw89_8852a_phy_bb_table	rtw8852a_table.c	/^const struct rtw89_phy_table rtw89_8852a_phy_bb_table = {$/;"	v	typeref:struct:rtw89_phy_table
rtw89_8852a_phy_dig_table	rtw8852a_table.c	/^const struct rtw89_phy_dig_gain_table rtw89_8852a_phy_dig_table = {$/;"	v	typeref:struct:rtw89_phy_dig_gain_table
rtw89_8852a_phy_nctl_regs	rtw8852a_table.c	/^static const struct rtw89_reg2_def rtw89_8852a_phy_nctl_regs[] = {$/;"	v	typeref:struct:rtw89_reg2_def	file:
rtw89_8852a_phy_nctl_table	rtw8852a_table.c	/^const struct rtw89_phy_table rtw89_8852a_phy_nctl_table = {$/;"	v	typeref:struct:rtw89_phy_table
rtw89_8852a_phy_radioa_regs	rtw8852a_table.c	/^static const struct rtw89_reg2_def rtw89_8852a_phy_radioa_regs[] = {$/;"	v	typeref:struct:rtw89_reg2_def	file:
rtw89_8852a_phy_radioa_table	rtw8852a_table.c	/^const struct rtw89_phy_table rtw89_8852a_phy_radioa_table = {$/;"	v	typeref:struct:rtw89_phy_table
rtw89_8852a_phy_radiob_regs	rtw8852a_table.c	/^static const struct rtw89_reg2_def rtw89_8852a_phy_radiob_regs[] = {$/;"	v	typeref:struct:rtw89_reg2_def	file:
rtw89_8852a_phy_radiob_table	rtw8852a_table.c	/^const struct rtw89_phy_table rtw89_8852a_phy_radiob_table = {$/;"	v	typeref:struct:rtw89_phy_table
rtw89_8852a_tia_gain_a	rtw8852a_table.c	/^DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_a);$/;"	v
rtw89_8852a_tia_gain_a	rtw8852a_table.c	/^static const struct rtw89_reg_def rtw89_8852a_tia_gain_a[] = {$/;"	v	typeref:struct:rtw89_reg_def	file:
rtw89_8852a_tia_gain_g	rtw8852a_table.c	/^DECLARE_DIG_TABLE(rtw89_8852a_tia_gain_g);$/;"	v
rtw89_8852a_tia_gain_g	rtw8852a_table.c	/^static const struct rtw89_reg_def rtw89_8852a_tia_gain_g[] = {$/;"	v	typeref:struct:rtw89_reg_def	file:
rtw89_8852a_trk_cfg	rtw8852a_table.c	/^const struct rtw89_txpwr_track_cfg rtw89_8852a_trk_cfg = {$/;"	v	typeref:struct:rtw89_txpwr_track_cfg
rtw89_8852a_txpwr_byrate	rtw8852a_table.c	/^static const struct rtw89_txpwr_byrate_cfg rtw89_8852a_txpwr_byrate[] = {$/;"	v	typeref:struct:rtw89_txpwr_byrate_cfg	file:
rtw89_8852a_txpwr_lmt_2g	rtw8852a_table.c	/^const s8 rtw89_8852a_txpwr_lmt_2g[RTW89_2G_BW_NUM][RTW89_NTX_NUM]$/;"	v
rtw89_8852a_txpwr_lmt_5g	rtw8852a_table.c	/^const s8 rtw89_8852a_txpwr_lmt_5g[RTW89_5G_BW_NUM][RTW89_NTX_NUM]$/;"	v
rtw89_8852a_txpwr_lmt_ru_2g	rtw8852a_table.c	/^const s8 rtw89_8852a_txpwr_lmt_ru_2g[RTW89_RU_NUM][RTW89_NTX_NUM]$/;"	v
rtw89_8852a_txpwr_lmt_ru_5g	rtw8852a_table.c	/^const s8 rtw89_8852a_txpwr_lmt_ru_5g[RTW89_RU_NUM][RTW89_NTX_NUM]$/;"	v
rtw89_add_cam_sec_mode	core.h	/^enum rtw89_add_cam_sec_mode {$/;"	g
rtw89_addr_cam_entry	core.h	/^struct rtw89_addr_cam_entry {$/;"	s
rtw89_agc_gaincode_set	core.h	/^struct rtw89_agc_gaincode_set {$/;"	s
rtw89_aifsn_to_aifs	mac80211.c	/^static u8 rtw89_aifsn_to_aifs(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_ampdu_params	core.h	/^struct rtw89_ampdu_params {$/;"	s
rtw89_apply_sar_common	sar.c	/^static int rtw89_apply_sar_common(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_band	core.h	/^enum rtw89_band {$/;"	g
rtw89_bandwidth	core.h	/^enum rtw89_bandwidth {$/;"	g
rtw89_bandwidth_section_num	core.h	/^enum rtw89_bandwidth_section_num {$/;"	g
rtw89_beamforming_type	core.h	/^enum rtw89_beamforming_type {$/;"	g
rtw89_bitrates	core.c	/^static struct ieee80211_rate rtw89_bitrates[] = {$/;"	v	typeref:struct:ieee80211_rate	file:
rtw89_bssid_cam_entry	core.h	/^struct rtw89_bssid_cam_entry {$/;"	s
rtw89_btc	core.h	/^struct rtw89_btc {$/;"	s
rtw89_btc_3rdcx_info	core.h	/^struct rtw89_btc_3rdcx_info {$/;"	s
rtw89_btc_8852a_bt_rssi_thres	rtw8852a.c	/^u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28};$/;"	v	file:
rtw89_btc_8852a_mon_reg	rtw8852a.c	/^static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = {$/;"	v	typeref:struct:rtw89_btc_fbtc_mreg	file:
rtw89_btc_8852a_rf_dl	rtw8852a.c	/^static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = {$/;"	v	typeref:struct:rtw89_btc_rf_trx_para	file:
rtw89_btc_8852a_rf_ul	rtw8852a.c	/^static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = {$/;"	v	typeref:struct:rtw89_btc_rf_trx_para	file:
rtw89_btc_8852a_wl_rssi_thres	rtw8852a.c	/^u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30};$/;"	v	file:
rtw89_btc_ant_info	core.h	/^struct rtw89_btc_ant_info {$/;"	s
rtw89_btc_bool_sta_chg	core.h	/^struct rtw89_btc_bool_sta_chg {$/;"	s
rtw89_btc_bt_a2dp_desc	core.h	/^struct rtw89_btc_bt_a2dp_desc {$/;"	s
rtw89_btc_bt_hfp_desc	core.h	/^struct rtw89_btc_bt_hfp_desc {$/;"	s
rtw89_btc_bt_hid_desc	core.h	/^struct rtw89_btc_bt_hid_desc {$/;"	s
rtw89_btc_bt_info	core.h	/^struct rtw89_btc_bt_info {$/;"	s
rtw89_btc_bt_link_info	core.h	/^struct rtw89_btc_bt_link_info {$/;"	s
rtw89_btc_bt_pan_desc	core.h	/^struct rtw89_btc_bt_pan_desc {$/;"	s
rtw89_btc_bt_profile	core.h	/^enum rtw89_btc_bt_profile {$/;"	g
rtw89_btc_bt_rfk_counter	core.h	/^enum rtw89_btc_bt_rfk_counter {$/;"	g
rtw89_btc_bt_rfk_info	core.h	/^struct rtw89_btc_bt_rfk_info {$/;"	s
rtw89_btc_bt_rfk_info_map	core.h	/^union rtw89_btc_bt_rfk_info_map {$/;"	u
rtw89_btc_bt_scan_info	core.h	/^struct rtw89_btc_bt_scan_info {$/;"	s
rtw89_btc_bt_scan_type	core.h	/^enum rtw89_btc_bt_scan_type {$/;"	g
rtw89_btc_bt_smap	core.h	/^struct rtw89_btc_bt_smap {$/;"	s
rtw89_btc_bt_state_cnt	core.h	/^enum rtw89_btc_bt_state_cnt {$/;"	g
rtw89_btc_bt_state_map	core.h	/^union rtw89_btc_bt_state_map {$/;"	u
rtw89_btc_bt_ver_info	core.h	/^struct rtw89_btc_bt_ver_info {$/;"	s
rtw89_btc_btf_fw_event	core.h	/^enum rtw89_btc_btf_fw_event {$/;"	g
rtw89_btc_btf_fwinfo	core.h	/^struct rtw89_btc_btf_fwinfo {$/;"	s
rtw89_btc_btf_h2c_class	fw.h	/^enum rtw89_btc_btf_h2c_class {$/;"	g
rtw89_btc_btf_set	fw.h	/^enum rtw89_btc_btf_set {$/;"	g
rtw89_btc_btf_set_mon_reg	coex.c	/^struct rtw89_btc_btf_set_mon_reg {$/;"	s	file:
rtw89_btc_btf_set_report	coex.c	/^struct rtw89_btc_btf_set_report {$/;"	s	file:
rtw89_btc_btf_set_slot_table	coex.c	/^struct rtw89_btc_btf_set_slot_table {$/;"	s	file:
rtw89_btc_btf_tlv	coex.c	/^struct rtw89_btc_btf_tlv {$/;"	s	file:
rtw89_btc_btfre_type	core.h	/^enum rtw89_btc_btfre_type {$/;"	g
rtw89_btc_btinfo	core.h	/^enum rtw89_btc_btinfo {$/;"	g
rtw89_btc_c2h_handle	coex.c	/^void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,$/;"	f
rtw89_btc_ctrl	core.h	/^struct rtw89_btc_ctrl {$/;"	s
rtw89_btc_cx	core.h	/^struct rtw89_btc_cx {$/;"	s
rtw89_btc_cxdrvinfo	fw.h	/^enum rtw89_btc_cxdrvinfo {$/;"	g
rtw89_btc_cxst_state	core.h	/^enum rtw89_btc_cxst_state {$/;"	g
rtw89_btc_dbg	core.h	/^struct rtw89_btc_dbg {$/;"	s
rtw89_btc_dcnt	core.h	/^enum rtw89_btc_dcnt {$/;"	g
rtw89_btc_dm	core.h	/^struct rtw89_btc_dm {$/;"	s
rtw89_btc_dm_emap	core.h	/^struct rtw89_btc_dm_emap {$/;"	s
rtw89_btc_dm_error_map	core.h	/^union rtw89_btc_dm_error_map {$/;"	u
rtw89_btc_dm_step	core.h	/^struct rtw89_btc_dm_step {$/;"	s
rtw89_btc_dump_info	coex.c	/^void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m)$/;"	f
rtw89_btc_fbtc_btafh	core.h	/^struct rtw89_btc_fbtc_btafh {$/;"	s
rtw89_btc_fbtc_btdevinfo	core.h	/^struct rtw89_btc_fbtc_btdevinfo {$/;"	s
rtw89_btc_fbtc_btscan	core.h	/^struct rtw89_btc_fbtc_btscan {$/;"	s
rtw89_btc_fbtc_btver	core.h	/^struct rtw89_btc_fbtc_btver {$/;"	s
rtw89_btc_fbtc_cynullsta	core.h	/^struct rtw89_btc_fbtc_cynullsta { \/* cycle null statistics *\/$/;"	s
rtw89_btc_fbtc_cysta	core.h	/^struct rtw89_btc_fbtc_cysta { \/* statistics for cycles *\/$/;"	s
rtw89_btc_fbtc_cysta_cpu	coex.c	/^struct rtw89_btc_fbtc_cysta_cpu {$/;"	s	file:
rtw89_btc_fbtc_cysta_to_cpu	coex.c	/^static void rtw89_btc_fbtc_cysta_to_cpu(const struct rtw89_btc_fbtc_cysta *src,$/;"	f	file:
rtw89_btc_fbtc_gpio_dbg	core.h	/^struct rtw89_btc_fbtc_gpio_dbg {$/;"	s
rtw89_btc_fbtc_mreg	core.h	/^struct rtw89_btc_fbtc_mreg {$/;"	s
rtw89_btc_fbtc_mreg_val	core.h	/^struct rtw89_btc_fbtc_mreg_val {$/;"	s
rtw89_btc_fbtc_rpt_ctrl	core.h	/^struct rtw89_btc_fbtc_rpt_ctrl {$/;"	s
rtw89_btc_fbtc_rxflct	core.h	/^union rtw89_btc_fbtc_rxflct {$/;"	u
rtw89_btc_fbtc_slot	core.h	/^struct rtw89_btc_fbtc_slot {$/;"	s
rtw89_btc_fbtc_slots	core.h	/^struct rtw89_btc_fbtc_slots {$/;"	s
rtw89_btc_fbtc_step	core.h	/^struct rtw89_btc_fbtc_step {$/;"	s
rtw89_btc_fbtc_steps	core.h	/^struct rtw89_btc_fbtc_steps {$/;"	s
rtw89_btc_fbtc_tdma	core.h	/^struct rtw89_btc_fbtc_tdma {$/;"	s
rtw89_btc_fw_en_rpt	coex.c	/^static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_btc_fw_set_slots	coex.c	/^static void rtw89_btc_fw_set_slots(struct rtw89_dev *rtwdev, u8 num,$/;"	f	file:
rtw89_btc_init_info	core.h	/^struct rtw89_btc_init_info {$/;"	s
rtw89_btc_module	core.h	/^struct rtw89_btc_module {$/;"	s
rtw89_btc_ncnt	core.h	/^enum rtw89_btc_ncnt {$/;"	g
rtw89_btc_ntfy_arp_packet_work	coex.c	/^void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work)$/;"	f
rtw89_btc_ntfy_dhcp_packet_work	coex.c	/^void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work)$/;"	f
rtw89_btc_ntfy_eapol_packet_work	coex.c	/^void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work)$/;"	f
rtw89_btc_ntfy_icmp_packet_work	coex.c	/^void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work)$/;"	f
rtw89_btc_ntfy_init	coex.c	/^void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode)$/;"	f
rtw89_btc_ntfy_poweroff	coex.c	/^void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev)$/;"	f
rtw89_btc_ntfy_poweron	coex.c	/^void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev)$/;"	f
rtw89_btc_ntfy_radio_state	coex.c	/^void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state)$/;"	f
rtw89_btc_ntfy_role_info	coex.c	/^void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_btc_ntfy_scan_finish	coex.c	/^void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx)$/;"	f
rtw89_btc_ntfy_scan_start	coex.c	/^void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band)$/;"	f
rtw89_btc_ntfy_specific_packet	coex.c	/^void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev,$/;"	f
rtw89_btc_ntfy_switch_band	coex.c	/^void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band)$/;"	f
rtw89_btc_ntfy_wl_rfk	coex.c	/^void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map,$/;"	f
rtw89_btc_ntfy_wl_sta	coex.c	/^void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev)$/;"	f
rtw89_btc_ntfy_wl_sta_iter	coex.c	/^static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_btc_path_phymap	coex.h	/^static inline u8 rtw89_btc_path_phymap(struct rtw89_dev *rtwdev,$/;"	f
rtw89_btc_phymap	coex.h	/^static inline u8 rtw89_btc_phymap(struct rtw89_dev *rtwdev,$/;"	f
rtw89_btc_prpt	coex.c	/^struct rtw89_btc_prpt {$/;"	s	file:
rtw89_btc_report_ctrl_state	core.h	/^struct rtw89_btc_report_ctrl_state {$/;"	s
rtw89_btc_rf_para	core.h	/^struct rtw89_btc_rf_para {$/;"	s
rtw89_btc_rf_trx_para	core.h	/^struct rtw89_btc_rf_trx_para {$/;"	s
rtw89_btc_rpt_cmn_info	core.h	/^struct rtw89_btc_rpt_cmn_info {$/;"	s
rtw89_btc_rpt_fbtc_btafh	core.h	/^struct rtw89_btc_rpt_fbtc_btafh {$/;"	s
rtw89_btc_rpt_fbtc_btdev	core.h	/^struct rtw89_btc_rpt_fbtc_btdev {$/;"	s
rtw89_btc_rpt_fbtc_btscan	core.h	/^struct rtw89_btc_rpt_fbtc_btscan {$/;"	s
rtw89_btc_rpt_fbtc_btver	core.h	/^struct rtw89_btc_rpt_fbtc_btver {$/;"	s
rtw89_btc_rpt_fbtc_cysta	core.h	/^struct rtw89_btc_rpt_fbtc_cysta {$/;"	s
rtw89_btc_rpt_fbtc_gpio_dbg	core.h	/^struct rtw89_btc_rpt_fbtc_gpio_dbg {$/;"	s
rtw89_btc_rpt_fbtc_mreg	core.h	/^struct rtw89_btc_rpt_fbtc_mreg {$/;"	s
rtw89_btc_rpt_fbtc_nullsta	core.h	/^struct rtw89_btc_rpt_fbtc_nullsta {$/;"	s
rtw89_btc_rpt_fbtc_slots	core.h	/^struct rtw89_btc_rpt_fbtc_slots {$/;"	s
rtw89_btc_rpt_fbtc_step	core.h	/^struct rtw89_btc_rpt_fbtc_step {$/;"	s
rtw89_btc_rpt_fbtc_tdma	core.h	/^struct rtw89_btc_rpt_fbtc_tdma {$/;"	s
rtw89_btc_statistic	core.h	/^struct rtw89_btc_statistic {$/;"	s
rtw89_btc_u8_sta_chg	core.h	/^struct rtw89_btc_u8_sta_chg {$/;"	s
rtw89_btc_wl_active_role	core.h	/^struct rtw89_btc_wl_active_role {$/;"	s
rtw89_btc_wl_afh_info	core.h	/^struct rtw89_btc_wl_afh_info {$/;"	s
rtw89_btc_wl_dbcc_info	core.h	/^struct rtw89_btc_wl_dbcc_info {$/;"	s
rtw89_btc_wl_info	core.h	/^struct rtw89_btc_wl_info {$/;"	s
rtw89_btc_wl_link_info	core.h	/^struct rtw89_btc_wl_link_info {$/;"	s
rtw89_btc_wl_rfk_info	core.h	/^struct rtw89_btc_wl_rfk_info {$/;"	s
rtw89_btc_wl_role_info	core.h	/^struct rtw89_btc_wl_role_info { \/* struct size must be n*4 bytes *\/$/;"	s
rtw89_btc_wl_role_info_bpos	core.h	/^struct rtw89_btc_wl_role_info_bpos {$/;"	s
rtw89_btc_wl_role_info_map	core.h	/^union rtw89_btc_wl_role_info_map {$/;"	u
rtw89_btc_wl_scan_info	core.h	/^struct rtw89_btc_wl_scan_info {$/;"	s
rtw89_btc_wl_smap	core.h	/^struct rtw89_btc_wl_smap {$/;"	s
rtw89_btc_wl_sta_iter_data	coex.c	/^struct rtw89_btc_wl_sta_iter_data {$/;"	s	file:
rtw89_btc_wl_state_cnt	core.h	/^enum rtw89_btc_wl_state_cnt {$/;"	g
rtw89_btc_wl_state_map	core.h	/^union rtw89_btc_wl_state_map {$/;"	u
rtw89_btc_wl_tx_limit_para	core.h	/^struct rtw89_btc_wl_tx_limit_para {$/;"	s
rtw89_btc_wl_ver_info	core.h	/^struct rtw89_btc_wl_ver_info {$/;"	s
rtw89_build_txwd_body0	core.c	/^static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_body2	core.c	/^static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_body3	core.c	/^static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_info0	core.c	/^static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_info1	core.c	/^static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_info2	core.c	/^static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_build_txwd_info4	core.c	/^static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)$/;"	f	file:
rtw89_c2h_phy_cap	fw.h	/^struct rtw89_c2h_phy_cap {$/;"	s
rtw89_cam_addr_hash	cam.c	/^static u8 rtw89_cam_addr_hash(u8 start, u8 *addr)$/;"	f	file:
rtw89_cam_attach_sec_cam	cam.c	/^static int rtw89_cam_attach_sec_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_bssid_changed	cam.c	/^void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_cam_deinit	cam.c	/^void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_cam_fill_addr_cam_info	cam.c	/^void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev,$/;"	f
rtw89_cam_fill_bssid_cam_info	cam.c	/^int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev,$/;"	f
rtw89_cam_get_addr_cam_key_idx	cam.c	/^static int rtw89_cam_get_addr_cam_key_idx(struct rtw89_addr_cam_entry *addr_cam,$/;"	f	file:
rtw89_cam_get_avail_addr_cam	cam.c	/^static int rtw89_cam_get_avail_addr_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_get_avail_bssid_cam	cam.c	/^static int rtw89_cam_get_avail_bssid_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_get_avail_sec_cam	cam.c	/^static int rtw89_cam_get_avail_sec_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_get_sec_key_cmd	cam.c	/^rtw89_cam_get_sec_key_cmd(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_info	core.h	/^struct rtw89_cam_info {$/;"	s
rtw89_cam_init	cam.c	/^int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_cam_init_addr_cam	cam.c	/^static int rtw89_cam_init_addr_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_init_bssid_cam	cam.c	/^static int rtw89_cam_init_bssid_cam(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_reset_key_iter	cam.c	/^static void rtw89_cam_reset_key_iter(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_cam_reset_keys	cam.c	/^void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev)$/;"	f
rtw89_cam_sec_key_add	cam.c	/^int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev,$/;"	f
rtw89_cam_sec_key_del	cam.c	/^int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev,$/;"	f
rtw89_cam_sec_key_install	cam.c	/^static int rtw89_cam_sec_key_install(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cam_send_sec_key_cmd	cam.c	/^static int rtw89_cam_send_sec_key_cmd(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_ccx_edcca_opt_bw_idx	core.h	/^enum rtw89_ccx_edcca_opt_bw_idx {$/;"	g
rtw89_ccx_edcca_opt_sc_idx	core.h	/^enum rtw89_ccx_edcca_opt_sc_idx {$/;"	g
rtw89_ccx_para_info	core.h	/^struct rtw89_ccx_para_info {$/;"	s
rtw89_ccx_unit	phy.h	/^enum rtw89_ccx_unit {$/;"	g
rtw89_cfo_tracking_info	core.h	/^struct rtw89_cfo_tracking_info {$/;"	s
rtw89_channel_help_params	core.h	/^struct rtw89_channel_help_params {$/;"	s
rtw89_channel_params	core.h	/^struct rtw89_channel_params {$/;"	s
rtw89_channel_to_idx	phy.c	/^static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 channel)$/;"	f	file:
rtw89_channels_2ghz	core.c	/^static struct ieee80211_channel rtw89_channels_2ghz[] = {$/;"	v	typeref:struct:ieee80211_channel	file:
rtw89_channels_5ghz	core.c	/^static struct ieee80211_channel rtw89_channels_5ghz[] = {$/;"	v	typeref:struct:ieee80211_channel	file:
rtw89_check_and_reclaim_tx_resource	core.c	/^static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)$/;"	f	file:
rtw89_chip_bb_ctrl_btc_preagc	core.h	/^static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_bb_sethw	core.h	/^static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_board_info_setup	core.c	/^static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_chip_cfg_txpwr_ul_tb_offset	core.h	/^void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_efuse_info_setup	core.c	/^static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_chip_fem_setup	core.h	/^static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_get_thermal	core.h	/^static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_info	core.h	/^struct rtw89_chip_info {$/;"	s
rtw89_chip_info_setup	core.c	/^EXPORT_SYMBOL(rtw89_chip_info_setup);$/;"	v
rtw89_chip_info_setup	core.c	/^int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_init_txpwr_unit	core.h	/^static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_ops	core.h	/^struct rtw89_chip_ops {$/;"	s
rtw89_chip_power_trim	core.h	/^static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_query_ppdu	core.h	/^static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_rfk_band_changed	core.h	/^static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_rfk_channel	core.h	/^static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_rfk_init	core.h	/^static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_rfk_scan	core.h	/^static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)$/;"	f
rtw89_chip_rfk_track	core.h	/^static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_set_channel_done	core.h	/^void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_set_channel_prepare	core.h	/^void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,$/;"	f
rtw89_chip_set_txpwr	core.h	/^static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev)$/;"	f
rtw89_chip_set_txpwr_ctrl	core.h	/^static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)$/;"	f
rtw89_coex_act1_work	coex.c	/^void rtw89_coex_act1_work(struct work_struct *work)$/;"	f
rtw89_coex_bt_devinfo_work	coex.c	/^void rtw89_coex_bt_devinfo_work(struct work_struct *work)$/;"	f
rtw89_coex_rfk_chk_work	coex.c	/^void rtw89_coex_rfk_chk_work(struct work_struct *work)$/;"	f
rtw89_common_sar_freq_ranges	sar.c	/^static const struct cfg80211_sar_freq_ranges rtw89_common_sar_freq_ranges[] = {$/;"	v	typeref:struct:cfg80211_sar_freq_ranges	file:
rtw89_common_sar_subband_map	sar.c	/^static const u8 rtw89_common_sar_subband_map[] = {$/;"	v	file:
rtw89_conf_tx	mac80211.c	/^static void rtw89_conf_tx(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_acquire_bit_map	core.c	/^u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)$/;"	f
rtw89_core_ba_work	core.c	/^static void rtw89_core_ba_work(struct work_struct *work)$/;"	f	file:
rtw89_core_chip_id	core.h	/^enum rtw89_core_chip_id {$/;"	g
rtw89_core_clr_supported_band	core.c	/^static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_core_deinit	core.c	/^EXPORT_SYMBOL(rtw89_core_deinit);$/;"	v
rtw89_core_deinit	core.c	/^void rtw89_core_deinit(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_fill_txdesc	core.c	/^EXPORT_SYMBOL(rtw89_core_fill_txdesc);$/;"	v
rtw89_core_fill_txdesc	core.c	/^void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_flush_ppdu_rx_queue	core.c	/^static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_free_sta_pending_ba	core.c	/^static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_get_ch_dma	txrx.h	/^static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)$/;"	f
rtw89_core_get_mgmt_rate	core.c	/^static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_get_no_ul_ofdma_htc	core.c	/^static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc)$/;"	f	file:
rtw89_core_get_phy_status_ie_len	core.c	/^static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr)$/;"	f	file:
rtw89_core_get_qsel	txrx.h	/^static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid)$/;"	f
rtw89_core_get_tid_indicate	txrx.h	/^static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid)$/;"	f
rtw89_core_get_tx_type	core.c	/^rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_init	core.c	/^EXPORT_SYMBOL(rtw89_core_init);$/;"	v
rtw89_core_init	core.c	/^int rtw89_core_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_iter_rx_status	core.c	/^struct rtw89_core_iter_rx_status {$/;"	s	file:
rtw89_core_napi_deinit	core.c	/^EXPORT_SYMBOL(rtw89_core_napi_deinit);$/;"	v
rtw89_core_napi_deinit	core.c	/^void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_napi_init	core.c	/^EXPORT_SYMBOL(rtw89_core_napi_init);$/;"	v
rtw89_core_napi_init	core.c	/^void rtw89_core_napi_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_napi_start	core.c	/^EXPORT_SYMBOL(rtw89_core_napi_start);$/;"	v
rtw89_core_napi_start	core.c	/^void rtw89_core_napi_start(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_napi_stop	core.c	/^EXPORT_SYMBOL(rtw89_core_napi_stop);$/;"	v
rtw89_core_napi_stop	core.c	/^void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_parse_phy_status_ie01	core.c	/^static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr,$/;"	f	file:
rtw89_core_ppdu_sts_init	core.c	/^static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_core_process_phy_status_ie	core.c	/^static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr,$/;"	f	file:
rtw89_core_query_rxdesc	core.c	/^EXPORT_SYMBOL(rtw89_core_query_rxdesc);$/;"	v
rtw89_core_query_rxdesc	core.c	/^void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_register	core.c	/^EXPORT_SYMBOL(rtw89_core_register);$/;"	v
rtw89_core_register	core.c	/^int rtw89_core_register(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_register_hw	core.c	/^static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_core_release_all_bits_map	core.c	/^void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)$/;"	f
rtw89_core_release_bit_map	core.c	/^void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)$/;"	f
rtw89_core_rx	core.c	/^EXPORT_SYMBOL(rtw89_core_rx);$/;"	v
rtw89_core_rx	core.c	/^void rtw89_core_rx(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_rx_parse_phy_sts	core.c	/^static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_pending_skb	core.c	/^static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_ppdu_match	core.c	/^static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_process_mac_ppdu	core.c	/^static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_process_phy_ppdu	core.c	/^static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_process_phy_ppdu_iter	core.c	/^static void rtw89_core_rx_process_phy_ppdu_iter(void *data,$/;"	f	file:
rtw89_core_rx_process_phy_sts	core.c	/^static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_process_ppdu_sts	core.c	/^static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_process_report	core.c	/^static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_stats	core.c	/^static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_rx_type	core.h	/^enum rtw89_core_rx_type {$/;"	g
rtw89_core_set_supported_band	core.c	/^static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_core_sta_add	core.c	/^int rtw89_core_sta_add(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_sta_assoc	core.c	/^int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_sta_disassoc	core.c	/^int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_sta_disconnect	core.c	/^int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_sta_remove	core.c	/^int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_start	core.c	/^int rtw89_core_start(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_stats_sta_rx_status	core.c	/^static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_stats_sta_rx_status_iter	core.c	/^void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_core_stop	core.c	/^void rtw89_core_stop(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_tx_btc_spec_pkt_notify	core.c	/^rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_kick_off	core.c	/^void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)$/;"	f
rtw89_core_tx_request	core.h	/^struct rtw89_core_tx_request {$/;"	s
rtw89_core_tx_type	core.h	/^enum rtw89_core_tx_type {$/;"	g
rtw89_core_tx_update_ampdu_info	core.c	/^rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_data_info	core.c	/^rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_desc_info	core.c	/^rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_h2c_info	core.c	/^rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_he_qos_htc	core.c	/^rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_mgmt_info	core.c	/^rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_update_sec_key	core.c	/^rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_tx_write	core.c	/^int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,$/;"	f
rtw89_core_txq_agg_wait	core.c	/^static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_txq_check_agg	core.c	/^static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_txq_init	core.h	/^static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,$/;"	f
rtw89_core_txq_push	core.c	/^static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_core_txq_reinvoke_work	core.c	/^static void rtw89_core_txq_reinvoke_work(struct work_struct *w)$/;"	f	file:
rtw89_core_txq_schedule	core.c	/^static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)$/;"	f	file:
rtw89_core_txq_work	core.c	/^static void rtw89_core_txq_work(struct work_struct *w)$/;"	f	file:
rtw89_core_unregister	core.c	/^EXPORT_SYMBOL(rtw89_core_unregister);$/;"	v
rtw89_core_unregister	core.c	/^void rtw89_core_unregister(struct rtw89_dev *rtwdev)$/;"	f
rtw89_core_unregister_hw	core.c	/^static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_core_update_phy_ppdu	core.c	/^static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)$/;"	f	file:
rtw89_core_update_rx_status	core.c	/^static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_cpuio_ctrl	mac.h	/^struct rtw89_cpuio_ctrl {$/;"	s
rtw89_ctrl_btg	core.h	/^static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)$/;"	f
rtw89_cv	core.h	/^enum rtw89_cv {$/;"	g
rtw89_dack_info	core.h	/^struct rtw89_dack_info {$/;"	s
rtw89_dbi_read8	pci.c	/^static int rtw89_dbi_read8(struct rtw89_dev *rtwdev, u16 addr, u8 *value)$/;"	f	file:
rtw89_dbi_write8	pci.c	/^static int rtw89_dbi_write8(struct rtw89_dev *rtwdev, u16 addr, u8 data)$/;"	f	file:
rtw89_dbi_write8_clr	pci.c	/^static int rtw89_dbi_write8_clr(struct rtw89_dev *rtwdev, u16 addr, u8 bit)$/;"	f	file:
rtw89_dbi_write8_set	pci.c	/^static int rtw89_dbi_write8_set(struct rtw89_dev *rtwdev, u16 addr, u8 bit)$/;"	f	file:
rtw89_dcfo_comp	phy.c	/^static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)$/;"	f	file:
rtw89_dcfo_comp_init	phy.c	/^static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_debug	debug.h	/^static inline void rtw89_debug(struct rtw89_dev *rtwdev,$/;"	f
rtw89_debug	debug.h	51;"	d
rtw89_debug_append_rx_rate	debug.c	/^rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,$/;"	f	file:
rtw89_debug_dump_mac_mem	debug.c	/^static void rtw89_debug_dump_mac_mem(struct seq_file *m,$/;"	f	file:
rtw89_debug_fw_log_btc_manual_set	debug.c	/^static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp,$/;"	f	file:
rtw89_debug_mac_dbg_port_dump	debug.c	/^static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_dbg_port_sel	debug.c	/^rtw89_debug_mac_dbg_port_sel(struct seq_file *m,$/;"	f	file:
rtw89_debug_mac_dump_cmac_dbg	debug.c	/^static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_dump_dbg_port	debug.c	/^static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_dump_dle_dbg	debug.c	/^static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_dump_dmac_dbg	debug.c	/^static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_dump_ss_dbg	debug.c	/^static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_debug_mac_reg_sel	debug.h	/^enum rtw89_debug_mac_reg_sel {$/;"	g
rtw89_debug_mask	debug.c	/^EXPORT_SYMBOL(rtw89_debug_mask);$/;"	v
rtw89_debug_mask	debug.c	/^unsigned int rtw89_debug_mask;$/;"	v
rtw89_debug_mask	debug.h	/^enum rtw89_debug_mask {$/;"	g
rtw89_debug_priv_btc_info	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_btc_info_get	debug.c	/^static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_btc_manual	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_btc_manual_set	debug.c	/^static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,$/;"	f	file:
rtw89_debug_priv_early_h2c	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_early_h2c_get	debug.c	/^rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_early_h2c_set	debug.c	/^rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,$/;"	f	file:
rtw89_debug_priv_fw_log_manual	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_mac_dbg_port_dump	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_mac_dbg_port_dump_get	debug.c	/^rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_mac_dbg_port_dump_select	debug.c	/^rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,$/;"	f	file:
rtw89_debug_priv_mac_mem_dump	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_mac_mem_dump_get	debug.c	/^rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_mac_mem_dump_select	debug.c	/^rtw89_debug_priv_mac_mem_dump_select(struct file *filp,$/;"	f	file:
rtw89_debug_priv_mac_reg_dump	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_mac_reg_dump_get	debug.c	/^static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_mac_reg_dump_select	debug.c	/^rtw89_debug_priv_mac_reg_dump_select(struct file *filp,$/;"	f	file:
rtw89_debug_priv_phy_info	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_phy_info_get	debug.c	/^static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_read_reg	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_read_reg_get	debug.c	/^static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_read_reg_select	debug.c	/^rtw89_debug_priv_read_reg_select(struct file *filp,$/;"	f	file:
rtw89_debug_priv_read_rf	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_read_rf_get	debug.c	/^static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_read_rf_select	debug.c	/^rtw89_debug_priv_read_rf_select(struct file *filp,$/;"	f	file:
rtw89_debug_priv_rf_reg_dump	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_rf_reg_dump_get	debug.c	/^static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_send_h2c	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_send_h2c_set	debug.c	/^static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,$/;"	f	file:
rtw89_debug_priv_txpwr_table	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_txpwr_table_get	debug.c	/^static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debug_priv_write_reg	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_write_reg_set	debug.c	/^static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,$/;"	f	file:
rtw89_debug_priv_write_rf	debug.c	/^static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = {$/;"	v	typeref:struct:rtw89_debugfs_priv	file:
rtw89_debug_priv_write_rf_set	debug.c	/^static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,$/;"	f	file:
rtw89_debugfs_add	debug.c	2428;"	d	file:
rtw89_debugfs_add_r	debug.c	2441;"	d	file:
rtw89_debugfs_add_rw	debug.c	2439;"	d	file:
rtw89_debugfs_add_w	debug.c	2437;"	d	file:
rtw89_debugfs_close	debug.c	/^static int rtw89_debugfs_close(struct inode *inode, struct file *filp)$/;"	f	file:
rtw89_debugfs_init	debug.c	/^void rtw89_debugfs_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_debugfs_init	debug.h	/^static inline void rtw89_debugfs_init(struct rtw89_dev *rtwdev) {}$/;"	f
rtw89_debugfs_priv	debug.c	/^struct rtw89_debugfs_priv {$/;"	s	file:
rtw89_debugfs_seq_file_write	debug.c	/^static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,$/;"	f	file:
rtw89_debugfs_single_open	debug.c	/^static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)$/;"	f	file:
rtw89_debugfs_single_show	debug.c	/^static int rtw89_debugfs_single_show(struct seq_file *m, void *v)$/;"	f	file:
rtw89_debugfs_single_write	debug.c	/^static ssize_t rtw89_debugfs_single_write(struct file *filp,$/;"	f	file:
rtw89_dev	core.h	/^struct rtw89_dev {$/;"	s
rtw89_dig_gain_lna_idx	phy.h	/^enum rtw89_dig_gain_lna_idx {$/;"	g
rtw89_dig_gain_tia_idx	phy.h	/^enum rtw89_dig_gain_tia_idx {$/;"	g
rtw89_dig_gain_type	phy.h	/^enum rtw89_dig_gain_type {$/;"	g
rtw89_dig_info	core.h	/^struct rtw89_dig_info {$/;"	s
rtw89_dig_noisy_level	core.h	/^enum rtw89_dig_noisy_level {$/;"	g
rtw89_disable_ps_mode	core.c	/^static bool rtw89_disable_ps_mode;$/;"	v	file:
rtw89_dle_info	core.h	/^struct rtw89_dle_info {$/;"	s
rtw89_dle_mem	core.h	/^struct rtw89_dle_mem {$/;"	s
rtw89_dle_size	core.h	/^struct rtw89_dle_size {$/;"	s
rtw89_dma_ch	core.h	/^enum rtw89_dma_ch {$/;"	g
rtw89_dpk_bkup_para	core.h	/^struct rtw89_dpk_bkup_para {$/;"	s
rtw89_dpk_info	core.h	/^struct rtw89_dpk_info {$/;"	s
rtw89_dump_logical_efuse_map	efuse.c	/^static int rtw89_dump_logical_efuse_map(struct rtw89_dev *rtwdev, u8 *phy_map,$/;"	f	file:
rtw89_dump_physical_efuse_map	efuse.c	/^static int rtw89_dump_physical_efuse_map(struct rtw89_dev *rtwdev, u8 *map,$/;"	f	file:
rtw89_early_h2c	core.h	/^struct rtw89_early_h2c {$/;"	s
rtw89_efuse	core.h	/^struct rtw89_efuse {$/;"	s
rtw89_efuse_bank	efuse.c	/^enum rtw89_efuse_bank {$/;"	g	file:
rtw89_enter_ips	ps.c	/^void rtw89_enter_ips(struct rtw89_dev *rtwdev)$/;"	f
rtw89_enter_lps	ps.c	/^void rtw89_enter_lps(struct rtw89_dev *rtwdev, u8 mac_id)$/;"	f
rtw89_enter_lps_track	core.c	/^static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_env_monitor_info	core.h	/^struct rtw89_env_monitor_info {$/;"	s
rtw89_env_monitor_result_level	phy.h	/^enum rtw89_env_monitor_result_level {$/;"	g
rtw89_env_racing_lv	core.h	/^enum rtw89_env_racing_lv {$/;"	g
rtw89_err	debug.h	47;"	d
rtw89_fbtc_ext_ctrl_type	core.h	/^enum rtw89_fbtc_ext_ctrl_type {$/;"	g
rtw89_fem_info	core.h	/^struct rtw89_fem_info {$/;"	s
rtw89_flags	core.h	/^enum rtw89_flags {$/;"	g
rtw89_for_each_rtwvif	util.h	14;"	d
rtw89_fw_bin_info	fw.h	/^struct rtw89_fw_bin_info {$/;"	s
rtw89_fw_c2h_category	fw.h	/^enum rtw89_fw_c2h_category {$/;"	g
rtw89_fw_c2h_cmd_handle	fw.c	/^static void rtw89_fw_c2h_cmd_handle(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_fw_c2h_irqsafe	fw.c	/^void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h)$/;"	f
rtw89_fw_c2h_work	fw.c	/^void rtw89_fw_c2h_work(struct work_struct *work)$/;"	f
rtw89_fw_check_rdy	fw.c	/^int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_dl_fail_dump	fw.c	/^static void rtw89_fw_dl_fail_dump(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_fw_dl_status	fw.h	/^enum rtw89_fw_dl_status {$/;"	g
rtw89_fw_download	fw.c	/^int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type)$/;"	f
rtw89_fw_download_hdr	fw.c	/^static int rtw89_fw_download_hdr(struct rtw89_dev *rtwdev, const u8 *fw, u32 len)$/;"	f	file:
rtw89_fw_download_main	fw.c	/^static int rtw89_fw_download_main(struct rtw89_dev *rtwdev, const u8 *fw,$/;"	f	file:
rtw89_fw_free_all_early_h2c	fw.c	/^void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_alloc_skb	fw.c	/^static struct sk_buff *rtw89_fw_h2c_alloc_skb(u32 len, bool header)$/;"	f	file:
rtw89_fw_h2c_alloc_skb_no_hdr	fw.c	/^struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(u32 len)$/;"	f
rtw89_fw_h2c_alloc_skb_with_hdr	fw.c	/^struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(u32 len)$/;"	f
rtw89_fw_h2c_assoc_cmac_tbl	fw.c	/^int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_h2c_ba_cam	fw.c	/^int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, bool valid, u8 macid,$/;"	f
rtw89_fw_h2c_cam	fw.c	/^int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_fw_h2c_cxdrv_ctrl	fw.c	/^int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_cxdrv_init	fw.c	/^int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_cxdrv_rfk	fw.c	/^int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_cxdrv_role	fw.c	/^int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_default_cmac_tbl	fw.c	/^int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, u8 macid)$/;"	f
rtw89_fw_h2c_fw_log	fw.c	/^int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable)$/;"	f
rtw89_fw_h2c_general_pkt	fw.c	/^int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid)$/;"	f
rtw89_fw_h2c_join_info	fw.c	/^int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_fw_h2c_lps_parm	fw.c	/^int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_h2c_macid_pause	fw.c	/^int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp,$/;"	f
rtw89_fw_h2c_ra	fw.c	/^int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi)$/;"	f
rtw89_fw_h2c_raw	fw.c	/^int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len)$/;"	f
rtw89_fw_h2c_raw_with_hdr	fw.c	/^int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_h2c_rf_reg	fw.c	/^int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_h2c_rf_reg_info	fw.h	/^struct rtw89_fw_h2c_rf_reg_info {$/;"	s
rtw89_fw_h2c_set_edca	fw.c	/^int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_fw_h2c_set_ofld_cfg	fw.c	/^int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_h2c_txtime_cmac_tbl	fw.c	/^int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_h2c_vif_maintain	fw.c	/^int rtw89_fw_h2c_vif_maintain(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_hdr_parser	fw.c	/^static int rtw89_fw_hdr_parser(struct rtw89_dev *rtwdev, const u8 *fw, u32 len,$/;"	f	file:
rtw89_fw_hdr_section_info	fw.h	/^struct rtw89_fw_hdr_section_info {$/;"	s
rtw89_fw_info	core.h	/^struct rtw89_fw_info {$/;"	s
rtw89_fw_leave_lps_check	ps.c	/^static int rtw89_fw_leave_lps_check(struct rtw89_dev *rtwdev, u8 macid)$/;"	f	file:
rtw89_fw_log_comp	fw.h	/^enum rtw89_fw_log_comp {$/;"	g
rtw89_fw_log_level	fw.h	/^enum rtw89_fw_log_level {$/;"	g
rtw89_fw_log_path	fw.h	/^enum rtw89_fw_log_path {$/;"	g
rtw89_fw_macid_pause_grp	fw.h	/^struct rtw89_fw_macid_pause_grp {$/;"	s
rtw89_fw_msg_reg	fw.c	/^int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_prog_cnt_dump	fw.c	/^static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_fw_read_c2h_reg	fw.c	/^static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_fw_recognize	fw.c	/^int rtw89_fw_recognize(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_recognize_features	fw.c	/^static void rtw89_fw_recognize_features(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_fw_send_all_early_h2c	fw.c	/^void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_st_dbg_dump	fw.c	/^void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev)$/;"	f
rtw89_fw_suit	core.h	/^struct rtw89_fw_suit {$/;"	s
rtw89_fw_suit_get	core.h	/^static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,$/;"	f
rtw89_fw_type	core.h	/^enum rtw89_fw_type {$/;"	g
rtw89_fw_update_ver	fw.c	/^static void rtw89_fw_update_ver(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_fw_write_h2c_reg	fw.c	/^static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_get_channel_params	core.c	/^static void rtw89_get_channel_params(struct cfg80211_chan_def *chandef,$/;"	f	file:
rtw89_get_traffic_level	core.c	/^static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_gi_ltf	core.h	/^enum rtw89_gi_ltf {$/;"	g
rtw89_h2c_pkt_set_hdr	fw.c	/^void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb,$/;"	f
rtw89_h2c_pkt_set_hdr_fwdl	fw.c	/^static void rtw89_h2c_pkt_set_hdr_fwdl(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_h2c_tx	core.c	/^int rtw89_h2c_tx(struct rtw89_dev *rtwdev,$/;"	f
rtw89_h2creg_sch_tx_en	fw.h	/^struct rtw89_h2creg_sch_tx_en {$/;"	s
rtw89_hal	core.h	/^struct rtw89_hal {$/;"	s
rtw89_hci_check_and_reclaim_tx_resource	core.h	/^static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)$/;"	f
rtw89_hci_deinit	core.h	/^static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)$/;"	f
rtw89_hci_flush_queues	core.h	/^static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,$/;"	f
rtw89_hci_info	core.h	/^struct rtw89_hci_info {$/;"	s
rtw89_hci_ops	core.h	/^struct rtw89_hci_ops {$/;"	s
rtw89_hci_recalc_int_mit	core.h	/^static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)$/;"	f
rtw89_hci_reset	core.h	/^static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)$/;"	f
rtw89_hci_start	core.h	/^static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)$/;"	f
rtw89_hci_stop	core.h	/^static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)$/;"	f
rtw89_hci_tx_kick_off	core.h	/^static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)$/;"	f
rtw89_hci_tx_write	core.h	/^static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,$/;"	f
rtw89_hci_type	core.h	/^enum rtw89_hci_type {$/;"	g
rtw89_hcifc_mode	core.h	/^enum rtw89_hcifc_mode {$/;"	g
rtw89_hex2bin_user	debug.c	/^static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_hex_dump	debug.h	/^static inline void rtw89_hex_dump(struct rtw89_dev *rtwdev,$/;"	f
rtw89_hfc_ch_cfg	core.h	/^struct rtw89_hfc_ch_cfg {$/;"	s
rtw89_hfc_ch_info	core.h	/^struct rtw89_hfc_ch_info {$/;"	s
rtw89_hfc_param	core.h	/^struct rtw89_hfc_param {$/;"	s
rtw89_hfc_param_ini	core.h	/^struct rtw89_hfc_param_ini {$/;"	s
rtw89_hfc_prec_cfg	core.h	/^struct rtw89_hfc_prec_cfg {$/;"	s
rtw89_hfc_pub_cfg	core.h	/^struct rtw89_hfc_pub_cfg {$/;"	s
rtw89_hfc_pub_info	core.h	/^struct rtw89_hfc_pub_info {$/;"	s
rtw89_host_rpr_mode	core.h	/^enum rtw89_host_rpr_mode {$/;"	g
rtw89_hw_rate	core.h	/^enum rtw89_hw_rate {$/;"	g
rtw89_hw_sch_tx_en_h2c	mac.c	/^static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,$/;"	f	file:
rtw89_ifs_clm_application	core.h	/^enum rtw89_ifs_clm_application {$/;"	g
rtw89_info	debug.h	45;"	d
rtw89_init_he_cap	core.c	/^static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_init_ht_cap	core.c	/^static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_init_vht_cap	core.c	/^static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_iqk_info	core.h	/^struct rtw89_iqk_info {$/;"	s
rtw89_iter_bitrate_mask_data	mac80211.c	/^struct rtw89_iter_bitrate_mask_data {$/;"	s	file:
rtw89_iterate_vifs_bh	util.h	9;"	d
rtw89_last_rpwm_mode	core.h	/^enum rtw89_last_rpwm_mode {$/;"	g
rtw89_leave_ips	ps.c	/^void rtw89_leave_ips(struct rtw89_dev *rtwdev)$/;"	f
rtw89_leave_lps	ps.c	/^void rtw89_leave_lps(struct rtw89_dev *rtwdev)$/;"	f
rtw89_leave_lps_vif	ps.c	/^static void rtw89_leave_lps_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f	file:
rtw89_leave_ps_mode	ps.c	/^void rtw89_leave_ps_mode(struct rtw89_dev *rtwdev)$/;"	f
rtw89_load_firmware	fw.c	/^int rtw89_load_firmware(struct rtw89_dev *rtwdev)$/;"	f
rtw89_load_firmware_cb	fw.c	/^static void rtw89_load_firmware_cb(const struct firmware *firmware, void *context)$/;"	f	file:
rtw89_load_txpwr_table	core.h	/^static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,$/;"	f
rtw89_lps_parm	core.h	/^struct rtw89_lps_parm {$/;"	s
rtw89_lv1_rcvy_step	core.h	/^enum rtw89_lv1_rcvy_step {$/;"	g
rtw89_mac_add_vif	mac.c	/^int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_mac_ax_coex	mac.h	/^struct rtw89_mac_ax_coex {$/;"	s
rtw89_mac_ax_coex_gnt	core.h	/^struct rtw89_mac_ax_coex_gnt {$/;"	s
rtw89_mac_ax_gnt	core.h	/^struct rtw89_mac_ax_gnt {$/;"	s
rtw89_mac_ax_l0_to_l1_event	mac.h	/^enum rtw89_mac_ax_l0_to_l1_event {$/;"	g
rtw89_mac_ax_plt	mac.h	/^struct rtw89_mac_ax_plt {$/;"	s
rtw89_mac_ax_ps_mode	core.h	/^enum rtw89_mac_ax_ps_mode {$/;"	g
rtw89_mac_bf_assoc	mac.c	/^void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,$/;"	f
rtw89_mac_bf_disassoc	mac.c	/^void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,$/;"	f
rtw89_mac_bf_monitor_calc	mac.c	/^void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_bf_monitor_calc_iter	mac.c	/^void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_mac_bf_monitor_iter_data	mac.c	/^struct rtw89_mac_bf_monitor_iter_data {$/;"	s	file:
rtw89_mac_bf_monitor_track	mac.h	/^static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_bf_rrsc_rate	mac.h	/^enum rtw89_mac_bf_rrsc_rate {$/;"	g
rtw89_mac_bf_set_gid_table	mac.c	/^void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,$/;"	f
rtw89_mac_bfee_ctrl	mac.c	/^static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)$/;"	f	file:
rtw89_mac_c2h_class	mac.h	/^enum rtw89_mac_c2h_class {$/;"	g
rtw89_mac_c2h_done_ack	mac.c	/^rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)$/;"	f	file:
rtw89_mac_c2h_handle	mac.c	/^void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,$/;"	f
rtw89_mac_c2h_info	fw.h	/^struct rtw89_mac_c2h_info {$/;"	s
rtw89_mac_c2h_info_func	mac.h	/^enum rtw89_mac_c2h_info_func {$/;"	g
rtw89_mac_c2h_info_handler	mac.c	/^void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,$/;"	v	file:
rtw89_mac_c2h_log	mac.c	/^rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)$/;"	f	file:
rtw89_mac_c2h_macid_pause	mac.c	/^rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)$/;"	f	file:
rtw89_mac_c2h_ofld_func	mac.h	/^enum rtw89_mac_c2h_ofld_func {$/;"	g
rtw89_mac_c2h_ofld_handler	mac.c	/^void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,$/;"	v	file:
rtw89_mac_c2h_rec_ack	mac.c	/^rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)$/;"	f	file:
rtw89_mac_c2h_type	fw.h	/^enum rtw89_mac_c2h_type {$/;"	g
rtw89_mac_cfg_ctrl_path	mac.c	/^int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)$/;"	f
rtw89_mac_cfg_gnt	mac.c	/^int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_cfg_plt	mac.c	/^int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)$/;"	f
rtw89_mac_cfg_ppdu_status	mac.c	/^int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)$/;"	f
rtw89_mac_cfg_sb	mac.c	/^void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)$/;"	f
rtw89_mac_check_cpwm_state	mac.c	/^static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_check_mac_en	mac.c	/^int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,$/;"	f
rtw89_mac_cmac_tbl_init	mac.c	/^static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)$/;"	f	file:
rtw89_mac_coex_init	mac.c	/^int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)$/;"	f
rtw89_mac_cpuio_op_cmd_type	mac.h	/^enum rtw89_mac_cpuio_op_cmd_type {$/;"	g
rtw89_mac_csi_rrsc	mac.c	/^static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_dbcc_enable	mac.c	/^static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
rtw89_mac_dbg_port_info	mac.h	/^struct rtw89_mac_dbg_port_info {$/;"	s
rtw89_mac_dbg_port_sel	mac.h	/^enum rtw89_mac_dbg_port_sel {$/;"	g
rtw89_mac_disable_bb_rf	mac.c	/^void rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_disable_cpu	mac.c	/^static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_dle_buf_req	mac.c	/^static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len,$/;"	f	file:
rtw89_mac_dle_ctrl_type	mac.h	/^enum rtw89_mac_dle_ctrl_type {$/;"	g
rtw89_mac_dle_dfi_ctrl	mac.h	/^struct rtw89_mac_dle_dfi_ctrl {$/;"	s
rtw89_mac_dle_dfi_qempty	mac.h	/^struct rtw89_mac_dle_dfi_qempty {$/;"	s
rtw89_mac_dle_dfi_quota	mac.h	/^struct rtw89_mac_dle_dfi_quota {$/;"	s
rtw89_mac_dle_dfi_type	mac.h	/^enum rtw89_mac_dle_dfi_type {$/;"	g
rtw89_mac_dle_ple_quota_id	mac.h	/^enum rtw89_mac_dle_ple_quota_id {$/;"	g
rtw89_mac_dle_wde_quota_id	mac.h	/^enum rtw89_mac_dle_wde_quota_id {$/;"	g
rtw89_mac_dmac_tbl_init	mac.c	/^static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)$/;"	f	file:
rtw89_mac_dump_err_status	mac.c	/^static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_dump_l0_to_l1	mac.c	/^static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_dump_qta_lost	mac.c	/^static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_enable_bb_rf	mac.c	/^void rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_enable_cpu	mac.c	/^static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason,$/;"	f	file:
rtw89_mac_enable_imr	mac.c	/^static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,$/;"	f	file:
rtw89_mac_flush_txq	mac.c	/^void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)$/;"	f
rtw89_mac_fw_dl_pre_init	mac.c	/^static int rtw89_mac_fw_dl_pre_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_fwd_target	mac.h	/^enum rtw89_mac_fwd_target {$/;"	g
rtw89_mac_get_ctrl_path	mac.c	/^bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_get_err_status	mac.c	/^EXPORT_SYMBOL(rtw89_mac_get_err_status);$/;"	v
rtw89_mac_get_err_status	mac.c	/^u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_get_req_pwr_state	mac.c	/^rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_get_sb	mac.c	/^u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_get_tx_retry_limit	mac.c	/^int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_get_tx_time	mac.c	/^int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,$/;"	f
rtw89_mac_get_txpwr_cr	mac.c	/^bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_h2c_info	fw.h	/^struct rtw89_mac_h2c_info {$/;"	s
rtw89_mac_h2c_type	fw.h	/^enum rtw89_mac_h2c_type {$/;"	g
rtw89_mac_hci_func_en	mac.c	/^static void rtw89_mac_hci_func_en(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_hwmod_sel	mac.h	/^enum rtw89_mac_hwmod_sel {$/;"	g
rtw89_mac_idx	core.h	/^enum rtw89_mac_idx {$/;"	g
rtw89_mac_info	core.h	/^struct rtw89_mac_info {$/;"	s
rtw89_mac_init	mac.c	/^int rtw89_mac_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_init_bfee	mac.c	/^static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
rtw89_mac_lbc_tmr	mac.h	/^enum rtw89_mac_lbc_tmr {$/;"	g
rtw89_mac_mem_sel	mac.h	/^enum rtw89_mac_mem_sel {$/;"	g
rtw89_mac_multi_tag_num	mac.h	/^enum rtw89_mac_multi_tag_num {$/;"	g
rtw89_mac_partial_init	mac.c	/^int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_ple_dle_port_id	mac.h	/^enum rtw89_mac_ple_dle_port_id {$/;"	g
rtw89_mac_ple_dle_queid_plrls	mac.h	/^enum rtw89_mac_ple_dle_queid_plrls {$/;"	g
rtw89_mac_port_cfg_bcn_early	mac.c	/^static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bcn_hold_time	mac.c	/^static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bcn_intv	mac.c	/^static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bcn_mask_area	mac.c	/^static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bcn_prct	mac.c	/^static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bcn_setup_time	mac.c	/^static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_bss_color	mac.c	/^static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_func_en	mac.c	/^static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_func_sw	mac.c	/^static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_hiq_drop	mac.c	/^static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_mbssid	mac.c	/^static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_net_type	mac.c	/^static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_rx_rpt	mac.c	/^static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_rx_sw	mac.c	/^static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_rx_sync	mac.c	/^static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_tbtt_early	mac.c	/^static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_tx_rpt	mac.c	/^static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_cfg_tx_sw	mac.c	/^static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_port_update	mac.c	/^int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_mac_power_mode_change	mac.c	/^void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)$/;"	f
rtw89_mac_power_switch	mac.c	/^static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)$/;"	f	file:
rtw89_mac_pwr_off	mac.c	/^void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_pwr_seq	mac.c	/^static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_read_lte	mac.c	/^int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)$/;"	f
rtw89_mac_read_phycap	mac.c	/^static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_reg_by_idx	mac.h	/^static inline u32 rtw89_mac_reg_by_idx(u32 reg_base, u8 band)$/;"	f
rtw89_mac_reg_by_port	mac.h	/^static inline u32 rtw89_mac_reg_by_port(u32 base, u8 port, u8 mac_idx)$/;"	f
rtw89_mac_remove_vif	mac.c	/^int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_mac_resume_sch_tx	mac.c	/^int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en)$/;"	f
rtw89_mac_send_rpwm	mac.c	/^static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_set_cpuio	mac.c	/^static int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_set_csi_para_reg	mac.c	/^static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_set_err_status	mac.c	/^EXPORT_SYMBOL(rtw89_mac_set_err_status);$/;"	v
rtw89_mac_set_err_status	mac.c	/^int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)$/;"	f
rtw89_mac_set_hw_muedca_ctrl	mac.c	/^int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_set_tx_retry_limit	mac.c	/^int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_set_tx_time	mac.c	/^int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,$/;"	f
rtw89_mac_setup_phycap	mac.c	/^int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)$/;"	f
rtw89_mac_stop_sch_tx	mac.c	/^int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,$/;"	f
rtw89_mac_sub_pwr_seq	mac.c	/^static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,$/;"	f	file:
rtw89_mac_sys_init	mac.c	/^static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_trx_init	mac.c	/^static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_mac_txpwr_read32	mac.h	/^static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_txpwr_write32	mac.h	/^static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_txpwr_write32_mask	mac.h	/^static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev,$/;"	f
rtw89_mac_typ_fltr_opt	mac.c	/^static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_mac_update_rts_threshold	mac.c	/^void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f
rtw89_mac_vif_deinit	mac.c	/^int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_mac_vif_init	mac.c	/^int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f
rtw89_mac_wd_dma_intvl	mac.h	/^enum rtw89_mac_wd_dma_intvl {$/;"	g
rtw89_mac_wde_dle_port_id	mac.h	/^enum rtw89_mac_wde_dle_port_id {$/;"	g
rtw89_mac_wde_dle_queid_wdrls	mac.h	/^enum rtw89_mac_wde_dle_queid_wdrls {$/;"	g
rtw89_mac_write_lte	mac.c	/^int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)$/;"	f
rtw89_machdr_frame_type	mac.h	/^enum rtw89_machdr_frame_type {$/;"	g
rtw89_mfw_hdr	fw.h	/^struct rtw89_mfw_hdr {$/;"	s
rtw89_mfw_info	fw.h	/^struct rtw89_mfw_info {$/;"	s
rtw89_mfw_recognize	fw.c	/^int rtw89_mfw_recognize(struct rtw89_dev *rtwdev, enum rtw89_fw_type type,$/;"	f	file:
rtw89_msk_sO_el	core.h	/^enum rtw89_msk_sO_el {$/;"	g
rtw89_multi_cfo_mode	core.h	/^	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;$/;"	m	struct:rtw89_cfo_tracking_info	typeref:enum:rtw89_cfo_tracking_info::rtw89_multi_cfo_mode
rtw89_multi_cfo_mode	core.h	/^enum rtw89_multi_cfo_mode {$/;"	g
rtw89_net_type	core.h	/^enum rtw89_net_type {$/;"	g
rtw89_nss	core.h	/^enum rtw89_nss {$/;"	g
rtw89_ntx	core.h	/^enum rtw89_ntx {$/;"	g
rtw89_ops	mac80211.c	/^EXPORT_SYMBOL(rtw89_ops);$/;"	v
rtw89_ops	mac80211.c	/^const struct ieee80211_ops rtw89_ops = {$/;"	v	typeref:struct:ieee80211_ops
rtw89_ops_add_interface	mac80211.c	/^static int rtw89_ops_add_interface(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_ampdu_action	mac80211.c	/^static int rtw89_ops_ampdu_action(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_bss_info_changed	mac80211.c	/^static void rtw89_ops_bss_info_changed(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_conf_tx	mac80211.c	/^static int rtw89_ops_conf_tx(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_config	mac80211.c	/^static int rtw89_ops_config(struct ieee80211_hw *hw, u32 changed)$/;"	f	file:
rtw89_ops_configure_filter	mac80211.c	/^static void rtw89_ops_configure_filter(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_flush	mac80211.c	/^static void rtw89_ops_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,$/;"	f	file:
rtw89_ops_get_antenna	mac80211.c	/^int rtw89_ops_get_antenna(struct ieee80211_hw *hw,  u32 *tx_ant, u32 *rx_ant)$/;"	f	file:
rtw89_ops_reconfig_complete	mac80211.c	/^static void rtw89_ops_reconfig_complete(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_remove_interface	mac80211.c	/^static void rtw89_ops_remove_interface(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_set_antenna	mac80211.c	/^int rtw89_ops_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)$/;"	f	file:
rtw89_ops_set_bitrate_mask	mac80211.c	/^static int rtw89_ops_set_bitrate_mask(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_set_key	mac80211.c	/^static int rtw89_ops_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,$/;"	f	file:
rtw89_ops_set_rts_threshold	mac80211.c	/^static int rtw89_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value)$/;"	f	file:
rtw89_ops_set_sar_specs	sar.c	/^int rtw89_ops_set_sar_specs(struct ieee80211_hw *hw,$/;"	f
rtw89_ops_sta_state	mac80211.c	/^static int rtw89_ops_sta_state(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_sta_statistics	mac80211.c	/^static void rtw89_ops_sta_statistics(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_start	mac80211.c	/^static int rtw89_ops_start(struct ieee80211_hw *hw)$/;"	f	file:
rtw89_ops_stop	mac80211.c	/^static void rtw89_ops_stop(struct ieee80211_hw *hw)$/;"	f	file:
rtw89_ops_sw_scan_complete	mac80211.c	/^static void rtw89_ops_sw_scan_complete(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_sw_scan_start	mac80211.c	/^static void rtw89_ops_sw_scan_start(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_tx	mac80211.c	/^static void rtw89_ops_tx(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_ops_wake_tx_queue	mac80211.c	/^static void rtw89_ops_wake_tx_queue(struct ieee80211_hw *hw,$/;"	f	file:
rtw89_parse_efuse_map	efuse.c	/^int rtw89_parse_efuse_map(struct rtw89_dev *rtwdev)$/;"	f
rtw89_parse_phycap_map	efuse.c	/^int rtw89_parse_phycap_map(struct rtw89_dev *rtwdev)$/;"	f
rtw89_pci	pci.h	/^struct rtw89_pci {$/;"	s
rtw89_pci-y	Makefile	/^rtw89_pci-y := pci.o$/;"	m
rtw89_pci_alloc_rx_ring	pci.c	/^static int rtw89_pci_alloc_rx_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_alloc_rx_rings	pci.c	/^static int rtw89_pci_alloc_rx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_alloc_trx_rings	pci.c	/^static int rtw89_pci_alloc_trx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_alloc_tx_ring	pci.c	/^static int rtw89_pci_alloc_tx_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_alloc_tx_rings	pci.c	/^static int rtw89_pci_alloc_tx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_alloc_tx_wd_ring	pci.c	/^static int rtw89_pci_alloc_tx_wd_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_aphy_pwrcut	pci.c	/^static void rtw89_pci_aphy_pwrcut(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_aspm_set	pci.c	/^static void rtw89_pci_aspm_set(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
rtw89_pci_auto_refclk_cal	pci.c	/^static int rtw89_pci_auto_refclk_cal(struct rtw89_dev *rtwdev, bool autook_en)$/;"	f	file:
rtw89_pci_bd_ram	pci.h	/^struct rtw89_pci_bd_ram {$/;"	s
rtw89_pci_check_and_reclaim_tx_resource	pci.c	/^static u32 rtw89_pci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_check_mdio	pci.c	/^static int rtw89_pci_check_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 rw_bit)$/;"	f	file:
rtw89_pci_claim_device	pci.c	/^static int rtw89_pci_claim_device(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_clear_isr0	pci.c	/^static void rtw89_pci_clear_isr0(struct rtw89_dev *rtwdev, u32 isr00)$/;"	f	file:
rtw89_pci_clear_mapping	pci.c	/^static void rtw89_pci_clear_mapping(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_clear_resource	pci.c	/^static void rtw89_pci_clear_resource(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_clkreq_set	pci.c	/^static void rtw89_pci_clkreq_set(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
rtw89_pci_clr_idx_all	pci.c	/^static void rtw89_pci_clr_idx_all(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ctrl_dma_all	pci.c	/^static void rtw89_pci_ctrl_dma_all(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
rtw89_pci_ctrl_dma_all_pcie	pci.c	/^static void rtw89_pci_ctrl_dma_all_pcie(struct rtw89_dev *rtwdev, u8 en)$/;"	f	file:
rtw89_pci_ctrl_hci_dma_en	pci.c	/^static void rtw89_pci_ctrl_hci_dma_en(struct rtw89_dev *rtwdev, u8 en)$/;"	f	file:
rtw89_pci_declaim_device	pci.c	/^static void rtw89_pci_declaim_device(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_default_intr_mask	pci.c	/^static void rtw89_pci_default_intr_mask(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_deglitch_setting	pci.c	/^static int rtw89_pci_deglitch_setting(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_dequeue_txwd	pci.h	/^rtw89_pci_dequeue_txwd(struct rtw89_pci_tx_ring *tx_ring)$/;"	f
rtw89_pci_disable_aspm_l1	pci.c	/^static bool rtw89_pci_disable_aspm_l1;$/;"	v	file:
rtw89_pci_disable_clkreq	pci.c	/^static bool rtw89_pci_disable_clkreq;$/;"	v	file:
rtw89_pci_disable_intr	pci.c	/^static void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_disable_l1ss	pci.c	/^static bool rtw89_pci_disable_l1ss;$/;"	v	file:
rtw89_pci_dma_recalc	pci.c	/^static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_dma_ring	pci.h	/^struct rtw89_pci_dma_ring {$/;"	s
rtw89_pci_driver	pci.c	/^module_pci_driver(rtw89_pci_driver);$/;"	v
rtw89_pci_driver	pci.c	/^static struct pci_driver rtw89_pci_driver = {$/;"	v	typeref:struct:pci_driver	file:
rtw89_pci_enable_intr	pci.c	/^static void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_enqueue_txwd	pci.h	/^rtw89_pci_enqueue_txwd(struct rtw89_pci_tx_ring *tx_ring,$/;"	f
rtw89_pci_free_irq	pci.c	/^static void rtw89_pci_free_irq(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_rx_ring	pci.c	/^static void rtw89_pci_free_rx_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_rx_rings	pci.c	/^static void rtw89_pci_free_rx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_trx_rings	pci.c	/^static void rtw89_pci_free_trx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_tx_ring	pci.c	/^static void rtw89_pci_free_tx_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_tx_rings	pci.c	/^static void rtw89_pci_free_tx_rings(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_free_tx_wd_ring	pci.c	/^static void rtw89_pci_free_tx_wd_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_fwcmd_submit	pci.c	/^static int rtw89_pci_fwcmd_submit(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_get_avail_txbd_num	pci.c	/^static u32 rtw89_pci_get_avail_txbd_num(struct rtw89_pci_tx_ring *ring)$/;"	f	file:
rtw89_pci_get_next_txbd	pci.h	/^rtw89_pci_get_next_txbd(struct rtw89_pci_tx_ring *tx_ring)$/;"	f
rtw89_pci_get_rxch_addrs	pci.c	/^static int rtw89_pci_get_rxch_addrs(enum rtw89_rx_channel rxch,$/;"	f	file:
rtw89_pci_get_txch_addrs	pci.c	/^static int rtw89_pci_get_txch_addrs(enum rtw89_tx_channel txch,$/;"	f	file:
rtw89_pci_h2c_init	pci.c	/^static void rtw89_pci_h2c_init(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_hci_ldo	pci.c	/^static void rtw89_pci_hci_ldo(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_id_table	pci.c	/^static const struct pci_device_id rtw89_pci_id_table[] = {$/;"	v	typeref:struct:pci_device_id	file:
rtw89_pci_init_rx_bd	pci.c	/^static int rtw89_pci_init_rx_bd(struct rtw89_dev *rtwdev, struct pci_dev *pdev,$/;"	f	file:
rtw89_pci_interrupt_handler	pci.c	/^static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev)$/;"	f	file:
rtw89_pci_interrupt_threadfn	pci.c	/^static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)$/;"	f	file:
rtw89_pci_isr_rxd_unavail	pci.c	/^static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_isrs	pci.h	/^struct rtw89_pci_isrs {$/;"	s
rtw89_pci_l1off_pwroff	pci.c	/^static void rtw89_pci_l1off_pwroff(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_l1ss_cfg	pci.c	/^static void rtw89_pci_l1ss_cfg(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_l1ss_set	pci.c	/^static void rtw89_pci_l1ss_set(struct rtw89_dev *rtwdev, bool enable)$/;"	f	file:
rtw89_pci_l2_hci_ldo	pci.c	/^static void rtw89_pci_l2_hci_ldo(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_l2_rxen_lat	pci.c	/^static u32 rtw89_pci_l2_rxen_lat(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_link_cfg	pci.c	/^static void rtw89_pci_link_cfg(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ltr_is_err_reg_val	pci.h	/^static inline bool rtw89_pci_ltr_is_err_reg_val(u32 val)$/;"	f
rtw89_pci_ltr_set	pci.c	/^static int rtw89_pci_ltr_set(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_lv1rst_start_dma	pci.c	/^static int rtw89_pci_lv1rst_start_dma(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_lv1rst_stop_dma	pci.c	/^static int rtw89_pci_lv1rst_stop_dma(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_napi_poll	pci.c	/^static int rtw89_pci_napi_poll(struct napi_struct *napi, int budget)$/;"	f	file:
rtw89_pci_ops	pci.c	/^static const struct rtw89_hci_ops rtw89_pci_ops = {$/;"	v	typeref:struct:rtw89_hci_ops	file:
rtw89_pci_ops_deinit	pci.c	/^static int rtw89_pci_ops_deinit(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_dump_err_status	pci.c	/^static void rtw89_pci_ops_dump_err_status(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_flush_queues	pci.c	/^static void rtw89_pci_ops_flush_queues(struct rtw89_dev *rtwdev, u32 queues,$/;"	f	file:
rtw89_pci_ops_mac_lv1_recovery	pci.c	/^static int rtw89_pci_ops_mac_lv1_recovery(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_ops_mac_post_init	pci.c	/^static int rtw89_pci_ops_mac_post_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_mac_pre_init	pci.c	/^static int rtw89_pci_ops_mac_pre_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_read16	pci.c	/^static u16 rtw89_pci_ops_read16(struct rtw89_dev *rtwdev, u32 addr)$/;"	f	file:
rtw89_pci_ops_read32	pci.c	/^static u32 rtw89_pci_ops_read32(struct rtw89_dev *rtwdev, u32 addr)$/;"	f	file:
rtw89_pci_ops_read32_cmac	pci.c	/^static u32 rtw89_pci_ops_read32_cmac(struct rtw89_dev *rtwdev, u32 addr)$/;"	f	file:
rtw89_pci_ops_read8	pci.c	/^static u8 rtw89_pci_ops_read8(struct rtw89_dev *rtwdev, u32 addr)$/;"	f	file:
rtw89_pci_ops_reset	pci.c	/^static void rtw89_pci_ops_reset(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_start	pci.c	/^static int rtw89_pci_ops_start(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_stop	pci.c	/^static void rtw89_pci_ops_stop(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_ops_tx_kick_off	pci.c	/^static void rtw89_pci_ops_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)$/;"	f	file:
rtw89_pci_ops_tx_write	pci.c	/^static int rtw89_pci_ops_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req)$/;"	f	file:
rtw89_pci_ops_write16	pci.c	/^static void rtw89_pci_ops_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)$/;"	f	file:
rtw89_pci_ops_write32	pci.c	/^static void rtw89_pci_ops_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)$/;"	f	file:
rtw89_pci_ops_write8	pci.c	/^static void rtw89_pci_ops_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)$/;"	f	file:
rtw89_pci_poll_io_idle	pci.c	/^static int rtw89_pci_poll_io_idle(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_poll_rpq_dma	pci.c	/^static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_poll_rxq_dma	pci.c	/^static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_probe	pci.c	/^static int rtw89_pci_probe(struct pci_dev *pdev,$/;"	f	file:
rtw89_pci_recalc_int_mit	pci.c	/^static void rtw89_pci_recalc_int_mit(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_reclaim_tx_fwcmd	pci.c	/^static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_reclaim_txbd	pci.c	/^static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring)$/;"	f	file:
rtw89_pci_recognize_intrs	pci.c	/^static void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_busy_txwd	pci.c	/^static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_fwcmd	pci.c	/^static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_pending_txwd_skb	pci.c	/^static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_rpp	pci.c	/^static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_tx	pci.c	/^static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_tx_ring	pci.c	/^static void rtw89_pci_release_tx_ring(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_tx_skbs	pci.c	/^static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_release_txwd_skb	pci.c	/^static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_remove	pci.c	/^static void rtw89_pci_remove(struct pci_dev *pdev)$/;"	f	file:
rtw89_pci_request_irq	pci.c	/^static int rtw89_pci_request_irq(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_reset_trx_rings	pci.c	/^static void rtw89_pci_reset_trx_rings(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_resume	pci.c	/^static int __maybe_unused rtw89_pci_resume(struct device *dev)$/;"	f	file:
rtw89_pci_rpp_fmt	pci.h	/^struct rtw89_pci_rpp_fmt {$/;"	s
rtw89_pci_rst_bdram	pci.c	/^static int rtw89_pci_rst_bdram(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_rst_bdram_pcie	pci.c	/^static int rtw89_pci_rst_bdram_pcie(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_rx_bd_32	pci.h	/^struct rtw89_pci_rx_bd_32 {$/;"	s
rtw89_pci_rx_info	pci.h	/^struct rtw89_pci_rx_info {$/;"	s
rtw89_pci_rx_ring	pci.h	/^struct rtw89_pci_rx_ring {$/;"	s
rtw89_pci_rxbd_deliver	pci.c	/^static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_rxbd_deliver_skbs	pci.c	/^static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_rxbd_increase	pci.h	/^rtw89_pci_rxbd_increase(struct rtw89_pci_rx_ring *rx_ring, u32 cnt)$/;"	f
rtw89_pci_rxbd_info	pci.h	/^struct rtw89_pci_rxbd_info {$/;"	s
rtw89_pci_rxbd_info_update	pci.c	/^static int rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_rxbd_recalc	pci.c	/^static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_rxdma_prefth	pci.c	/^static void rtw89_pci_rxdma_prefth(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_set_dbg	pci.c	/^static void rtw89_pci_set_dbg(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_set_sic	pci.c	/^static void rtw89_pci_set_sic(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_pci_setup_mapping	pci.c	/^static int rtw89_pci_setup_mapping(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_setup_resource	pci.c	/^static int rtw89_pci_setup_resource(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_suspend	pci.c	/^static int __maybe_unused rtw89_pci_suspend(struct device *dev)$/;"	f	file:
rtw89_pci_sync_skb_for_cpu	pci.c	/^static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_sync_skb_for_device	pci.c	/^static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_tx_addr_info_32	pci.h	/^struct rtw89_pci_tx_addr_info_32 {$/;"	s
rtw89_pci_tx_bd_32	pci.h	/^struct rtw89_pci_tx_bd_32 {$/;"	s
rtw89_pci_tx_bd_ring_update	pci.c	/^static void rtw89_pci_tx_bd_ring_update(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring,$/;"	f	file:
rtw89_pci_tx_data	pci.h	/^struct rtw89_pci_tx_data {$/;"	s
rtw89_pci_tx_ring	pci.h	/^struct rtw89_pci_tx_ring {$/;"	s
rtw89_pci_tx_status	pci.c	/^static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_tx_wd	pci.h	/^struct rtw89_pci_tx_wd {$/;"	s
rtw89_pci_tx_wd_ring	pci.h	/^struct rtw89_pci_tx_wd_ring {$/;"	s
rtw89_pci_tx_wp_info	pci.h	/^struct rtw89_pci_tx_wp_info {$/;"	s
rtw89_pci_tx_write	pci.c	/^static int rtw89_pci_tx_write(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req,$/;"	f	file:
rtw89_pci_txbd_recalc	pci.c	/^static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_txbd_submit	pci.c	/^static int rtw89_pci_txbd_submit(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pci_txwd_submit	pci.c	/^static int rtw89_pci_txwd_submit(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_pcie_clkdly_hw	pci.h	/^enum rtw89_pcie_clkdly_hw {$/;"	g
rtw89_pcie_l0sdly	pci.h	/^enum rtw89_pcie_l0sdly {$/;"	g
rtw89_pcie_l1dly	pci.h	/^enum rtw89_pcie_l1dly {$/;"	g
rtw89_pcie_phy	pci.h	/^enum rtw89_pcie_phy {$/;"	g
rtw89_phy0_phy1_offset	phy.c	/^static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)$/;"	f	file:
rtw89_phy_average_cfo_calc	phy.c	/^static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_bb_reset	phy.c	/^static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_c2h_class	phy.h	/^enum rtw89_phy_c2h_class {$/;"	g
rtw89_phy_c2h_handle	phy.c	/^void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,$/;"	f
rtw89_phy_c2h_ra_func	phy.h	/^enum rtw89_phy_c2h_ra_func {$/;"	g
rtw89_phy_c2h_ra_handler	phy.c	/^void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,$/;"	v	file:
rtw89_phy_c2h_ra_rpt	phy.c	/^rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)$/;"	f	file:
rtw89_phy_c2h_ra_rpt_iter	phy.c	/^static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_phy_ccx_get_report	phy.c	/^static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,$/;"	f	file:
rtw89_phy_ccx_idx_to_us	phy.c	/^static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)$/;"	f	file:
rtw89_phy_ccx_ms_to_period_unit	phy.c	/^static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_ccx_racing_ctrl	phy.c	/^static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_ccx_racing_release	phy.c	/^static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ccx_top_setting_init	phy.c	/^static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ccx_trigger	phy.c	/^static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ccx_us_to_idx	phy.c	/^static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)$/;"	f	file:
rtw89_phy_cfo_crystal_cap_adjust	phy.c	/^static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_cfo_dm	phy.c	/^static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_cfo_get_xcap_reg	phy.c	/^static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)$/;"	f	file:
rtw89_phy_cfo_init	phy.c	/^static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_cfo_parse	phy.c	/^void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,$/;"	f
rtw89_phy_cfo_reset	phy.c	/^static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_cfo_set_crystal_cap	phy.c	/^static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_cfo_set_xcap_reg	phy.c	/^static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,$/;"	f	file:
rtw89_phy_cfo_start_work	phy.c	/^static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_cfo_statistics_reset	phy.c	/^static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_cfo_status	core.h	/^enum rtw89_phy_cfo_status {$/;"	g
rtw89_phy_cfo_track	phy.c	/^void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_cfo_track_work	phy.c	/^void rtw89_phy_cfo_track_work(struct work_struct *work)$/;"	f
rtw89_phy_ch_info	core.h	/^struct rtw89_phy_ch_info {$/;"	s
rtw89_phy_cofig_rf_reg_store	phy.c	/^rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_config_bb_reg	phy.c	/^static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_config_rf_h2c	fw.h	/^	__le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE];$/;"	m	struct:rtw89_fw_h2c_rf_reg_info
rtw89_phy_config_rf_reg	phy.c	/^static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_config_rf_reg_fw	phy.c	/^static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_dig	phy.c	/^void rtw89_phy_dig(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_dig_dyn_pd_th	phy.c	/^static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,$/;"	f	file:
rtw89_phy_dig_gain_cfg	phy.h	/^struct rtw89_phy_dig_gain_cfg {$/;"	s
rtw89_phy_dig_gain_table	phy.h	/^struct rtw89_phy_dig_gain_table {$/;"	s
rtw89_phy_dig_gaincode_by_rssi	phy.c	/^static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,$/;"	f	file:
rtw89_phy_dig_igi_offset_by_env	phy.c	/^static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dig_init	phy.c	/^static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dig_lna_idx_by_rssi	phy.c	/^static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)$/;"	f	file:
rtw89_phy_dig_para_reset	phy.c	/^static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dig_read_gain_table	phy.c	/^static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)$/;"	f	file:
rtw89_phy_dig_reset	phy.c	/^void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_dig_rxb_idx_by_rssi	phy.c	/^static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,$/;"	f	file:
rtw89_phy_dig_sdagc_follow_pagc_config	phy.c	/^static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_dig_set_igi_cr	phy.c	/^static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_dig_set_lna_idx	phy.c	/^static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)$/;"	f	file:
rtw89_phy_dig_set_rxb_idx	phy.c	/^static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)$/;"	f	file:
rtw89_phy_dig_set_tia_idx	phy.c	/^static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)$/;"	f	file:
rtw89_phy_dig_tia_idx_by_rssi	phy.c	/^static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)$/;"	f	file:
rtw89_phy_dig_update_gain_para	phy.c	/^static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dig_update_para	phy.c	/^static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dig_update_rssi_info	phy.c	/^static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_dm_init	phy.c	/^void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_env_monitor_init	phy.c	/^static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_env_monitor_track	phy.c	/^void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_fill_txpwr_limit	phy.c	/^void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_fill_txpwr_limit_20m	phy.c	/^static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_fill_txpwr_limit_40m	phy.c	/^static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_fill_txpwr_limit_80m	phy.c	/^static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_fill_txpwr_limit_ru	phy.c	/^void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_fill_txpwr_limit_ru_20m	phy.c	/^rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_fill_txpwr_limit_ru_40m	phy.c	/^rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_fill_txpwr_limit_ru_80m	phy.c	/^rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_get_txsc	phy.c	/^u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_idx	core.h	/^enum rtw89_phy_idx {$/;"	g
rtw89_phy_ifs_clm_get_result	phy.c	/^static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ifs_clm_get_utility	phy.c	/^static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ifs_clm_set	phy.c	/^static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_ifs_clm_set_th_reg	phy.c	/^static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ifs_clm_setting_init	phy.c	/^static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ifs_clm_th_update_check	phy.c	/^static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_init_bb_reg	phy.c	/^void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_init_reg	phy.c	/^static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_init_rf_nctl	phy.c	/^static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_init_rf_reg	phy.c	/^void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_iter_ra_data	phy.c	/^struct rtw89_phy_iter_ra_data {$/;"	s	file:
rtw89_phy_iter_rssi_data	phy.c	/^struct rtw89_phy_iter_rssi_data {$/;"	s	file:
rtw89_phy_load_txpwr_byrate	phy.c	/^void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_multi_sta_cfo_calc	phy.c	/^static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_nctl_poll	phy.c	/^static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_ra_assoc	phy.c	/^void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)$/;"	f
rtw89_phy_ra_mask_cfg	phy.c	/^static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)$/;"	f	file:
rtw89_phy_ra_mask_rssi	phy.c	/^static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,$/;"	f	file:
rtw89_phy_ra_sta_update	phy.c	/^static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_ra_updata_sta	phy.c	/^void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta)$/;"	f
rtw89_phy_ra_updata_sta_iter	phy.c	/^static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_phy_ra_update	phy.c	/^void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_rate_pattern	core.h	/^struct rtw89_phy_rate_pattern {$/;"	s
rtw89_phy_rate_pattern_vif	phy.c	/^void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_read16	phy.h	/^static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_phy_read32	phy.h	/^static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_phy_read32_mask	phy.h	/^static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_read8	phy.h	/^static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_phy_read_rf	phy.c	/^EXPORT_SYMBOL(rtw89_phy_read_rf);$/;"	v
rtw89_phy_read_rf	phy.c	/^u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	f
rtw89_phy_read_txpwr_byrate	phy.c	/^s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_read_txpwr_limit	phy.c	/^s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_read_txpwr_limit_ru	phy.c	/^static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_reg3_tbl	phy.h	/^struct rtw89_phy_reg3_tbl {$/;"	s
rtw89_phy_sel_headline	phy.c	/^static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_phy_set_bss_color	phy.c	/^void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif)$/;"	f
rtw89_phy_set_phy_regs	phy.c	/^void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,$/;"	f
rtw89_phy_stat	core.h	/^struct rtw89_phy_stat {$/;"	s
rtw89_phy_stat_init	phy.c	/^static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_stat_rssi_update	phy.c	/^static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_stat_rssi_update_iter	phy.c	/^static void rtw89_phy_stat_rssi_update_iter(void *data,$/;"	f	file:
rtw89_phy_stat_thermal_update	phy.c	/^static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_phy_stat_track	phy.c	/^void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)$/;"	f
rtw89_phy_status_ie_type	txrx.h	/^enum rtw89_phy_status_ie_type {$/;"	g
rtw89_phy_table	core.h	/^struct rtw89_phy_table {$/;"	s
rtw89_phy_write16	phy.h	/^static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write32	phy.h	/^static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write32_clr	phy.h	/^static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write32_idx	phy.c	/^void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,$/;"	f
rtw89_phy_write32_mask	phy.h	/^static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write32_set	phy.h	/^static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write8	phy.h	/^static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write_reg3_tbl	phy.c	/^void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,$/;"	f
rtw89_phy_write_rf	phy.c	/^EXPORT_SYMBOL(rtw89_phy_write_rf);$/;"	v
rtw89_phy_write_rf	phy.c	/^bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	f
rtw89_pkt_stat	core.h	/^struct rtw89_pkt_stat {$/;"	s
rtw89_ple_quota	core.h	/^struct rtw89_ple_quota {$/;"	s
rtw89_pm_ops	pci.c	/^EXPORT_SYMBOL(rtw89_pm_ops);$/;"	v
rtw89_port	core.h	/^enum rtw89_port {$/;"	g
rtw89_port_reg	core.h	/^struct rtw89_port_reg {$/;"	s
rtw89_power_trim_info	core.h	/^struct rtw89_power_trim_info {$/;"	s
rtw89_ppdu_sts_info	core.h	/^struct rtw89_ppdu_sts_info {$/;"	s
rtw89_print_sar	sar.c	/^void rtw89_print_sar(struct seq_file *m, struct rtw89_dev *rtwdev)$/;"	f
rtw89_ps_mode	core.h	/^enum rtw89_ps_mode {$/;"	g
rtw89_pwr_cfg	mac.h	/^struct rtw89_pwr_cfg {$/;"	s
rtw89_qta_mode	core.h	/^enum rtw89_qta_mode {$/;"	g
rtw89_query_sar	sar.c	/^s8 rtw89_query_sar(struct rtw89_dev *rtwdev)$/;"	f
rtw89_query_sar_config_common	sar.c	/^static int rtw89_query_sar_config_common(struct rtw89_dev *rtwdev, s32 *cfg)$/;"	f	file:
rtw89_ra_info	core.h	/^struct rtw89_ra_info {$/;"	s
rtw89_ra_mask_he_rates	phy.c	/^rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,$/;"	v	file:
rtw89_ra_mask_ht_rates	phy.c	/^rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,$/;"	v	file:
rtw89_ra_mask_info_update	mac80211.c	/^static void rtw89_ra_mask_info_update(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_ra_mask_info_update_iter	mac80211.c	/^static void rtw89_ra_mask_info_update_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_ra_mask_vht_rates	phy.c	/^rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,$/;"	v	file:
rtw89_ra_mode	core.h	/^enum rtw89_ra_mode {$/;"	g
rtw89_ra_report	core.h	/^struct rtw89_ra_report {$/;"	s
rtw89_ra_report_mode	core.h	/^enum rtw89_ra_report_mode {$/;"	g
rtw89_ra_report_to_bitrate	core.c	/^u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate)$/;"	f
rtw89_rate_desc	core.h	/^struct rtw89_rate_desc {$/;"	s
rtw89_rate_max	core.h	/^enum rtw89_rate_max {$/;"	g
rtw89_rate_section	core.h	/^enum rtw89_rate_section {$/;"	g
rtw89_read16	core.h	/^static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_read16_mask	core.h	/^rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)$/;"	f
rtw89_read16_mdio	pci.c	/^rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val)$/;"	f	file:
rtw89_read32	core.h	/^static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_read32_mask	core.h	/^rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)$/;"	f
rtw89_read32_port_mask	mac.h	/^rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_read8	core.h	/^static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)$/;"	f
rtw89_read8_mask	core.h	/^rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)$/;"	f
rtw89_read_chip_ver	core.c	/^static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_read_rf	core.h	/^rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	f
rtw89_reg2_def	core.h	/^struct rtw89_reg2_def {$/;"	s
rtw89_reg3_def	core.h	/^struct rtw89_reg3_def {$/;"	s
rtw89_reg5_def	core.h	/^struct rtw89_reg5_def {$/;"	s
rtw89_reg_def	core.h	/^struct rtw89_reg_def {$/;"	s
rtw89_regd_find_reg_by_name	regd.c	/^static const struct rtw89_regulatory *rtw89_regd_find_reg_by_name(char *alpha2)$/;"	f	file:
rtw89_regd_get	core.h	/^static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)$/;"	f
rtw89_regd_init	regd.c	/^int rtw89_regd_init(struct rtw89_dev *rtwdev,$/;"	f
rtw89_regd_is_ww	regd.c	/^static bool rtw89_regd_is_ww(const struct rtw89_regulatory *regd)$/;"	f	file:
rtw89_regd_map	regd.c	/^static const struct rtw89_regulatory rtw89_regd_map[] = {$/;"	v	typeref:struct:rtw89_regulatory	file:
rtw89_regd_notifier	regd.c	/^void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request)$/;"	f
rtw89_regd_notifier_apply	regd.c	/^static void rtw89_regd_notifier_apply(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_regulation_type	core.h	/^enum rtw89_regulation_type {$/;"	g
rtw89_regulatory	core.h	/^struct rtw89_regulatory {$/;"	s
rtw89_rf_path	core.h	/^enum rtw89_rf_path {$/;"	g
rtw89_rf_path_bit	core.h	/^enum rtw89_rf_path_bit {$/;"	g
rtw89_rfk_flag	rtw8852a_rfk_table.h	/^enum rtw89_rfk_flag {$/;"	g
rtw89_rfk_parser	rtw8852a_rfk.c	/^rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)$/;"	f	file:
rtw89_rfk_parser_by_cond	rtw8852a_rfk.c	66;"	d	file:
rtw89_rfk_tbl	rtw8852a_rfk_table.h	/^struct rtw89_rfk_tbl {$/;"	s
rtw89_rpwm_req_pwr_state	mac.h	/^enum rtw89_rpwm_req_pwr_state {$/;"	g
rtw89_rs_idx_max	phy.c	/^const u8 rtw89_rs_idx_max[] = {$/;"	v
rtw89_rs_nss_max	phy.c	/^const u8 rtw89_rs_nss_max[] = {$/;"	v
rtw89_ru_bandwidth	core.h	/^enum rtw89_ru_bandwidth {$/;"	g
rtw89_rx_channel	txrx.h	/^enum rtw89_rx_channel {$/;"	g
rtw89_rx_desc_info	core.h	/^struct rtw89_rx_desc_info {$/;"	s
rtw89_rx_frame_type	core.h	/^enum rtw89_rx_frame_type {$/;"	g
rtw89_rx_phy_ppdu	core.h	/^struct rtw89_rx_phy_ppdu {$/;"	s
rtw89_rx_rate_cnt_info	debug.c	/^static const struct rtw89_rx_rate_cnt_info {$/;"	s	file:
rtw89_rx_rate_cnt_infos	debug.c	/^} rtw89_rx_rate_cnt_infos[] = {$/;"	v	typeref:struct:rtw89_rx_rate_cnt_info	file:
rtw89_rxdesc_long	core.h	/^struct rtw89_rxdesc_long {$/;"	s
rtw89_rxdesc_short	core.h	/^struct rtw89_rxdesc_short {$/;"	s
rtw89_rxdesc_to_nl_he_gi	core.c	/^static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_sar_capa	sar.c	/^const struct cfg80211_sar_capa rtw89_sar_capa = {$/;"	v	typeref:struct:cfg80211_sar_capa
rtw89_sar_cfg_common	core.h	/^struct rtw89_sar_cfg_common {$/;"	s
rtw89_sar_handler	sar.h	/^struct rtw89_sar_handler {$/;"	s
rtw89_sar_handlers	sar.c	/^struct rtw89_sar_handler rtw89_sar_handlers[RTW89_SAR_SOURCE_NR] = {$/;"	v	typeref:struct:rtw89_sar_handler	file:
rtw89_sar_info	core.h	/^struct rtw89_sar_info {$/;"	s
rtw89_sar_set_src	sar.c	29;"	d	file:
rtw89_sar_sources	core.h	/^enum rtw89_sar_sources {$/;"	g
rtw89_sband_2ghz	core.c	/^static struct ieee80211_supported_band rtw89_sband_2ghz = {$/;"	v	typeref:struct:ieee80211_supported_band	file:
rtw89_sband_5ghz	core.c	/^static struct ieee80211_supported_band rtw89_sband_5ghz = {$/;"	v	typeref:struct:ieee80211_supported_band	file:
rtw89_sc_offset	core.h	/^enum rtw89_sc_offset {$/;"	g
rtw89_sch_tx_sel	core.h	/^enum rtw89_sch_tx_sel {$/;"	g
rtw89_sec_cam_entry	core.h	/^struct rtw89_sec_cam_entry {$/;"	s
rtw89_sec_key_type	core.h	/^enum rtw89_sec_key_type {$/;"	g
rtw89_self_role	core.h	/^enum rtw89_self_role {$/;"	g
rtw89_ser	core.h	/^struct rtw89_ser {$/;"	s
rtw89_ser_alarm_work	ser.c	/^static void rtw89_ser_alarm_work(struct work_struct *work)$/;"	f	file:
rtw89_ser_deinit	ser.c	/^int rtw89_ser_deinit(struct rtw89_dev *rtwdev)$/;"	f
rtw89_ser_hdl_work	ser.c	/^static void rtw89_ser_hdl_work(struct work_struct *work)$/;"	f	file:
rtw89_ser_init	ser.c	/^int rtw89_ser_init(struct rtw89_dev *rtwdev)$/;"	f
rtw89_ser_notify	ser.c	/^EXPORT_SYMBOL(rtw89_ser_notify);$/;"	v
rtw89_ser_notify	ser.c	/^int rtw89_ser_notify(struct rtw89_dev *rtwdev, u32 err)$/;"	f
rtw89_ser_rcvy_step	core.h	/^enum rtw89_ser_rcvy_step {$/;"	g
rtw89_ser_recfg_done	ser.c	/^void rtw89_ser_recfg_done(struct rtw89_dev *rtwdev)$/;"	f
rtw89_set_channel	core.c	/^void rtw89_set_channel(struct rtw89_dev *rtwdev)$/;"	f
rtw89_set_coex_ctrl_lps	ps.c	/^void rtw89_set_coex_ctrl_lps(struct rtw89_dev *rtwdev, bool btc_ctrl)$/;"	f
rtw89_set_hw_sch_tx_en	mac.c	/^static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,$/;"	f	file:
rtw89_set_macid_pause	mac.c	/^static int rtw89_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)$/;"	f	file:
rtw89_skb_put_rx_data	pci.c	/^rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls,$/;"	f	file:
rtw89_sta	core.h	/^struct rtw89_sta {$/;"	s
rtw89_sta_has_beamformer_cap	core.h	/^static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)$/;"	f
rtw89_sta_info_get_iter	debug.c	/^static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_station_mode_sta_assoc	mac80211.c	/^static void rtw89_station_mode_sta_assoc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_subband	core.h	/^enum rtw89_subband {$/;"	g
rtw89_switch_efuse_bank	efuse.c	/^static int rtw89_switch_efuse_bank(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_tfc_dir	core.h	/^enum rtw89_tfc_dir {$/;"	g
rtw89_tfc_lv	core.h	/^enum rtw89_tfc_lv {$/;"	g
rtw89_track_work	core.c	/^static void rtw89_track_work(struct work_struct *work)$/;"	f	file:
rtw89_traffic_stats	core.h	/^struct rtw89_traffic_stats {$/;"	s
rtw89_traffic_stats_accu	core.c	/^static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_traffic_stats_calc	core.c	/^static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,$/;"	f	file:
rtw89_traffic_stats_init	core.c	/^void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,$/;"	f
rtw89_traffic_stats_track	core.c	/^static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_tssi_info	core.h	/^struct rtw89_tssi_info {$/;"	s
rtw89_tx_channel	txrx.h	/^enum rtw89_tx_channel {$/;"	g
rtw89_tx_desc_info	core.h	/^struct rtw89_tx_desc_info {$/;"	s
rtw89_tx_qsel	txrx.h	/^enum rtw89_tx_qsel {$/;"	g
rtw89_tx_time_iter	coex.c	/^static void rtw89_tx_time_iter(void *data, struct ieee80211_sta *sta)$/;"	f	file:
rtw89_txpwr_byrate	core.h	/^struct rtw89_txpwr_byrate {$/;"	s
rtw89_txpwr_byrate_cfg	phy.h	/^struct rtw89_txpwr_byrate_cfg {$/;"	s
rtw89_txpwr_limit	core.h	/^struct rtw89_txpwr_limit {$/;"	s
rtw89_txpwr_limit_ru	core.h	/^struct rtw89_txpwr_limit_ru {$/;"	s
rtw89_txpwr_sar_to_mac	sar.c	/^static s8 rtw89_txpwr_sar_to_mac(struct rtw89_dev *rtwdev, u8 fct, s32 cfg)$/;"	f	file:
rtw89_txpwr_table	core.h	/^struct rtw89_txpwr_table {$/;"	s
rtw89_txpwr_track_cfg	phy.h	/^struct rtw89_txpwr_track_cfg {$/;"	s
rtw89_txq	core.h	/^struct rtw89_txq {$/;"	s
rtw89_txq_flags	core.h	/^enum rtw89_txq_flags {$/;"	g
rtw89_txq_to_txq	core.h	/^static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)$/;"	f
rtw89_txtime_data	coex.c	/^struct rtw89_txtime_data {$/;"	s	file:
rtw89_txwd_body	core.h	/^struct rtw89_txwd_body {$/;"	s
rtw89_txwd_info	core.h	/^struct rtw89_txwd_info {$/;"	s
rtw89_unload_firmware	fw.c	/^void rtw89_unload_firmware(struct rtw89_dev *rtwdev)$/;"	f
rtw89_upd_mode	core.h	/^enum rtw89_upd_mode {$/;"	g
rtw89_update_ps_mode	core.c	/^static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)$/;"	f	file:
rtw89_vif	core.h	/^struct rtw89_vif {$/;"	s
rtw89_vif_enter_lps	core.c	/^static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f	file:
rtw89_vif_rx_stats_iter	core.c	/^static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,$/;"	f	file:
rtw89_vif_rx_stats_iter_data	core.c	/^struct rtw89_vif_rx_stats_iter_data {$/;"	s	file:
rtw89_vif_type_mapping	core.c	/^void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc)$/;"	f
rtw89_wait_firmware_completion	fw.c	/^int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev)$/;"	f
rtw89_warn	debug.h	46;"	d
rtw89_wde_quota	core.h	/^struct rtw89_wde_quota {$/;"	s
rtw89_wifi_role	core.h	/^enum rtw89_wifi_role {$/;"	g
rtw89_write16	core.h	/^static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)$/;"	f
rtw89_write16_clr	core.h	/^rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)$/;"	f
rtw89_write16_mask	core.h	/^rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)$/;"	f
rtw89_write16_mdio	pci.c	/^rtw89_write16_mdio(struct rtw89_dev *rtwdev, u8 addr, u16 data, u8 speed)$/;"	f	file:
rtw89_write16_mdio_clr	pci.c	/^static int rtw89_write16_mdio_clr(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed)$/;"	f	file:
rtw89_write16_mdio_set	pci.c	/^static int rtw89_write16_mdio_set(struct rtw89_dev *rtwdev, u8 addr, u16 mask, u8 speed)$/;"	f	file:
rtw89_write16_port_clr	mac.h	/^rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_write16_port_mask	mac.h	/^rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_write16_set	core.h	/^rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)$/;"	f
rtw89_write32	core.h	/^static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)$/;"	f
rtw89_write32_clr	core.h	/^rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)$/;"	f
rtw89_write32_mask	core.h	/^rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)$/;"	f
rtw89_write32_port	mac.h	/^rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base,$/;"	f
rtw89_write32_port_clr	mac.h	/^rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_write32_port_mask	mac.h	/^rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_write32_port_set	mac.h	/^rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,$/;"	f
rtw89_write32_set	core.h	/^rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)$/;"	f
rtw89_write8	core.h	/^static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)$/;"	f
rtw89_write8_clr	core.h	/^rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)$/;"	f
rtw89_write8_mask	core.h	/^rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)$/;"	f
rtw89_write8_set	core.h	/^rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)$/;"	f
rtw89_write_rf	core.h	/^rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	f
rtw89_ww_regd	regd.c	/^static const struct rtw89_regulatory rtw89_ww_regd =$/;"	v	typeref:struct:rtw89_regulatory	file:
rtw_btc_btf_reg_type	core.h	/^enum rtw_btc_btf_reg_type {$/;"	g
rtw_hfc_preccfg_pcie	mac.c	/^const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = {$/;"	v	typeref:struct:rtw89_hfc_prec_cfg
rtw_port_base	mac.c	/^static const struct rtw89_port_reg rtw_port_base = {$/;"	v	typeref:struct:rtw89_port_reg	file:
rtwdev	coex.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_btc_wl_sta_iter_data	typeref:struct:rtw89_btc_wl_sta_iter_data::rtw89_dev	file:
rtwdev	coex.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_txtime_data	typeref:struct:rtw89_txtime_data::rtw89_dev	file:
rtwdev	core.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_core_iter_rx_status	typeref:struct:rtw89_core_iter_rx_status::rtw89_dev	file:
rtwdev	core.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_vif_rx_stats_iter_data	typeref:struct:rtw89_vif_rx_stats_iter_data::rtw89_dev	file:
rtwdev	core.h	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_fw_info	typeref:struct:rtw89_fw_info::rtw89_dev
rtwdev	debug.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_debugfs_priv	typeref:struct:rtw89_debugfs_priv::rtw89_dev	file:
rtwdev	mac.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_mac_bf_monitor_iter_data	typeref:struct:rtw89_mac_bf_monitor_iter_data::rtw89_dev	file:
rtwdev	mac80211.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_iter_bitrate_mask_data	typeref:struct:rtw89_iter_bitrate_mask_data::rtw89_dev	file:
rtwdev	phy.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_phy_iter_ra_data	typeref:struct:rtw89_phy_iter_ra_data::rtw89_dev	file:
rtwdev	phy.c	/^	struct rtw89_dev *rtwdev;$/;"	m	struct:rtw89_phy_iter_rssi_data	typeref:struct:rtw89_phy_iter_rssi_data::rtw89_dev	file:
rtwsta_to_sta	core.h	/^static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)$/;"	f
rtwvif	core.h	/^	struct rtw89_vif *rtwvif;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::rtw89_vif
rtwvif_to_vif	core.h	/^static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)$/;"	f
rtwvifs_list	core.h	/^	struct list_head rtwvifs_list;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::list_head
ru106	core.h	/^	s8 ru106[RTW89_RU_SEC_NUM];$/;"	m	struct:rtw89_txpwr_limit_ru
ru26	core.h	/^	s8 ru26[RTW89_RU_SEC_NUM];$/;"	m	struct:rtw89_txpwr_limit_ru
ru52	core.h	/^	s8 ru52[RTW89_RU_SEC_NUM];$/;"	m	struct:rtw89_txpwr_limit_ru
run	core.h	/^	u32 run: 1;$/;"	m	struct:rtw89_btc_bt_rfk_info
run_action	core.h	/^	u8 run_action;$/;"	m	struct:rtw89_btc_dm
run_patch_code	core.h	/^	u32 run_patch_code: 1;$/;"	m	struct:rtw89_btc_bt_info
run_reason	core.h	/^	u8 run_reason;$/;"	m	struct:rtw89_btc_dm
running	pci.h	/^	bool running;$/;"	m	struct:rtw89_pci
rx	mac.h	/^	u8 rx;$/;"	m	struct:rtw89_mac_ax_plt
rx_avg_len	core.h	/^	u32 rx_avg_len;$/;"	m	struct:rtw89_traffic_stats
rx_cnt	core.h	/^	u32 rx_cnt;$/;"	m	struct:rtw89_btc_rpt_cmn_info
rx_cnt	core.h	/^	u64 rx_cnt;$/;"	m	struct:rtw89_traffic_stats
rx_diversity	rtw8852a.h	/^	u8 rx_diversity:2;$/;"	m	struct:rtw8852a_efuse
rx_ewma_tp	core.h	/^	struct ewma_tp rx_ewma_tp;$/;"	m	struct:rtw89_traffic_stats	typeref:struct:rtw89_traffic_stats::ewma_tp
rx_fltr	core.h	/^	u32 rx_fltr;$/;"	m	struct:rtw89_hal
rx_fltr_init	mac.c	/^static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
rx_gain_freerun	core.h	/^	u32 rx_gain_freerun;$/;"	m	struct:rtw89_btc_rf_para
rx_gain_perpkt	core.h	/^	u32 rx_gain_perpkt;$/;"	m	struct:rtw89_btc_rf_para
rx_hw_rate	core.h	/^	u16 rx_hw_rate;$/;"	m	struct:rtw89_sta
rx_len	core.h	/^	u32 rx_len;$/;"	m	struct:rtw89_btc_rpt_cmn_info
rx_lvl	core.h	/^	u16 rx_lvl;$/;"	m	struct:rtw89_btc_wl_active_role
rx_nss	core.h	/^	u8 rx_nss;$/;"	m	struct:rtw89_chip_info
rx_nss	core.h	/^	u8 rx_nss;$/;"	m	struct:rtw89_hal
rx_nss	fw.h	/^	u32 rx_nss:8;$/;"	m	struct:rtw89_c2h_phy_cap
rx_pl_id	core.h	/^	u8 rx_pl_id;$/;"	m	struct:rtw89_rx_desc_info
rx_queue	core.h	/^	struct sk_buff_head rx_queue[RTW89_PHY_MAX];$/;"	m	struct:rtw89_ppdu_sts_info	typeref:struct:rtw89_ppdu_sts_info::sk_buff_head
rx_rate	core.h	/^	u16 rx_rate;$/;"	m	struct:rtw89_btc_wl_active_role
rx_rate	core.h	/^	u16 rx_rate;$/;"	m	struct:rtw89_traffic_stats
rx_rate_cnt	core.h	/^	u32 rx_rate_cnt[RTW89_HW_RATE_NR];$/;"	m	struct:rtw89_pkt_stat
rx_rate_drop_cnt	core.h	/^	u32 rx_rate_drop_cnt;$/;"	m	struct:rtw89_btc_wl_link_info
rx_rings	pci.h	/^	struct rtw89_pci_rx_ring rx_rings[RTW89_RXCH_NUM];$/;"	m	struct:rtw89_pci	typeref:struct:rtw89_pci::rtw89_pci_rx_ring
rx_status	core.c	/^	struct ieee80211_rx_status *rx_status;$/;"	m	struct:rtw89_core_iter_rx_status	typeref:struct:rtw89_core_iter_rx_status::ieee80211_rx_status	file:
rx_status	core.h	/^	struct ieee80211_rx_status rx_status;$/;"	m	struct:rtw89_sta	typeref:struct:rtw89_sta::ieee80211_rx_status
rx_tfc_lv	core.h	/^	enum rtw89_tfc_lv rx_tfc_lv;$/;"	m	struct:rtw89_traffic_stats	typeref:enum:rtw89_traffic_stats::rtw89_tfc_lv
rx_throughput	core.h	/^	u32 rx_throughput;$/;"	m	struct:rtw89_traffic_stats
rx_throughput_raw	core.h	/^	u32 rx_throughput_raw;$/;"	m	struct:rtw89_traffic_stats
rx_unicast	core.h	/^	u64 rx_unicast;$/;"	m	struct:rtw89_traffic_stats
rxb_idx	core.h	/^	u8 rxb_idx;$/;"	m	struct:rtw89_agc_gaincode_set
rxflctrl	core.h	/^	u8 rxflctrl;$/;"	m	struct:rtw89_btc_fbtc_tdma
rxsc_160	core.h	/^	u8 rxsc_160;$/;"	m	struct:rtw89_phy_ch_info
rxsc_20	core.h	/^	u8 rxsc_20;$/;"	m	struct:rtw89_phy_ch_info
rxsc_40	core.h	/^	u8 rxsc_40;$/;"	m	struct:rtw89_phy_ch_info
rxsc_80	core.h	/^	u8 rxsc_80;$/;"	m	struct:rtw89_phy_ch_info
rxsc_l	core.h	/^	u8 rxsc_l;$/;"	m	struct:rtw89_phy_ch_info
s_def	coex.c	/^static const struct rtw89_btc_fbtc_slot s_def[] = {$/;"	v	typeref:struct:rtw89_btc_fbtc_slot	file:
sar	core.h	/^	struct rtw89_sar_info sar;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_sar_info
scam_num	core.h	/^	u8 scam_num;$/;"	m	struct:rtw89_chip_info
scan	core.h	/^	u32 scan: 1;$/;"	m	struct:rtw89_btc_wl_smap
scan	core.h	/^	u8 scan[6];$/;"	m	struct:rtw89_btc_fbtc_btscan
scan_band	core.h	/^	u8 scan_band[RTW89_PHY_MAX]; \/* scan band in  each phy *\/$/;"	m	struct:rtw89_btc_wl_dbcc_info
scan_info	core.h	/^	struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_bt_scan_info
scan_info	core.h	/^	struct rtw89_btc_wl_scan_info scan_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_scan_info
scanning	core.h	/^	bool scanning;$/;"	m	struct:rtw89_dev
scbd	core.h	/^	u32 scbd;$/;"	m	struct:rtw89_btc_bt_info
scbd	core.h	/^	u32 scbd;$/;"	m	struct:rtw89_btc_wl_info
scbd	core.h	/^	u8 scbd;$/;"	m	struct:rtw89_chip_info
scheduler_init	mac.c	/^static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
sco_busy	coex.c	/^	u8 sco_busy: 1;$/;"	m	struct:btc_btinfo_lb2	file:
sco_busy	core.h	/^	u32 sco_busy: 1;$/;"	m	struct:rtw89_btc_bt_smap
sdagc_config	phy.c	/^static const struct rtw89_reg_def sdagc_config[4] = {$/;"	v	typeref:struct:rtw89_reg_def	file:
sec_cam_id	core.h	/^	u8 sec_cam_id;$/;"	m	struct:rtw89_rx_desc_info
sec_cam_idx	core.h	/^	u8 sec_cam_idx;$/;"	m	struct:rtw89_sec_cam_entry
sec_cam_idx	core.h	/^	u8 sec_cam_idx;$/;"	m	struct:rtw89_tx_desc_info
sec_ctrl_efuse_size	core.h	/^	u8 sec_ctrl_efuse_size;$/;"	m	struct:rtw89_chip_info
sec_en	core.h	/^	bool sec_en;$/;"	m	struct:rtw89_tx_desc_info
sec_eng_init	mac.c	/^static int sec_eng_init(struct rtw89_dev *rtwdev)$/;"	f	file:
sec_ent	core.h	/^	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];$/;"	m	struct:rtw89_addr_cam_entry
sec_ent_keyid	core.h	/^	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];$/;"	m	struct:rtw89_addr_cam_entry
sec_ent_mode	core.h	/^	u8 sec_ent_mode;$/;"	m	struct:rtw89_addr_cam_entry
sec_entries	core.h	/^	struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];$/;"	m	struct:rtw89_addr_cam_entry	typeref:struct:rtw89_addr_cam_entry::rtw89_sec_cam_entry
sec_type	core.h	/^	u8 sec_type;$/;"	m	struct:rtw89_tx_desc_info
section_info	fw.h	/^	struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];$/;"	m	struct:rtw89_fw_bin_info	typeref:struct:rtw89_fw_bin_info::rtw89_fw_hdr_section_info
section_num	fw.h	/^	u8 section_num;$/;"	m	struct:rtw89_fw_bin_info
sel	debug.c	/^			u8 sel;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon5	file:
sel_addr	mac.h	/^	u32 sel_addr;$/;"	m	struct:rtw89_mac_dbg_port_info
sel_byte	mac.h	/^	u8 sel_byte;$/;"	m	struct:rtw89_mac_dbg_port_info
sel_msk	mac.h	/^	u32 sel_msk;$/;"	m	struct:rtw89_mac_dbg_port_info
self_role	core.h	/^	u8 self_role;$/;"	m	struct:rtw89_vif
seq	core.h	/^	u16 seq;$/;"	m	struct:rtw89_rx_desc_info
seq	core.h	/^	u16 seq;$/;"	m	struct:rtw89_tx_desc_info
seq	fw.h	/^	u32 seq:4;$/;"	m	struct:rtw89_c2h_phy_cap
seq	pci.h	/^	u32 seq;$/;"	m	struct:rtw89_pci_tx_wd
seq0	pci.h	/^	__le16 seq0;$/;"	m	struct:rtw89_pci_tx_wp_info
seq1	pci.h	/^	__le16 seq1;$/;"	m	struct:rtw89_pci_tx_wp_info
seq2	pci.h	/^	__le16 seq2;$/;"	m	struct:rtw89_pci_tx_wp_info
seq3	pci.h	/^	__le16 seq3;$/;"	m	struct:rtw89_pci_tx_wp_info
seq_num	fw.h	/^	u8 seq_num:4;$/;"	m	struct:rtw89_h2creg_sch_tx_en
seq_print_segment	coex.c	/^void seq_print_segment(struct seq_file *m, const char *prefix, u16 *data,$/;"	f	file:
ser	core.h	/^	struct rtw89_ser ser;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_ser
ser_alarm_work	core.h	/^	struct delayed_work ser_alarm_work;$/;"	m	struct:rtw89_ser	typeref:struct:rtw89_ser::delayed_work
ser_del_alarm	ser.c	/^static void ser_del_alarm(struct rtw89_ser *ser)$/;"	f	file:
ser_do_hci_st_hdl	ser.c	/^static void ser_do_hci_st_hdl(struct rtw89_ser *ser, u8 evt)$/;"	f	file:
ser_ev_name	ser.c	/^static char *ser_ev_name(struct rtw89_ser *ser, u8 event)$/;"	f	file:
ser_ev_tbl	ser.c	/^static struct event_ent ser_ev_tbl[] = {$/;"	v	typeref:struct:event_ent	file:
ser_evt	ser.c	/^enum ser_evt {$/;"	g	file:
ser_hdl_work	core.h	/^	struct work_struct ser_hdl_work;$/;"	m	struct:rtw89_ser	typeref:struct:rtw89_ser::work_struct
ser_idle_st_hdl	ser.c	/^static void ser_idle_st_hdl(struct rtw89_ser *ser, u8 evt)$/;"	f	file:
ser_l2_reset_st_hdl	ser.c	/^static void ser_l2_reset_st_hdl(struct rtw89_ser *ser, u8 evt)$/;"	f	file:
ser_msg	ser.c	/^struct ser_msg {$/;"	s	file:
ser_reset_mac_binding	ser.c	/^static void ser_reset_mac_binding(struct rtw89_dev *rtwdev)$/;"	f	file:
ser_reset_trx_st_hdl	ser.c	/^static void ser_reset_trx_st_hdl(struct rtw89_ser *ser, u8 evt)$/;"	f	file:
ser_reset_vif	ser.c	/^static void ser_reset_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)$/;"	f	file:
ser_send_msg	ser.c	/^static int ser_send_msg(struct rtw89_ser *ser, u8 event)$/;"	f	file:
ser_set_alarm	ser.c	/^static void ser_set_alarm(struct rtw89_ser *ser, u32 ms, u8 event)$/;"	f	file:
ser_st_name	ser.c	/^static char *ser_st_name(struct rtw89_ser *ser)$/;"	f	file:
ser_st_tbl	ser.c	/^static struct state_ent ser_st_tbl[] = {$/;"	v	typeref:struct:state_ent	file:
ser_state	ser.c	/^enum ser_state {$/;"	g	file:
ser_state_goto	ser.c	/^static void ser_state_goto(struct rtw89_ser *ser, u8 new_state)$/;"	f	file:
ser_state_run	ser.c	/^static void ser_state_run(struct rtw89_ser *ser, u8 evt)$/;"	f	file:
set	core.h	/^	bool set[RTW89_SUBBAND_NR];$/;"	m	struct:rtw89_sar_cfg_common
set_ant_path	core.h	/^	u32 set_ant_path;$/;"	m	struct:rtw89_btc_dm
set_channel	core.h	/^	void (*set_channel)(struct rtw89_dev *rtwdev,$/;"	m	struct:rtw89_chip_ops
set_channel_help	core.h	/^	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,$/;"	m	struct:rtw89_chip_ops
set_host_rpr	mac.c	/^static int set_host_rpr(struct rtw89_dev *rtwdev)$/;"	f	file:
set_txpwr	core.h	/^	void (*set_txpwr)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
set_txpwr_ctrl	core.h	/^	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_chip_ops
set_txpwr_ul_tb_offset	core.h	/^	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,$/;"	m	struct:rtw89_chip_ops
shared_ant	rtw8852a.h	/^	u8 shared_ant:1;$/;"	m	struct:rtw8852a_efuse
shf	phy.h	/^	u8 shf;$/;"	m	struct:rtw89_txpwr_byrate_cfg
shift	core.h	/^	u8 shift;$/;"	m	struct:rtw89_rx_desc_info
shift	fw.h	/^	__le32 shift;$/;"	m	struct:rtw89_mfw_info
sid	coex.c	/^	u8 sid; \/* slot id *\/$/;"	m	struct:btc_fbtc_1slot	file:
sig	fw.h	/^	u8 sig;	\/* RTW89_MFW_SIG *\/$/;"	m	struct:rtw89_mfw_hdr
single_pos	core.h	/^	u8 single_pos: 1;\/* Single antenna at S0 or S1 *\/$/;"	m	struct:rtw89_btc_ant_info
sink	core.h	/^	u8 sink: 1;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
size	core.h	/^	u32 size;$/;"	m	struct:rtw89_fw_suit
size	core.h	/^	u32 size;$/;"	m	struct:rtw89_txpwr_table
size	debug.c	/^	u8 size;$/;"	m	struct:txpwr_map	file:
size	fw.h	/^	__le32 size;$/;"	m	struct:rtw89_mfw_info
size	phy.h	/^	int size;$/;"	m	struct:rtw89_phy_reg3_tbl
size	phy.h	/^	u8 size;$/;"	m	struct:rtw89_phy_dig_gain_cfg
size	rtw8852a_rfk_table.h	/^	u32 size;$/;"	m	struct:rtw89_rfk_tbl
skb	core.c	/^	struct sk_buff *skb;$/;"	m	struct:rtw89_vif_rx_stats_iter_data	typeref:struct:rtw89_vif_rx_stats_iter_data::sk_buff	file:
skb	core.h	/^	struct sk_buff *skb;$/;"	m	struct:rtw89_core_tx_request	typeref:struct:rtw89_core_tx_request::sk_buff
skip_cnt	coex.c	/^	u32 skip_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
skip_cnt	core.h	/^	__le32 skip_cnt;$/;"	m	struct:rtw89_btc_fbtc_cysta
slave	coex.c	/^	u8 slave: 1;$/;"	m	struct:btc_btinfo_hb2	file:
slave_role	core.h	/^	u32 slave_role: 1;$/;"	m	struct:rtw89_btc_bt_link_info
slot	coex.c	/^	struct rtw89_btc_fbtc_slot slot;$/;"	m	struct:btc_fbtc_1slot	typeref:struct:btc_fbtc_1slot::rtw89_btc_fbtc_slot	file:
slot	core.h	/^	struct rtw89_btc_fbtc_slot slot[CXST_MAX];$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_fbtc_slot
slot	core.h	/^	struct rtw89_btc_fbtc_slot slot[CXST_MAX];$/;"	m	struct:rtw89_btc_fbtc_slots	typeref:struct:rtw89_btc_fbtc_slots::rtw89_btc_fbtc_slot
slot_cnt	coex.c	/^	u32 slot_cnt[CXST_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
slot_cnt	core.h	/^	__le32 slot_cnt[CXST_MAX]; \/* slot count *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
slot_dur	core.h	/^	u16 slot_dur[CXST_MAX];$/;"	m	struct:rtw89_btc_dm
slot_info	core.h	/^	u32 slot_info: 2;$/;"	m	struct:rtw89_btc_bt_hid_desc
slot_now	core.h	/^	struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_fbtc_slot
sma	core.h	/^	u8 sma[ETH_ALEN];$/;"	m	struct:rtw89_addr_cam_entry
spatial_reuse_init	mac.c	/^static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
spp_mode	core.h	/^	u8 spp_mode : 1;$/;"	m	struct:rtw89_sec_cam_entry
sr_en	core.h	/^	bool sr_en;$/;"	m	struct:rtw89_rx_desc_info
src	core.h	/^	enum rtw89_sar_sources src;$/;"	m	struct:rtw89_sar_info	typeref:enum:rtw89_sar_info::rtw89_sar_sources
src_pid	mac.h	/^	u8 src_pid;$/;"	m	struct:rtw89_cpuio_ctrl
src_qid	mac.h	/^	u8 src_qid;$/;"	m	struct:rtw89_cpuio_ctrl
srt	mac.h	/^	u32 srt;$/;"	m	struct:rtw89_mac_dbg_port_info
srvd	core.h	/^	u32 srvd: 29;$/;"	m	struct:rtw89_btc_bool_sta_chg
ss_dbg	debug.c	/^			u8 ss_dbg:1;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon4	file:
ss_num	core.h	/^	u8 ss_num:3;$/;"	m	struct:rtw89_ra_info
st_func	ser.c	/^	void (*st_func)(struct rtw89_ser *ser, u8 event);$/;"	m	struct:state_ent	file:
st_tbl	core.h	/^	struct state_ent *st_tbl;$/;"	m	struct:rtw89_ser	typeref:struct:rtw89_ser::state_ent
sta	core.h	/^	struct ieee80211_sta *sta;$/;"	m	struct:rtw89_core_tx_request	typeref:struct:rtw89_core_tx_request::ieee80211_sta
sta_cfo_tolerance	core.h	/^	u32 sta_cfo_tolerance;$/;"	m	struct:rtw89_cfo_tracking_info
sta_list	core.h	/^			struct list_head sta_list;$/;"	m	struct:rtw89_vif::__anon11::__anon13	typeref:struct:rtw89_vif::__anon11::__anon13::list_head
sta_sch_init	mac.c	/^static int sta_sch_init(struct rtw89_dev *rtwdev)$/;"	f	file:
start	core.h	/^	int (*start)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
start	debug.c	/^			u32 start;$/;"	m	struct:rtw89_debugfs_priv::__anon1::__anon5	file:
start_idx	pci.h	/^	u8 start_idx;$/;"	m	struct:rtw89_pci_bd_ram
start_pktid	mac.h	/^	u16 start_pktid;$/;"	m	struct:rtw89_cpuio_ctrl
start_time	core.h	/^	u64 start_time;$/;"	m	struct:rtw89_env_monitor_info
stat	core.h	/^	struct rtw89_btc_statistic stat;$/;"	m	struct:rtw89_btc_wl_link_info	typeref:struct:rtw89_btc_wl_link_info::rtw89_btc_statistic
state	core.h	/^	u32 state: 2;$/;"	m	struct:rtw89_btc_wl_rfk_info
state	core.h	/^	u8 state;$/;"	m	struct:rtw89_ser
state	ser.c	/^	u8 state;$/;"	m	struct:state_ent	file:
state_ent	ser.c	/^struct state_ent {$/;"	s	file:
state_map	core.h	/^	u32 state_map;$/;"	m	struct:rtw89_btc_cx
station	core.h	/^	u16 station: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
stats	core.h	/^	struct rtw89_traffic_stats stats;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_traffic_stats
stats	core.h	/^	struct rtw89_traffic_stats stats;$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::rtw89_traffic_stats
status	core.h	/^	union rtw89_btc_bt_state_map status;$/;"	m	struct:rtw89_btc_bt_link_info	typeref:union:rtw89_btc_bt_link_info::rtw89_btc_bt_state_map
status	core.h	/^	union rtw89_btc_wl_state_map status;$/;"	m	struct:rtw89_btc_wl_info	typeref:union:rtw89_btc_wl_info::rtw89_btc_wl_state_map
stbc_cap	core.h	/^	u8 stbc_cap:1;$/;"	m	struct:rtw89_ra_info
step	core.h	/^	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];$/;"	m	struct:rtw89_btc_fbtc_steps	typeref:struct:rtw89_btc_fbtc_steps::rtw89_btc_fbtc_step
step	core.h	/^	u16 step[RTW89_BTC_DM_MAXSTEP];$/;"	m	struct:rtw89_btc_dm_step
step_ov	core.h	/^	bool step_ov;$/;"	m	struct:rtw89_btc_dm_step
step_pos	core.h	/^	u8 step_pos;$/;"	m	struct:rtw89_btc_dm_step
steps_to_str	coex.c	/^static const char *steps_to_str(u16 step)$/;"	f	file:
stop	core.h	/^	void (*stop)(struct rtw89_dev *rtwdev);$/;"	m	struct:rtw89_hci_ops
sub_idex	core.h	/^	u8 sub_idex;$/;"	m	struct:rtw89_fw_suit
sub_ver	core.h	/^	u8 sub_ver;$/;"	m	struct:rtw89_fw_suit
sut_pwr_level	core.h	/^	u8 sut_pwr_level[BTC_PROFILE_MAX];$/;"	m	struct:rtw89_btc_bt_link_info
sw_amsdu_max_size	core.h	/^	u32 sw_amsdu_max_size;$/;"	m	struct:rtw89_hal
sw_dec	core.h	/^	bool sw_dec;$/;"	m	struct:rtw89_rx_desc_info
switch_type	core.h	/^	u8 switch_type: 1;$/;"	m	struct:rtw89_btc_module
syn1to2	core.h	/^	u32 syn1to2;$/;"	m	struct:rtw89_iqk_info
t_def	coex.c	/^static const struct rtw89_btc_fbtc_tdma t_def[] = {$/;"	v	typeref:struct:rtw89_btc_fbtc_tdma	file:
table	phy.h	/^	const struct rtw89_reg_def *table;$/;"	m	struct:rtw89_phy_dig_gain_cfg	typeref:struct:rtw89_phy_dig_gain_cfg::rtw89_reg_def
tag	pci.h	/^	u16 tag; \/* range from 0x0001 ~ 0x1fff *\/$/;"	m	struct:rtw89_pci_tx_ring
tag	pci.h	/^	u32 fs:1, ls:1, tag:11, len:14;$/;"	m	struct:rtw89_pci_rx_info
target	mac.h	/^	u32 target;$/;"	m	struct:rtw89_mac_dle_dfi_ctrl
tavg_a2dp	coex.c	/^	u16 tavg_a2dp[CXT_FLCTRL_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tavg_a2dp	core.h	/^	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; \/* avg a2dp PSTDMA\/TDMA time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tavg_a2dpept	coex.c	/^	u16 tavg_a2dpept;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tavg_a2dpept	core.h	/^	__le16 tavg_a2dpept; \/* avg a2dp empty time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tavg_cycle	coex.c	/^	u16 tavg_cycle[CXT_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tavg_cycle	core.h	/^	__le16 tavg_cycle[CXT_MAX]; \/* avg wl\/bt cycle time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tavg_lk	coex.c	/^	u16 tavg_lk;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tavg_lk	core.h	/^	__le16 tavg_lk; \/* avg leak-slot time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tbl_num	coex.c	/^	u8 tbl_num;$/;"	m	struct:rtw89_btc_btf_set_slot_table	file:
tbl_num	core.h	/^	u8 tbl_num;$/;"	m	struct:rtw89_btc_fbtc_slots
tbtt_agg	core.h	/^	u32 tbtt_agg;$/;"	m	struct:rtw89_port_reg
tbtt_early	core.h	/^	u32 tbtt_early;$/;"	m	struct:rtw89_port_reg
tbtt_prohib	core.h	/^	u32 tbtt_prohib;$/;"	m	struct:rtw89_port_reg
tbtt_shift	core.h	/^	u32 tbtt_shift;$/;"	m	struct:rtw89_port_reg
tdma	core.h	/^	struct rtw89_btc_fbtc_tdma tdma;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_fbtc_tdma
tdma_no_sync	core.h	/^	u32 tdma_no_sync: 1;$/;"	m	struct:rtw89_btc_dm_emap
tdma_now	core.h	/^	struct rtw89_btc_fbtc_tdma tdma_now;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_fbtc_tdma
tgt_ind	core.h	/^	u8 tgt_ind;$/;"	m	struct:rtw89_vif
ther_dpk	core.h	/^	u8 ther_dpk;$/;"	m	struct:rtw89_dpk_bkup_para
thermal	core.h	/^	u8 thermal[RF_PATH_MAX];$/;"	m	struct:rtw89_tssi_info
thermal	core.h	/^	u8 thermal[RTW89_IQK_PATH_NR];$/;"	m	struct:rtw89_iqk_info
thermal_rek_en	core.h	/^	bool thermal_rek_en;$/;"	m	struct:rtw89_iqk_info
thermal_trim	core.h	/^	u8 thermal_trim[RF_PATH_MAX];$/;"	m	struct:rtw89_power_trim_info
tia_gain	core.h	/^	s8 *tia_gain;$/;"	m	struct:rtw89_dig_info
tia_gain_a	core.h	/^	s8 tia_gain_a[TIA_GAIN_NUM];$/;"	m	struct:rtw89_dig_info
tia_gain_g	core.h	/^	s8 tia_gain_g[TIA_GAIN_NUM];$/;"	m	struct:rtw89_dig_info
tia_idx	core.h	/^	u8 tia_idx;$/;"	m	struct:rtw89_agc_gaincode_set
tid_indicate	core.h	/^	bool tid_indicate;$/;"	m	struct:rtw89_tx_desc_info
timeout	core.h	/^	u32 timeout: 1;$/;"	m	struct:rtw89_btc_bt_rfk_info
tma	core.h	/^	u8 tma[ETH_ALEN];$/;"	m	struct:rtw89_addr_cam_entry
tmac_init	mac.c	/^static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
tmax_a2dp	coex.c	/^	u16 tmax_a2dp[CXT_FLCTRL_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tmax_a2dp	core.h	/^	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; \/* max a2dp PSTDMA\/TDMA time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tmax_a2dpept	coex.c	/^	u16 tmax_a2dpept;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tmax_a2dpept	core.h	/^	__le16 tmax_a2dpept; \/* max a2dp empty time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tmax_cycle	coex.c	/^	u16 tmax_cycle[CXT_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tmax_cycle	core.h	/^	__le16 tmax_cycle[CXT_MAX]; \/* max wl\/bt cycle time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tmax_lk	coex.c	/^	u16 tmax_lk;$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tmax_lk	core.h	/^	__le16 tmax_lk; \/* max leak-slot time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
tmaxdiff_cycle	coex.c	/^	u16 tmaxdiff_cycle[CXT_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tmaxdiff_cycle	core.h	/^	__le16 tmaxdiff_cycle[CXT_MAX]; \/* max wl-wl bt-bt cycle diff time *\/$/;"	m	struct:rtw89_btc_fbtc_cysta
to_self	core.h	/^	bool to_self;$/;"	m	struct:rtw89_rx_phy_ppdu
total_len	fw.h	/^	u8 total_len:4;$/;"	m	struct:rtw89_h2creg_sch_tx_en
total_sta_assoc	core.h	/^	u8 total_sta_assoc;$/;"	m	struct:rtw89_dev
trace_step	core.h	/^	u32 trace_step: 16;$/;"	m	struct:rtw89_btc_ctrl
track_work	core.h	/^	struct delayed_work track_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
traffic	core.h	/^	struct rtw89_traffic_stats traffic;$/;"	m	struct:rtw89_btc_statistic	typeref:struct:rtw89_btc_statistic::rtw89_traffic_stats
traffic_dir	core.h	/^	u32 traffic_dir : 2;$/;"	m	struct:rtw89_btc_wl_smap
trigger	core.h	/^	bool trigger;$/;"	m	struct:rtw89_vif
trx_lock	pci.h	/^	spinlock_t trx_lock;$/;"	m	struct:rtw89_pci
trx_para_level	core.h	/^	u32 trx_para_level: 8;$/;"	m	struct:rtw89_btc_dm
trx_path_selection	rtw8852a.h	/^	u8 trx_path_selection;$/;"	m	struct:rtw8852a_efuse
trxptcl_init	mac.c	/^static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)$/;"	f	file:
tsftr_h	core.h	/^	u32 tsftr_h;$/;"	m	struct:rtw89_port_reg
tsftr_l	core.h	/^	u32 tsftr_l;$/;"	m	struct:rtw89_port_reg
tslot_cycle	coex.c	/^	u16 tslot_cycle[BTC_CYCLE_SLOT_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta_cpu	file:
tslot_cycle	core.h	/^	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];$/;"	m	struct:rtw89_btc_fbtc_cysta
tssi	core.h	/^	struct rtw89_tssi_info tssi;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::rtw89_tssi_info
tssi_cck	core.h	/^	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];$/;"	m	struct:rtw89_tssi_info
tssi_mcs	core.h	/^	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];$/;"	m	struct:rtw89_tssi_info
tssi_tracking_check	core.h	/^	bool tssi_tracking_check[RF_PATH_MAX];$/;"	m	struct:rtw89_tssi_info
tssi_trim	core.h	/^	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];$/;"	m	struct:rtw89_tssi_info
tx	mac.h	/^	u8 tx;$/;"	m	struct:rtw89_mac_ax_plt
tx_3m	coex.c	/^	u8 tx_3m: 1;$/;"	m	struct:btc_btinfo_hb3	file:
tx_3m	core.h	/^	u32 tx_3m: 1;$/;"	m	struct:rtw89_btc_bt_link_info
tx_acked	pci.h	/^	u64 tx_acked;$/;"	m	struct:rtw89_pci_tx_ring
tx_avg_len	core.h	/^	u32 tx_avg_len;$/;"	m	struct:rtw89_traffic_stats
tx_bb_swing_2g	rtw8852a.h	/^	u8 tx_bb_swing_2g;$/;"	m	struct:rtw8852a_efuse
tx_bb_swing_5g	rtw8852a.h	/^	u8 tx_bb_swing_5g;$/;"	m	struct:rtw8852a_efuse
tx_cali_pwr_trk_mode	rtw8852a.h	/^	u8 tx_cali_pwr_trk_mode;$/;"	m	struct:rtw8852a_efuse
tx_cnt	core.h	/^	u64 tx_cnt;$/;"	m	struct:rtw89_traffic_stats
tx_cnt	pci.h	/^	u64 tx_cnt;$/;"	m	struct:rtw89_pci_tx_ring
tx_cnt	rtw8852a.h	/^	u16 tx_cnt;$/;"	m	struct:rtw8852a_bb_pmac_info
tx_diversity	rtw8852a.h	/^	u8 tx_diversity:1;$/;"	m	struct:rtw8852a_efuse
tx_en	core.h	/^	u16 tx_en;$/;"	m	struct:rtw89_channel_help_params
tx_en	fw.h	/^	u16 tx_en:16;$/;"	m	struct:rtw89_h2creg_sch_tx_en
tx_ewma_tp	core.h	/^	struct ewma_tp tx_ewma_tp;$/;"	m	struct:rtw89_traffic_stats	typeref:struct:rtw89_traffic_stats::ewma_tp
tx_kick_off	core.h	/^	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);$/;"	m	struct:rtw89_hci_ops
tx_life_time	pci.h	/^	u64 tx_life_time;$/;"	m	struct:rtw89_pci_tx_ring
tx_lvl	core.h	/^	u16 tx_lvl;$/;"	m	struct:rtw89_btc_wl_active_role
tx_mac_id_drop	pci.h	/^	u64 tx_mac_id_drop;$/;"	m	struct:rtw89_pci_tx_ring
tx_nss	core.h	/^	u8 tx_nss;$/;"	m	struct:rtw89_chip_info
tx_nss	core.h	/^	u8 tx_nss;$/;"	m	struct:rtw89_hal
tx_nss	fw.h	/^	u32 tx_nss:8;$/;"	m	struct:rtw89_c2h_phy_cap
tx_params	core.h	/^	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];$/;"	m	struct:rtw89_vif	typeref:struct:rtw89_vif::ieee80211_tx_queue_params
tx_pwr_freerun	core.h	/^	u32 tx_pwr_freerun;$/;"	m	struct:rtw89_btc_rf_para
tx_pwr_perpkt	core.h	/^	u32 tx_pwr_perpkt;$/;"	m	struct:rtw89_btc_rf_para
tx_rate	core.h	/^	u16 tx_rate;$/;"	m	struct:rtw89_btc_wl_active_role
tx_rate	core.h	/^	u16 tx_rate;$/;"	m	struct:rtw89_traffic_stats
tx_retry	coex.c	/^	u8 tx_retry;$/;"	m	struct:rtw89_txtime_data	file:
tx_retry	core.h	/^	u16 tx_retry;$/;"	m	struct:rtw89_btc_wl_tx_limit_para
tx_retry	core.h	/^	u8 tx_retry;$/;"	m	struct:rtw89_btc_wl_link_info
tx_retry_lmt	pci.h	/^	u64 tx_retry_lmt;$/;"	m	struct:rtw89_pci_tx_ring
tx_rings	pci.h	/^	struct rtw89_pci_tx_ring tx_rings[RTW89_TXCH_NUM];$/;"	m	struct:rtw89_pci	typeref:struct:rtw89_pci::rtw89_pci_tx_ring
tx_tfc_lv	core.h	/^	enum rtw89_tfc_lv tx_tfc_lv;$/;"	m	struct:rtw89_traffic_stats	typeref:enum:rtw89_traffic_stats::rtw89_tfc_lv
tx_throughput	core.h	/^	u32 tx_throughput;$/;"	m	struct:rtw89_traffic_stats
tx_throughput_raw	core.h	/^	u32 tx_throughput_raw;$/;"	m	struct:rtw89_traffic_stats
tx_time	coex.c	/^	u32 tx_time;$/;"	m	struct:rtw89_txtime_data	file:
tx_time	core.h	/^	u32 tx_time;	\/* unit: us *\/$/;"	m	struct:rtw89_btc_wl_tx_limit_para
tx_time	core.h	/^	u32 tx_time;$/;"	m	struct:rtw89_btc_wl_link_info
tx_time	rtw8852a.h	/^	u16 tx_time;$/;"	m	struct:rtw8852a_bb_pmac_info
tx_type	core.h	/^	enum rtw89_core_tx_type tx_type;$/;"	m	struct:rtw89_core_tx_request	typeref:enum:rtw89_core_tx_request::rtw89_core_tx_type
tx_unicast	core.h	/^	u64 tx_unicast;$/;"	m	struct:rtw89_traffic_stats
tx_write	core.h	/^	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);$/;"	m	struct:rtw89_hci_ops
txagc_dpk	core.h	/^	u8 txagc_dpk;$/;"	m	struct:rtw89_dpk_bkup_para
txch	pci.h	/^	u8 txch;$/;"	m	struct:rtw89_pci_tx_ring
txpause	core.h	/^	u8 txpause;$/;"	m	struct:rtw89_btc_fbtc_tdma
txpwr_ent	debug.c	/^struct txpwr_ent {$/;"	s	file:
txpwr_factor_mac	core.h	/^	u8 txpwr_factor_mac;$/;"	m	struct:rtw89_chip_info
txpwr_factor_rf	core.h	/^	u8 txpwr_factor_rf;$/;"	m	struct:rtw89_chip_info
txpwr_factor_sar	sar.h	/^	u8 txpwr_factor_sar;$/;"	m	struct:rtw89_sar_handler
txpwr_lmt_2g	core.h	/^	const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]$/;"	m	struct:rtw89_chip_info
txpwr_lmt_5g	core.h	/^	const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]$/;"	m	struct:rtw89_chip_info
txpwr_lmt_ru_2g	core.h	/^	const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]$/;"	m	struct:rtw89_chip_info
txpwr_lmt_ru_5g	core.h	/^	const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]$/;"	m	struct:rtw89_chip_info
txpwr_map	debug.c	/^struct txpwr_map {$/;"	s	file:
txpwr_regd	core.h	/^	u8 txpwr_regd[RTW89_BAND_MAX];$/;"	m	struct:rtw89_regulatory
txq_reinvoke_work	core.h	/^	struct delayed_work txq_reinvoke_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::delayed_work
txq_work	core.h	/^	struct work_struct txq_work;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::work_struct
txq_wq	core.h	/^	struct workqueue_struct *txq_wq;$/;"	m	struct:rtw89_dev	typeref:struct:rtw89_dev::workqueue_struct
txrate	core.h	/^	struct rate_info txrate;$/;"	m	struct:rtw89_ra_report	typeref:struct:rtw89_ra_report::rate_info
txt	debug.c	/^	const char *txt;$/;"	m	struct:txpwr_ent	file:
type	coex.c	/^	int type;$/;"	m	struct:rtw89_txtime_data	file:
type	coex.c	/^	u8 type;$/;"	m	struct:rtw89_btc_btf_tlv	file:
type	coex.c	/^	u8 type;$/;"	m	struct:rtw89_btc_prpt	file:
type	core.h	/^	__le16 type;$/;"	m	struct:rtw89_btc_fbtc_mreg
type	core.h	/^	enum rtw89_hci_type type;$/;"	m	struct:rtw89_hci_info	typeref:enum:rtw89_hci_info::rtw89_hci_type
type	core.h	/^	u32 type: 1;$/;"	m	struct:rtw89_btc_bt_pan_desc
type	core.h	/^	u32 type: 2;$/;"	m	struct:rtw89_btc_bt_hfp_desc
type	core.h	/^	u32 type: 8;$/;"	m	struct:rtw89_btc_bt_hid_desc
type	core.h	/^	u32 type: 8;$/;"	m	struct:rtw89_btc_wl_rfk_info
type	core.h	/^	u8 type : 4;$/;"	m	struct:rtw89_sec_cam_entry
type	core.h	/^	u8 type: 3;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
type	core.h	/^	u8 type;   \/* 0: none, 1:zigbee, 2:LTE  *\/$/;"	m	struct:rtw89_btc_3rdcx_info
type	core.h	/^	u8 type;  \/* shared, dedicated *\/$/;"	m	struct:rtw89_btc_ant_info
type	core.h	/^	u8 type;$/;"	m	struct:rtw89_btc_fbtc_step
type	core.h	/^	u8 type;$/;"	m	struct:rtw89_btc_fbtc_tdma
type	fw.h	/^	u8 type; \/* enum rtw89_fw_type *\/$/;"	m	struct:rtw89_mfw_info
type	mac.h	/^	enum rtw89_mac_dle_ctrl_type type;$/;"	m	struct:rtw89_mac_dle_dfi_ctrl	typeref:enum:rtw89_mac_dle_dfi_ctrl::rtw89_mac_dle_ctrl_type
u	rtw8852a.h	/^		struct rtw8852au_efuse u;$/;"	m	union:rtw8852a_efuse::__anon6	typeref:struct:rtw8852a_efuse::__anon6::rtw8852au_efuse
unlnk_pge_num	core.h	/^	u16 unlnk_pge_num;$/;"	m	struct:rtw89_dle_size
upd_all	core.h	/^	u8 upd_all:1;$/;"	m	struct:rtw89_ra_info
upd_bw_nss_mask	core.h	/^	u8 upd_bw_nss_mask:1;$/;"	m	struct:rtw89_ra_info
upd_mask	core.h	/^	u8 upd_mask:1;$/;"	m	struct:rtw89_ra_info
update_map	core.h	/^	__le32 update_map;$/;"	m	struct:rtw89_btc_fbtc_slots
update_policy_force	core.h	/^	bool update_policy_force;$/;"	m	struct:rtw89_btc
update_slot_map	core.h	/^	u32 update_slot_map;$/;"	m	struct:rtw89_btc_dm
use_cfg_mask	core.h	/^	bool use_cfg_mask;$/;"	m	struct:rtw89_sta
use_pgnum	mac.h	/^	u16 use_pgnum;$/;"	m	struct:rtw89_mac_dle_dfi_quota
use_rate	core.h	/^	bool use_rate;$/;"	m	struct:rtw89_tx_desc_info
used	core.h	/^	u16 used;$/;"	m	struct:rtw89_hfc_ch_info
user_id	core.h	/^	u8 user_id;$/;"	m	struct:rtw89_rx_desc_info
vaddr	pci.h	/^	void *vaddr;$/;"	m	struct:rtw89_pci_tx_wd
val	coex.c	/^	u8 val;$/;"	m	union:btc_btinfo	file:
val	coex.c	/^	u8 val[1];$/;"	m	struct:rtw89_btc_btf_tlv	file:
val	core.h	/^	u16 val;$/;"	m	union:rtw89_btc_wl_role_info_map
val	core.h	/^	u32 val;$/;"	m	union:rtw89_btc_bt_rfk_info_map
val	core.h	/^	u32 val;$/;"	m	union:rtw89_btc_bt_state_map
val	core.h	/^	u32 val;$/;"	m	union:rtw89_btc_dm_error_map
val	core.h	/^	u32 val;$/;"	m	union:rtw89_btc_wl_state_map
val	core.h	/^	u8 val;$/;"	m	struct:rtw89_btc_fbtc_step
val	core.h	/^	u8 val;$/;"	m	union:rtw89_btc_fbtc_rxflct
val	mac.h	/^	u8 val;$/;"	m	struct:rtw89_pwr_cfg
valid	core.h	/^	bool valid;$/;"	m	struct:rtw89_efuse
valid	core.h	/^	bool valid;$/;"	m	struct:rtw89_rx_phy_ppdu
valid	core.h	/^	u8 valid	: 1;$/;"	m	struct:rtw89_addr_cam_entry
valid	core.h	/^	u8 valid : 1;$/;"	m	struct:rtw89_bssid_cam_entry
valid	core.h	/^	u8 valid;$/;"	m	struct:rtw89_btc_rpt_cmn_info
vap	core.h	/^	u16 vap: 1;$/;"	m	struct:rtw89_btc_wl_role_info_bpos
vendor_id	core.h	/^	__le16 vendor_id;$/;"	m	struct:rtw89_btc_fbtc_btdevinfo
vendor_id	core.h	/^	u16 vendor_id;$/;"	m	struct:rtw89_btc_bt_a2dp_desc
ver_info	core.h	/^	struct rtw89_btc_bt_ver_info ver_info;$/;"	m	struct:rtw89_btc_bt_info	typeref:struct:rtw89_btc_bt_info::rtw89_btc_bt_ver_info
ver_info	core.h	/^	struct rtw89_btc_wl_ver_info  ver_info;$/;"	m	struct:rtw89_btc_wl_info	typeref:struct:rtw89_btc_wl_info::rtw89_btc_wl_ver_info
version	core.h	/^	u8 version;$/;"	m	struct:rtw89_iqk_info
vif	core.h	/^	struct ieee80211_vif *vif;$/;"	m	struct:rtw89_core_tx_request	typeref:struct:rtw89_core_tx_request::ieee80211_vif
vif	mac80211.c	/^	struct ieee80211_vif *vif;$/;"	m	struct:rtw89_iter_bitrate_mask_data	typeref:struct:rtw89_iter_bitrate_mask_data::ieee80211_vif	file:
voice	coex.c	/^	u8 voice: 1;$/;"	m	struct:btc_btinfo_hb1	file:
w1_hang	core.h	/^	u32 w1_hang: 1;$/;"	m	struct:rtw89_btc_dm_emap
wait_cnt	core.h	/^	int wait_cnt;$/;"	m	struct:rtw89_txq
wapi	core.h	/^	u8 wapi		: 1;$/;"	m	struct:rtw89_addr_cam_entry
wcpu	core.h	/^	u16 wcpu;$/;"	m	struct:rtw89_ple_quota
wcpu	core.h	/^	u16 wcpu;$/;"	m	struct:rtw89_wde_quota
wd_page	core.h	/^	bool wd_page;$/;"	m	struct:rtw89_tx_desc_info
wd_rel	core.h	/^	u16 wd_rel;$/;"	m	struct:rtw89_ple_quota
wd_ring	pci.h	/^	struct rtw89_pci_tx_wd_ring wd_ring;$/;"	m	struct:rtw89_pci_tx_ring	typeref:struct:rtw89_pci_tx_ring::rtw89_pci_tx_wd_ring
wde_max_qt	core.h	/^	const struct rtw89_wde_quota *wde_max_qt;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_wde_quota
wde_min_qt	core.h	/^	const struct rtw89_wde_quota *wde_min_qt;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_wde_quota
wde_pg_size	core.h	/^	u16 wde_pg_size;$/;"	m	struct:rtw89_dle_info
wde_qt0	mac.c	/^const struct rtw89_wde_quota wde_qt0 = {$/;"	v	typeref:struct:rtw89_wde_quota
wde_qt4	mac.c	/^const struct rtw89_wde_quota wde_qt4 = {$/;"	v	typeref:struct:rtw89_wde_quota
wde_quota_cfg	mac.c	/^static void wde_quota_cfg(struct rtw89_dev *rtwdev,$/;"	f	file:
wde_size	core.h	/^	const struct rtw89_dle_size *wde_size;$/;"	m	struct:rtw89_dle_mem	typeref:struct:rtw89_dle_mem::rtw89_dle_size
wde_size0	mac.c	/^const struct rtw89_dle_size wde_size0 = {$/;"	v	typeref:struct:rtw89_dle_size
wde_size4	mac.c	/^const struct rtw89_dle_size wde_size4 = {$/;"	v	typeref:struct:rtw89_dle_size
whql_test	core.h	/^	u32 whql_test: 1;$/;"	m	struct:rtw89_btc_bt_info
wifi_role	core.h	/^	u8 wifi_role;$/;"	m	struct:rtw89_vif
win	core.h	/^	u16 win;$/;"	m	struct:rtw89_btc_bt_scan_info
wl	core.h	/^	struct rtw89_btc_wl_info wl;$/;"	m	struct:rtw89_btc_cx	typeref:struct:rtw89_btc_cx::rtw89_btc_wl_info
wl_btg_rx	core.h	/^	u32 wl_btg_rx: 1;$/;"	m	struct:rtw89_btc_dm
wl_func	fw.h	/^	u32 wl_func:8;$/;"	m	struct:rtw89_c2h_phy_cap
wl_fw_coex_ver	core.h	/^	u32 wl_fw_coex_ver; \/* match which driver's coex version *\/$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
wl_fw_cx_offload	core.h	/^	u32 wl_fw_cx_offload: 1;$/;"	m	struct:rtw89_btc_dm
wl_fw_cx_offload	core.h	/^	u32 wl_fw_cx_offload;$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
wl_fw_hang	core.h	/^	u32 wl_fw_hang: 1;$/;"	m	struct:rtw89_btc_dm_emap
wl_fw_ver	core.h	/^	u32 wl_fw_ver;$/;"	m	struct:rtw89_btc_fbtc_rpt_ctrl
wl_guard_ch	core.h	/^	u8 wl_guard_ch;$/;"	m	struct:rtw89_btc_init_info
wl_hd_iv_len	core.h	/^	u8 wl_hd_iv_len;$/;"	m	struct:rtw89_rx_desc_info
wl_init_ok	core.h	/^	u8 wl_init_ok: 1;$/;"	m	struct:rtw89_btc_init_info
wl_mimo_ps	core.h	/^	u32 wl_mimo_ps: 1;$/;"	m	struct:rtw89_btc_dm
wl_only	core.h	/^	u32 wl_only: 1;$/;"	m	struct:rtw89_btc_dm
wl_only	core.h	/^	u8 wl_only: 1;$/;"	m	struct:rtw89_btc_init_info
wl_ps_ctrl	core.h	/^	u32 wl_ps_ctrl: 2;$/;"	m	struct:rtw89_btc_dm
wl_rfk_timeout	core.h	/^	u32 wl_rfk_timeout: 1;$/;"	m	struct:rtw89_btc_dm_emap
wl_rssi_thres	core.h	/^	const u8 *wl_rssi_thres;$/;"	m	struct:rtw89_chip_info
wl_rx_gain	core.h	/^	u32 wl_rx_gain;  \/* rx gain table index (TBD.) *\/$/;"	m	struct:rtw89_btc_rf_trx_para
wl_slot_drift	core.h	/^	u32 wl_slot_drift: 1;$/;"	m	struct:rtw89_btc_dm_emap
wl_stb_chg	core.h	/^	u32 wl_stb_chg: 1;$/;"	m	struct:rtw89_btc_dm
wl_tx_limit	core.h	/^	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;$/;"	m	struct:rtw89_btc_dm	typeref:struct:rtw89_btc_dm::rtw89_btc_wl_tx_limit_para
wl_tx_power	core.h	/^	u32 wl_tx_power; \/* absolute Tx power (dBm), 0xff-> no BTC control *\/$/;"	m	struct:rtw89_btc_rf_trx_para
wlcx_desired	core.h	/^	u32 wlcx_desired;$/;"	m	struct:rtw89_chip_info
wmm	core.h	/^	u8 wmm;$/;"	m	struct:rtw89_vif
wowlan	core.h	/^	struct rtw89_fw_suit wowlan;$/;"	m	struct:rtw89_fw_info	typeref:struct:rtw89_fw_info::rtw89_fw_suit
wowlan_magic	core.h	/^	bool wowlan_magic;$/;"	m	struct:rtw89_vif
wowlan_pattern	core.h	/^	bool wowlan_pattern;$/;"	m	struct:rtw89_vif
wowlan_uc	core.h	/^	bool wowlan_uc;$/;"	m	struct:rtw89_vif
wp	pci.h	/^	u32 wp; \/* host idx *\/$/;"	m	struct:rtw89_pci_dma_ring
wp_aval	core.h	/^	u16 wp_aval;$/;"	m	struct:rtw89_hfc_pub_info
wp_ch07_full_cond	core.h	/^	u8 wp_ch07_full_cond;$/;"	m	struct:rtw89_hfc_prec_cfg
wp_ch07_prec	core.h	/^	u16 wp_ch07_prec;$/;"	m	struct:rtw89_hfc_prec_cfg
wp_ch811_full_cond	core.h	/^	u8 wp_ch811_full_cond;$/;"	m	struct:rtw89_hfc_prec_cfg
wp_ch811_prec	core.h	/^	u16 wp_ch811_prec;$/;"	m	struct:rtw89_hfc_prec_cfg
wp_offset	core.h	/^	u8 wp_offset;$/;"	m	struct:rtw89_tx_desc_info
wp_thrd	core.h	/^	u16 wp_thrd;$/;"	m	struct:rtw89_hfc_pub_cfg
write16	core.h	/^	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);$/;"	m	struct:rtw89_hci_ops
write32	core.h	/^	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);$/;"	m	struct:rtw89_hci_ops
write8	core.h	/^	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);$/;"	m	struct:rtw89_hci_ops
write_rf	core.h	/^	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,$/;"	m	struct:rtw89_chip_ops
wtgle_n	core.h	/^	u8 wtgle_n;$/;"	m	struct:rtw89_btc_fbtc_tdma
x_cap_ofst	core.h	/^	s8 x_cap_ofst;$/;"	m	struct:rtw89_cfo_tracking_info
xtal_cap	core.h	/^	u8 xtal_cap;$/;"	m	struct:rtw89_efuse
xtal_k	rtw8852a.h	/^	u8 xtal_k;$/;"	m	struct:rtw8852a_efuse
